WO2004042622A1

WO2004042622A1 - Semiconductor integrated circuit development method and semiconductor integrated circuit development support program

Info

Publication number: WO2004042622A1
Application number: PCT/JP2003/014191
Authority: WO
Inventors: Hitoshi Sugihara; Toshiyuki Usui; Hiroaki Sugimoto
Original assignee: Renesas Technology Corp.; Hitachi Engineering Co., Ltd.
Priority date: 2002-11-08
Filing date: 2003-11-07
Publication date: 2004-05-21
Also published as: AU2003277604A1; AU2003277604A8

Abstract

A semiconductor integrated circuit development method includes an analog circuit design support processing and a layout design support processing for the analog circuit. The circuit design support processing includes an attribute batch specification processing for specifying in batch mode a layout attribute for each of circuit elements of a plurality of types constituting the analog circuit. The layout design support processing inputs the layout attribute specified by the attribute batch specification processing and reflects the layout attribute concerning the circuit element when performing the circuit element layout. With the batch specification of the layout attribute, it is possible to save the energy required for assigning the same layout restriction to the identical type of circuit elements separately. Since the layout restriction is performed in the circuit design stage, it is possible to decide the layout restriction while considering the relationship with the necessary circuit characteristic.

Description

SPECIFICATION Semiconductor integrated circuit development method and semiconductor integrated circuit development support program

Technical field

The present invention relates to a method for developing an analog circuit or an analog / digital mixed semiconductor integrated circuit (LSI) and a development support program for the semiconductor integrated circuit. For example, the present invention relates to an automatic layout tool for analog circuit modules, a hierarchical layer for large analog modules. Technology that is applicable to the project. Background art

In recent years, in the late design for analog circuits or analog-digital mixed semiconductor integrated circuits, the man-hour required for the late design has been remarkably increased with the increase in the scale of analog circuits. In addition, the layout design of analog circuits is a field in which automation is hardly advanced due to many manual steps, and urgent improvement was required.

In an analog module layout system that uses analog automatic layout, cell shape selection and placement / routing are performed based on layout constraints (pairs, symmetry, etc.). For example, the layout design of an analog module can be performed by the following procedure.

(1) Specify the cell size, grid, power / ground position and width, and set the outer dimensions.

(2) Set analog layout constraints on the circuit diagram.

(3) Execute automatic placement using the set analog layout constraints and parameterized cells. Multiple automatic placement results can be created, among which The user selects the most suitable one from.

(4) Automatically route the design of the selected placement result. In automatic placement, based on the analog layout constraints (module generator constraints), a shape plan (Variant) for each cell to be placed is created, and an appropriate one is automatically selected and placed from among the shape plans for each cell. The proposed cell shape is a variation of the cell shape that can be created by changing the parameter values of the parameterized cells.

Patent Document 1 (Japanese Patent Application Laid-Open No. Hei 8-246658) discloses an automatic wiring technique for improving design efficiency and area efficiency by using cells standardized for an analog circuit block. According to this, a standardized analog cell has a fixed cell height, the power supply wiring is arranged at the upper and lower ends of the cell so as to run in the horizontal direction, and the input / output wiring runs in the cell in the vertical direction. And a guard ring is arranged so as to surround the periphery. The standardized analog cell is laid out on a chip to obtain an LSI having an analog circuit block. Disclosure of the invention

The inventor has studied an automatic rate technology (a hierarchical rate method) for a large-scale analog circuit. According to this, a large number of layouts are required to obtain the required analog circuit characteristics by individually designating the size, shape, orientation, relationship with other circuit elements, and the like of the circuit elements. It takes a number. For example, the time and effort required to apply a rate constraint to each circuit element for each circuit element subject to the same rate constraint becomes enormous. On the other hand, in a system similar to the standard cell of Patent Document 1, it is considered that it is difficult to obtain required analog characteristics even if the number of layouts is reduced. An object of the present invention is to reduce the number of analog circuit man-hours. Another object of the present invention is to provide a method for developing a semiconductor integrated circuit.

Another object of the present invention is to provide a development support program that can easily support the development of a semiconductor integrated circuit with a reduced number of analog circuit layout steps.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

The following is a brief description of an outline of typical inventions disclosed in the present application.

[1] A first aspect of the present invention is a simplified input of a rate constraint. Here, the specification of layout constraints is grasped as a part of circuit design. A method for developing a semiconductor integrated circuit according to the present invention includes a circuit design support process for an analog circuit, and a rate design support process for the analog circuit. The circuit design support process includes an attribute batch designation process for batch designating a layout attribute for each of a plurality of types of circuit elements constituting the analog circuit. In the layout design support processing, the layout attributes specified in the attribute collective specification processing are input, and the layout attributes of the circuit elements are reflected when laying out the circuit elements.

The attribute collective designation process includes, for example, a process for designating a shape range of a circuit element, a process for designating a constraint on a relative arrangement of circuit elements, and a circuit when a region on the circuit diagram of the analog circuit is divided into a plurality. For example, a process of designating a restriction on the layout position of the terminal according to the division area including the terminal shown in the figure.

The batch designating process of the layout attribute can save the trouble of separately applying the same layout constraint to the same type of circuit element. In addition, since layout constraints are performed at the circuit design stage, layout constraints can be determined in consideration of the relationship with required circuit characteristics, and required circuit characteristics can be obtained. This makes it easy to set layout constraints so as not to hinder or optimize the layout. In short, by adopting the batch setting of the rate constraint, the time required for setting the rate constraint for the analog circuit can be reduced.

A second aspect of the present invention is the adoption of a hierarchical rate method. The first hierarchical layout method is a top-down hierarchical layout. That is, the rate design support processing includes inputting hierarchical circuit diagram data of the analog circuit, and converting an area of a module specified from the input hierarchical circuit diagram data into a circuit constant of a circuit element included in the module. Based on this, the shape is made into a rectangle with a variable aspect ratio, and the module is regarded as one circuit element, and the circuit elements are laid out top down. By regarding the circuit module as a rectangular circuit element whose area is estimated with a variable aspect ratio, the layout of the top-down can be made flexible. The layout of this top-down allows a layout plan to be easily created in the upper layer, which is effective for the initial stage floor plan design and the like.

The second hierarchical layout method is a bottom-up hierarchical layout. That is, the layout design support processing includes inputting hierarchical circuit diagram data of the analog circuit, performing layout of a module specified from the input hierarchical circuit data from a lower hierarchical module, and laying out a layout of the upper hierarchical module. Then, the lower layer modules already laid out are regarded as rectangular circuit elements having a variable aspect ratio, and the circuit elements are laid out from the bottom up. This bottom-up hierarchical layout method estimates the module area by actually laying out circuit elements, and is therefore effective at the final stage of floor blank design and module layout execution.

In this way, the layout processing of the analog circuit employs a module P-cell having a variable aspect ratio with an estimated area, and a hierarchical layout. By adopting the method (top-down, bottom-up), it is possible to increase the efficiency of analog circuit layout.

[2] The specification of the rate constraint may be grasped separately from the circuit design. A method for developing a semiconductor integrated circuit from this viewpoint includes a process of inputting hierarchical circuit diagram data of an analog circuit and supporting a hierarchical layout design of the analog circuit. In the support processing, a layout attribute collectively designated for each circuit element is input to a plurality of types of circuit elements constituting the analog circuit, and a layout attribute of the circuit element is reflected when laying out the circuit element.

The layout attributes include restrictions on the shape range of the circuit element, restrictions on the relative arrangement of the circuit element, and the like. The terminal layout is divided into a plurality of circuit diagram regions of the module for which the hierarchical layout is specified from the input hierarchical circuit diagram of the analog circuit, and the terminal layout is determined according to where the terminals of the circuit diagram fall into the divided regions. May be performed.

By collectively specifying the layout attributes, it is possible to eliminate the need to separately apply the same layout constraints to the same type of circuit element.

[3] The hierarchical rate method may be understood separately from the circuit design. A method of developing a semiconductor integrated circuit from this viewpoint includes a process of inputting hierarchical circuit diagram data of an analog circuit and supporting a hierarchical layout design of the analog circuit. When a top-down hierarchical layout is adopted, the supporting process estimates an area of a module specified from the input hierarchical circuit diagram data of the analog circuit based on a circuit constant of a circuit element included in the module, The shape is defined as a rectangle with a variable aspect ratio, and the module is regarded as one circuit element, and the circuit elements are laid out in a top-down manner.

When the bottom-up hierarchical layout is adopted, the supporting process includes: The hierarchical circuit data of the analog circuit is input, the layout of the module specified from the input hierarchical circuit data of the analog circuit is performed from the lower hierarchical module, and the layout of the upper hierarchical module is already the layout. The lower-layer module thus determined is regarded as a rectangular circuit element having a variable aspect ratio, and the circuit elements are laid out from the bottom up.

[4] An invention according to yet another aspect is a development support program for causing a computer device to execute a process for supporting a hierarchical layout design of an analog circuit. As the supporting process, the layout constraint is specified collectively, the top-down hierarchical layout or the bottom-up hierarchical layout is performed. By executing this development support program, it becomes possible to easily develop a semiconductor integrated circuit with a reduced number of analog circuit layout steps. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is an explanatory diagram illustrating an outline of a development system used in a method of developing a semiconductor integrated circuit according to the present invention.

FIG. 2 is an explanatory diagram of an input screen for collectively specifying device style constraints.

FIG. 3 is an explanatory diagram of area division for collectively specifying pin style constraints.

FIG. 4 is an explanatory view of an input screen for designating a metal wiring layer constituting a terminal assigned to each of the four sides.

FIG. 5 is an explanatory diagram of an input screen for collectively specifying the arrangement positions of circuit elements.

FIG. 6 is an explanatory diagram of an input screen that allows a layout direction to be designated collectively for each element type. FIG. 4 is an explanatory diagram of the pin arrangement of the module cell.

FIG. 8 is an explanatory diagram exemplifying a manner in which an aspect ratio of a module cell is variable.

Figure 9 is a top-down hierarchical layout diagram that uses module cells for the original hierarchical layout diagram.

FIG. 10 is an explanatory diagram exemplifying a module arrangement result of the top hierarchy.

FIG. 11 is an explanatory diagram showing a wiring result between modules with respect to the module arrangement of FIG.

FIG. 12 is a flowchart illustrating a processing procedure of the bottom-up hierarchical layout processing.

FIG. 13 is an explanatory diagram of a circuit diagram hierarchical structure in which the highest hierarchy is l evel = 3 and the lowest hierarchy is l evel = l.

FIG. 14 is an explanatory diagram showing the placement and routing results in a circuit hierarchical configuration.

It is. BEST MODE FOR CARRYING OUT THE INVENTION

《Development system》

FIG. 1 illustrates an outline of a development system used in a method for developing a semiconductor integrated circuit according to the present invention.

The development system shown in the figure includes, but is not limited to, a circuit editor 1 and a layout editor 2. The circuit editor 1 and the layout editor 2 are configured by installing the circuit editor program and the layout editor program on separate computer devices or the same computer device, respectively.

Circuit Editor 1 is positioned as a circuit design tool for analog LSI In addition, the target analog circuit is hierarchized, and it assists in designing a specific circuit to satisfy the required electrical characteristics for each hierarchical module. For example, a circuit diagram can be generated according to input operations by making it possible to ascertain the size of circuit elements, circuit element drive capability, circuit element connections, timing, operating margin, and the effect on chip size. In particular, the circuit editor 1 performs, as a circuit design support process, an attribute batch designation process (layout constraint batch designation process) for batch designating layout attributes for each circuit element. The layout editor 2 inputs the hierarchical circuit diagram data 3 and the collective constraint data 4 generated in the circuit editor 1. Collective constraint data 4 is late constraint data obtained in the late constraint collective designation process. The layout editor 2 supports the layout of the specific circuit elements, that is, the placement and routing based on the input hierarchical circuit diagram data 3 and the collective constraint data 4. At this time, the layout editor 2 performs a hierarchical layout process as the layout design support process.

《Late constraint batch specification》

The late constraint batch designation process is a process for batch designating a layout attribute for each of a plurality of types of circuit elements constituting the analog circuit.

The late constraint collective designation process includes, for example, a process of designating a shape range of a circuit element, a process of designating a constraint relating to a relative arrangement of circuit elements, and a circuit diagram when an area on the circuit diagram of the analog circuit is divided into a plurality. For example, a process of designating a restriction on a layout position of a terminal according to a divided region including the terminal. This focuses on the fact that similar constraints are often specified for circuit elements of the same type, and rate constraints are collectively specified for each circuit element type. An example of rate constraint batch specification is shown below. (1) Batch specification of device style constraints

This is a process to collectively create a plan (variant) constraint for the element from information on the element constants (resistance value, etc.). It is possible to adopt a method in which the user directly specifies the shape deformation range, or a method in which the arrangement shape is automatically set so as to be a standard shape. For example, a resistance element having a resistance value close to the average of the resistance values in the circuit is adopted as a reference resistance value, and the element shape is set as a standard shape. As a specific example, if R = 2 k Q xl, R = 4 k Q xl O 0, R = 8 k Q x 20 total 1 2 1 resistor is in the circuit, the average value of the resistance value Is 4.6 kΩ, so the reference resistance value is 4 kΩ. A resistance element with R = 8 kΩ is created by folding two 4 Ω reference resistors. A resistance element with R = 4 k Q is created with one 4 Ω reference resistance. Thereby, the heights of the elements are uniform, and the gap between the elements is reduced. The type and number of the resistive elements in the circuit module may be automatically extracted from the hierarchical circuit data. Selection of the standard resistance value with respect to the average value may be automatically performed.

In the example of the support screen for rate constraint batch input in Fig. 2, the range of the minimum (M in) and the maximum (Max) for the standard size of each circuit element can be specified. Selectable circuit elements are shown in the TargetCell (s) column. As shown in the figure, the state in which the display of the circuit element name is inverted between white and black means that the circuit element is selected. For example, in the figure, MN is an N-channel MOS transistor, MP is a P-channel MOS transistor, QN is a bipolar transistor, RP is a resistor, and C CN is a capacitor. The specified minimum (M in) and maximum (Max) values for the circuit elements MN and MP mean the gate width.

(2) Batch specification of pin style constraints

This is done by dividing the outline of the symbol or circuit diagram into four, for example, diagonally, This is a process of collectively creating restrictions on the sides where the is placed. For example, taking the circuit of Fig. 3 as an example, the terminals IN 1, IN 2, V ref and ø in the area E 1 are located on the left side of the module, and the terminals OUT 1, OUT 2 and The restriction that ø / is on the right side of the module, the terminal GND in area # 3 is on the upper side of the module, and the terminal VCC in area # 4 is on the lower side of the module is restricted. For the terminals on the diagonal line, for example, assign the optimal one in the order of left, right, top, and bottom. The division area into which the terminal enters can be automatically determined from the relationship between the coordinates of the terminal on the circuit diagram and the vertex coordinates of the division area. The position of the terminal may be grasped at the position of the center of gravity.

FIG. 4 shows an example of an input screen for designating a metal wiring layer constituting a terminal assigned to each of the four sides. In FIG. 4, Top Pin indicates a terminal arranged on the top side, Bottom Pin indicates a terminal arranged on the bottom side, Left Pin indicates a terminal arranged on the left side, and Right Pin indicates a terminal arranged on the right side.

(3) Batch designation of circuit element placement positions

This is a process for creating restrictions on the arrangement of the top, bottom, etc. for each element type at once. For example, in the CMOS circuit, a P-channel MOS transistor is placed at the top, and an N-channel MOS transistor is placed at the bottom. Fig. 5 shows an example of an input screen that allows the layout position to be specified collectively for each element type. In the figure, the circuit element can be selected from the column of Cel l (s), and the layout position can be selected from the column of Soft Box. Top means upper side.

(4) Batch designation of circuit element placement direction

This is a process for collectively creating restrictions on the arrangement direction, such as rotation control, inversion, and the like, for each circuit element type. For example, when there is an offset in the arrangement of the gate electrode with respect to the source and drain, reversal and rotation are prohibited. Such restrictions on the placement direction are collectively specified. Fig. 6 shows an example of an input screen that allows the layout direction to be specified collectively for each element type. In the figure, the circuit element should be selected from the column of Cell (s), and the placement direction to be prohibited should be selected from the column of Orient (s). R 180 means 180 degree rotation, MX means mirror inversion with respect to X axis, and MXR 90 means 90 degree rotation after mirror inversion with respect to X axis.

(5) Batch specification of proximity placement constraints

This is a process to specify Group Form constraints (constrained placement constraints) for a group of devices with a common board node (eg, a board node at the MOS transistor). For example, specify the restrictions on the proximity arrangement such as forming an N-channel MOS transistor in the P-type well region o

Other restrictions that can be specified collectively include terminal distance restrictions, terminal symmetry restrictions, wiring width and wiring layer restrictions, wiring topology restrictions, wiring prohibited area crosstalk restrictions, and wiring electrical crosstalk restrictions. There is. According to the batch designating process of the layout constraints, it is possible to reduce the time required to specify the layout constraints. For example, it took about 5 hours to input a rate constraint for each element to an operational amplifier circuit (60 elements), but the batch constraint specification can reduce the processing time to about 0.5 hours. It has become possible.

《Module P cell》

The module P cell used for the hierarchical rate processing will be described. The module P-cell is a parameterized cell (P-Ce 11) that can freely change the aspect ratio with a constant area (holding) to create a module shape proposal. A module can be understood as a functional unit of any hierarchical level specified in the hierarchical circuit diagram. O

The pin arrangement of the module P-cell is set based on the circuit diagram of the module (top level) or the circuit diagram symbol (middle level). This is because the pin arrangement by these is often the same as the pin arrangement in the layout design. As shown in Fig. 7, the pin arrangement of the module P-cell can be initialized using the relative position (ratio to the external shape) from the pin arrangement of the circuit diagram symbol. In FIG. 7, 10 is a circuit diagram symbol, and 11 is a module P cell.

The area estimation for the module P cell is performed in the following procedure. As a first step, the area of each circuit element constituting the module of the hierarchy is calculated from the element constant value. For example, in the case of a resistive element, the area is estimated based on the resistance value, and in the case of the MOS transistor, the area is estimated based on the gate width (W) and the gate length (L). As a second step, the process of step 1 is executed for all elements in the lower layer of the module, and the total area is calculated. As a third step, the total area obtained in steps 1 and 2 above is multiplied by a coefficient, taking into account the power supply, the space between elements, and the like, to obtain the area of the module. The module P cell can be regarded as one rectangular circuit cell having a variable aspect ratio as illustrated in FIG.

<< Top down hierarchy layout processing >>

A top-down hierarchical layout process, which is one of the hierarchical layout processes, will be described. In the top-down hierarchical layout processing, hierarchical circuit data of an analog circuit is input, and an area of a module specified from the input hierarchical circuit data is estimated based on circuit constants of circuit elements included in the module. The shape is a rectangle with a variable aspect ratio, and the module (module P cell) is regarded as one circuit element, and the circuit elements are laid out in a top-down manner. Ask circuit module The flexibility of the top-down layout can be increased by considering the rectangular circuit element whose area is estimated with variable gate ratio. With this top-down layout, a layout plan can be easily created in the upper layer, which is effective for floor-blank design in the initial stage.

The top-down hierarchy rate processing will be described more specifically. The top-down hierarchy layout process is performed in the following procedure.

(1) As step 1, create a module P-cell for each analog module in the top level (top level) circuit diagram.

(2) As a step 2, copy the top hierarchical schematic (original) to the top-down hierarchical layout drawing. As a result, the hierarchy information of the original circuit diagram can be saved (operation option).

(3) In step 3, change the analog module reference in the top-down hierarchical layout drawing to the module P-cell. FIG. 9 exemplifies a top-down hierarchical layout diagram using module P-cells with respect to the original hierarchical layout diagram.

(4) As step 4, specify layout constraints (aspect ratio, placement position, etc.) for each module P-cell.

(5) As step 5, analog automatic layout DA (design method) For example, layout (automatic placement / wiring) using NeoCell (registered trademark), an analog cell level placement and routing tool of Soliton Systems Co., Ltd. ). The inputs at this time are the hierarchical layout drawing, the architecture of the top hierarchical layout (area, pin position, etc.), and the layout constraints specified collectively. The output is the placement / wiring result of the analog module. At this time, if there is an analog basic element in this layer, the P cell (parameterized cell) of that circuit element is used. This allows the analog module and the basic Allows for mixed elements and eliminates restrictions on hierarchical structure. FIG. 10 exemplifies the result of module placement in the top hierarchy, and FIG. 11 shows the result of inter-module wiring for the module placement in FIG.

(6) As step 6, each analog module obtained in step 5 is used as a layout top layer, and steps 1 to 5 are repeated in order from the upper layer to the lower layer, until the analog module at the lowest layer is repeated. This completes the placement / wiring of all layers.

The layout area of an analog module greatly depends on its layout constraints (target layout, target wiring, device skew reduction dummy element layout, etc.), and even with the same circuit configuration, the layout area is equal to the total area of all elements. In many cases, there is a variation of 150% or more with respect to the total area of the diffusion layers. This method can easily determine the approximate layout in a short time as compared with the bottom-up hierarchical layout method described later, and is effective for floor blank design at the initial stage of chip layout.

<< Bottom-up hierarchical layout processing >>

The second hierarchical layout method is a bottom-up hierarchical layout. In the bottom-up hierarchical layout, the hierarchical circuit data of the analog circuit is input, the layout of the module specified from the input hierarchical circuit data is performed from the lower hierarchical module, and the layout of the upper hierarchical module is as follows. The lower layer module already laid out is regarded as a rectangular circuit element having a variable aspect ratio, and the circuit elements are laid out from the bottom up. Since the bottom-up hierarchical layout method estimates the module area by actually performing the element layout, it is effective at the final stage of floor blank design and module layout execution.

The bottom-up hierarchical layout process will be described more specifically. No.

FIG. 12 illustrates a processing procedure of the bottom-up hierarchical layout processing. According to this, the bottom-up hierarchy rate processing is performed in the following procedure.

(1) As step 1, trace the drawing hierarchy from the top-level schematic and create a tree structure. Here, a hierarchical number is assigned from the leaf (leaf) of the tree structure to the root (root). The hierarchy level of the lowest schematic (leaf) is set to 1 (level = l). The hierarchical level of the intermediate hierarchical circuit (node) shall be one greater than the hierarchical level of the referenced schematic. The bottom-up hierarchy rate processing is sequentially executed from the top hierarchy, that is, from the lowest circuit diagram to the highest circuit diagram. In the circuit diagram hierarchical configuration illustrated in FIG. 13, the uppermost hierarchy is level = 3, and the lowermost hierarchy is level21.

(2) As step 2, a layout is performed for the lowest hierarchical level where no layout has been performed. That is, first, a layout constraint is input (S 1). The placement / routing is executed based on the result (S 2). For the lower rate completion hierarchy module, a module P cell is used. Create a module P cell from layout results (area, terminal position, etc.) (S3)

(3) As step 3, step 2 is repeated from the lower hierarchy to the uppermost hierarchy. This completes the layout for all layers. FIG. 14 illustrates the arrangement and wiring results in a circuit hierarchical configuration. At this time, the highest level is level = 3, and the lowest level is level = l.

In this method, although the placement / wiring engine for the analog automatic rate DA is actually executed, the processing time according to the circuit scale is required, but the accuracy of the area estimation value of the analog module in the floor plan design is high. It has become. This is because the floor blank design in the initial stage can be performed first by using the top-down hierarchical layout processing in combination. When the processing is completed, the layout of the analog module is completed. At the same time, an execution control file for placement / wiring by the analog automatic rate DA is created for each analog module. For this reason, a layout constraint can be added based on the execution result, and the final layout of the analog module can be easily completed. For the rate processing of analog circuits, module P-cells with variable area ratio with estimated area are adopted, batch setting of rate constraints is adopted, and hierarchical rate method (top-down, bottom-up) By adopting), the man-hours for layout of an analog-digital mixed LSI can be greatly improved, such as by 50%.

《Development support program》

The above-described analog circuit layout processing by the development system of FIG. 1 is realized by executing a circuit editor program and a layout editor program installed in the computer. Such a program is provided by a recording medium such as CD-ROM or a communication medium such as the Internet. By executing the program, the layout constraints are collectively specified, the top-down hierarchical layout, or the bottom-up hierarchical layout is performed as processing for supporting the hierarchical layout design of the analog circuit. By providing this development support program, it becomes possible to easily develop a semiconductor integrated circuit with a reduced number of analog circuit layout steps.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, a function of controlling the arrangement of dummy elements may be added in addition to the function of setting layout constraints in a lump. For example, the position and number of dummy elements to be added may be specified by radio buttons on the display screen. It is also possible to promote the practical use of an analog automatic rate by combining a circuit analysis with a variation analysis method as one of the rate constraint sufficiency verification means, and by starting up and combining an actual load simulation environment. This is applicable not only to analog-digital mixed (analog / digital mixed) LSI, but also to new analog module development and process migration of system-on-chip (S〇C) LSI. Industrial applicability

The present invention can be widely applied to automatic rate tools for analog circuit modules, hierarchical rates for large-scale analog modules, and the like.

Claims

The scope of the claims

1. Includes circuit design support processing for an analog circuit, and rate design support processing for the analog circuit,

The circuit design support processing includes attribute collective specification processing for collectively specifying a layout attribute for each circuit element for a plurality of types of circuit elements constituting the analog circuit,

The layout design support processing is characterized in that a layout attribute specified in the attribute batch specification processing is input, and a layout attribute of the circuit element is reflected when laying out the circuit element. Method.

2. The method for developing a semiconductor integrated circuit according to claim 1, wherein the attribute collective designation process is a process of designating a shape range of a circuit element.

3. The method for developing a semiconductor integrated circuit according to claim 1, wherein the attribute collective designation process is a process of designating a constraint on a relative arrangement of circuit elements.

4. The attribute collective designation process is characterized in that, when an area on the circuit diagram of the analog circuit is divided into a plurality of parts, a terminal position is restricted according to a divided area including a terminal of the circuit diagram. A method for developing a semiconductor integrated circuit according to claim 1.

5. The late design support processing includes inputting hierarchical circuit diagram data of the analog circuit for which a circuit is designed, and determining an area of a module specified by the input hierarchical circuit diagram data in a circuit definition of a circuit element included in the module. Estimated based on the number, the shape is made a rectangle with a variable aspect ratio, the module is regarded as one circuit element, and the circuit elements are laid out top-down. Development of the semiconductor integrated circuit according to claim 1 Method.

6. The late design support processing includes inputting a hierarchical circuit data of the analog circuit, laying out a module specified by the input hierarchical circuit data from a lower hierarchical module, and executing a layout of an upper hierarchical module. 2. The semiconductor device according to claim 1, wherein in the layout, the layout of the circuit elements is performed in a bottom-up manner, assuming that the lower layer modules already laid out are rectangular circuit elements having a variable aspect ratio. How to develop integrated circuits.

7. Includes processing to input hierarchical circuit diagram data of an analog circuit and support hierarchical layout design of the analog circuit,

In the support processing, a layout attribute collectively designated for each circuit element is input to a plurality of types of circuit elements constituting the analog circuit, and a layout attribute related to the circuit element is reflected when the circuit element is laid out A method for developing a semiconductor integrated circuit, characterized in that:

8. The method for developing a semiconductor integrated circuit according to claim 7, wherein the late attribute is a constraint on a shape range of a circuit element.

9. The method for developing a semiconductor integrated circuit according to claim 7, wherein the late attribute is a constraint on a relative arrangement of circuit elements.

10.The circuit diagram area of the hierarchical layout target module specified from the input hierarchical circuit diagram data of the analog circuit is divided into a plurality of parts, and the layout of the terminals is determined according to where the terminal of the circuit diagram is located in the divided area. 8. The method for developing a semiconductor integrated circuit according to claim 7, wherein the method is performed.

11. A process for inputting hierarchical circuit diagram data of an analog circuit and supporting a hierarchical layout design of the analog circuit,

The assisting process is performed by converting the area of a module specified from the input hierarchical circuit diagram data of the analog circuit into a circuit element included in the module. The semiconductor is characterized in that it is estimated based on the circuit constants of the elements, the shape is made into a rectangle with a variable aspect ratio, the module is regarded as one circuit element, and the circuit elements are laid out top down. How to develop integrated circuits.

12. A process for inputting hierarchical circuit diagram data of an analog circuit and supporting a hierarchical layout design of the analog circuit,

In the supporting process, the layout of the module specified by the input hierarchical circuit diagram data of the analog circuit is performed from the lower hierarchical module, and in the layout of the upper hierarchical module, the lower hierarchical module already laid out is aspected. A method of developing a semiconductor integrated circuit, characterized in that circuit elements are laid out by bottom-up, assuming that the circuit elements are variable rectangular circuit elements.

13. A semiconductor integrated circuit development support program for inputting hierarchical circuit diagram data of an analog circuit and causing a computer device to execute a process for supporting a hierarchical layout design of the analog circuit,

In the supporting process, a layout attribute collectively designated for each circuit element is input to a plurality of types of circuit elements constituting the analog circuit, and when laying out the circuit element, the layout attribute related to the circuit element is inverted. A program for supporting the development of semiconductor integrated circuits.

14. The semiconductor integrated circuit development support program according to claim 13, wherein the late attribute is a constraint on a shape range of a circuit element.

15. The semiconductor integrated circuit development support program according to claim 13, wherein the late attribute is a constraint on a relative arrangement of circuit elements.

1 6. Divide the circuit diagram area of the hierarchical layout target module specified by the input hierarchical circuit diagram data of the analog circuit into a plurality 14. The program for supporting the development of a semiconductor integrated circuit according to claim 13, wherein the terminal is laid out in accordance with where in the divided area.

17. A semiconductor integrated circuit development support program for inputting a hierarchical circuit diagram of an analog circuit and causing a computer device to execute a process for supporting a hierarchical layout design of the analog circuit,

In the supporting process, the area of a module specified by the input hierarchical circuit diagram data of the analog circuit is estimated based on the circuit constants of the circuit elements included in the module, and the shape is variable. A development support program for semiconductor integrated circuits, characterized in that the module is regarded as one circuit element and the circuit elements are laid out from the top down.

18. A semiconductor integrated circuit development support program for inputting hierarchical circuit diagram data of an analog circuit and causing a computer device to execute a process of supporting a hierarchical layout design of the analog circuit,

In the supporting process, the layout of the module specified by the input hierarchical circuit diagram data of the analog circuit is performed from the lower hierarchical module. In the layout of the upper hierarchical module, the layout of the lower hierarchical module already laid out is performed. A program for supporting the development of semiconductor integrated circuits, characterized in that circuit elements are laid out by means of bottom-up, assuming that the circuit elements are variable rectangular circuit elements.