WO2004040766A3 - Einrichtung der programmierbaren logik - Google Patents

Einrichtung der programmierbaren logik Download PDF

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Publication number
WO2004040766A3
WO2004040766A3 PCT/DE2003/003524 DE0303524W WO2004040766A3 WO 2004040766 A3 WO2004040766 A3 WO 2004040766A3 DE 0303524 W DE0303524 W DE 0303524W WO 2004040766 A3 WO2004040766 A3 WO 2004040766A3
Authority
WO
WIPO (PCT)
Prior art keywords
logic
blocks
logic device
configurable
programmable logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2003/003524
Other languages
English (en)
French (fr)
Other versions
WO2004040766A2 (de
Inventor
Christian Siemers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to JP2004547411A priority Critical patent/JP4160956B2/ja
Priority to EP03773569A priority patent/EP1554805A2/de
Priority to US10/532,643 priority patent/US7161383B2/en
Publication of WO2004040766A2 publication Critical patent/WO2004040766A2/de
Publication of WO2004040766A3 publication Critical patent/WO2004040766A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17752—Structural details of configuration resources for hot reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17756—Structural details of configuration resources for partial configuration or partial reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)

Abstract

Die Einrichtung (7) der programmierbaren Logik umfasst mehrere Logikblöcke (3A bis 3D) mit konfigurierbaren Eigenschaften und Mittel zum Verknüpfen der Logikblöcke untereinander und mit einer Verarbeitungseinheit (4) und einer Ein-/Ausgabeeinheit (5). Eine Rekonfigurierbarkeit der Logikblöcke (3A bis 3D) während des Betriebs der Logikeinrichtung (7) ist dadurch gegeben, dass die Verknüpfungsmittel zusätzlich wenigstens einen konfigurierbaren Umschalt-Logikblock (8) aufweisen, mit dem die Konfiguration wenigstens einiger der rekonfigurierbaren Logikblöcke (3A bis 3D) untereinander und/oder mit der Verarbeitungseinheit (4) und/oder der Ein-/Ausgabeeinheit (5) erfolgt.
PCT/DE2003/003524 2002-10-24 2003-10-23 Einrichtung der programmierbaren logik Ceased WO2004040766A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004547411A JP4160956B2 (ja) 2002-10-24 2003-10-23 プログラマブル論理装置
EP03773569A EP1554805A2 (de) 2002-10-24 2003-10-23 Einrichtung der programmierbaren logik
US10/532,643 US7161383B2 (en) 2002-10-24 2003-10-23 Programmable logic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10249676 2002-10-24
DE10249676.5 2002-10-24

Publications (2)

Publication Number Publication Date
WO2004040766A2 WO2004040766A2 (de) 2004-05-13
WO2004040766A3 true WO2004040766A3 (de) 2004-10-28

Family

ID=32102969

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/003524 Ceased WO2004040766A2 (de) 2002-10-24 2003-10-23 Einrichtung der programmierbaren logik

Country Status (5)

Country Link
US (1) US7161383B2 (de)
EP (1) EP1554805A2 (de)
JP (1) JP4160956B2 (de)
DE (1) DE10347975B4 (de)
WO (1) WO2004040766A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1771080B (zh) 2003-04-08 2010-12-15 诺沃挪第克公司 包括至少一个色谱处理步骤的生产治疗用多肽或其前体的方法
DE102005005073B4 (de) 2004-02-13 2009-05-07 Siemens Ag Rechnereinrichtung mit rekonfigurierbarer Architektur zur parallelen Berechnung beliebiger Algorithmen
US8612772B1 (en) 2004-09-10 2013-12-17 Altera Corporation Security core using soft key
US8566616B1 (en) * 2004-09-10 2013-10-22 Altera Corporation Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like
US20090128189A1 (en) * 2007-11-19 2009-05-21 Raminda Udaya Madurawe Three dimensional programmable devices
US8327126B2 (en) * 2008-08-25 2012-12-04 International Business Machines Corporation Multicore processor and method of use that adapts core functions based on workload execution
CA2955961A1 (en) 2014-07-28 2016-02-04 Econolite Group, Inc. Self-configuring traffic signal controller

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
WO2000069072A1 (en) * 1999-05-07 2000-11-16 Morphics Technology Inc. Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array
US20020143505A1 (en) * 2001-04-02 2002-10-03 Doron Drusinsky Implementing a finite state machine using concurrent finite state machines with delayed communications and no shared control signals

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US6346824B1 (en) * 1996-04-09 2002-02-12 Xilinx, Inc. Dedicated function fabric for use in field programmable gate arrays
US6091263A (en) * 1997-12-12 2000-07-18 Xilinx, Inc. Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
US6011740A (en) * 1998-03-04 2000-01-04 Xilinx, Inc. Structure and method for providing additional configuration memories on an FPGA
US6255848B1 (en) * 1999-04-05 2001-07-03 Xilinx, Inc. Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA
US20040004239A1 (en) * 2002-07-08 2004-01-08 Madurawe Raminda U. Three dimensional integrated circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
WO2000069072A1 (en) * 1999-05-07 2000-11-16 Morphics Technology Inc. Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array
US20020143505A1 (en) * 2001-04-02 2002-10-03 Doron Drusinsky Implementing a finite state machine using concurrent finite state machines with delayed communications and no shared control signals

Non-Patent Citations (12)

* Cited by examiner, † Cited by third party
Title
C. SIEMERS, S. WENNEKERS: "The Universal Configurable Block/Machine System - An Approach for a Homogeneous Configurable SoC-Architecture", PROCEEDINGS OF THE WORKSHOP HETEROGENEOUS RECONFIGURABLE SYSTEMS ON CHIP - SOC -, February 2002 (2002-02-01), HAMBURG, pages 1 - 6, XP002295076 *
C. SIEMERS: "Configurable Computing - Ansätze, Chancen und Herausforderungen", TAGUNGSBAND EMBEDDED WORLD 2003, February 2003 (2003-02-01), pages 631 - 648, XP002295074 *
CHIEN A A ET AL: "MORPH: a system architecture for robust high performance using customization (an NSF 100 TeraOps point design study)", FRONTIERS OF MASSIVELY PARALLEL COMPUTING, 1996. PROCEEDINGS FRONTIERS '96., SIXTH SYMPOSIUM ON THE ANNAPOLIS, MA, USA 27-31 OCT. 1996, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 27 October 1996 (1996-10-27), pages 336 - 345, XP010201607, ISBN: 0-8186-7551-9 *
DEVADAS S ET AL: "DECOMPOSITION AND FACTORIZATION OF SEQUENTIAL FINITE STATE MACHINES", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE INC. NEW YORK, US, vol. 8, no. 11, 1 November 1989 (1989-11-01), pages 1206 - 1217, XP000126892, ISSN: 0278-0070 *
E. CANTO ET AL.: "A Temporal Bipartitioning Algoritm for Dynamically Reconfigurable FPGAs", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION - VLSI - SYSTEMS, vol. 9, no. 1, February 2001 (2001-02-01), pages 210 - 218, XP002295077 *
HARTENSTEIN R: "Coarse grain reconfigurable architectures", CONFERENCE PROCEEDINGS ARTICLE, 30 January 2001 (2001-01-30), pages 564 - 569, XP010537867 *
M KÖSTER, J. TEICH: "(Self-)reconfigurable Finite State Machines: Theory and Implementation", PROCEEDINGS OF THE 2002 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 4 March 2002 (2002-03-04), PARIS, pages 1 - 8, XP002295075 *
P.M. HEYSTERS, J.M. SMIT, B. MOLENKAMP: "Reconfigurable Architecture for Handheld Devices", PROCEEDINGS OF THE 3D PROGRESS WORKSHOP ON EMBEDDED SYSTEMS, 24 October 2002 (2002-10-24), UTRECHT, XP002295073 *
RABAEY J M: "Hybrid reconfigurable processors-the road to low-power consumption", VLSI DESIGN, 1998. PROCEEDINGS., 1998 ELEVENTH INTERNATIONAL CONFERENCE ON CHENNAI, INDIA 4-7 JAN. 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 4 January 1998 (1998-01-04), pages 300 - 303, XP010263449, ISBN: 0-8186-8224-8 *
SIEMERS C ET AL: "Reconfigurable computing based on universal configurable blocks-a new approach for supporting performance- and realtime-dominated applications", COMPUTER ARCHITECTURE CONFERENCE, 2000. ACAC 2000. 5TH AUSTRALASIAN CANBERRA, ACT, AUSTRALIA 31 JAN.-3 FEB. 2000, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 31 January 2000 (2000-01-31), pages 82 - 89, XP010370824, ISBN: 0-7695-0512-0 *
SKLYAROV V: "Reconfigurable models of finite state machines and their implementation in FPGAs", JOURNAL OF SYSTEMS ARCHITECTURE, ELSEVIER SCIENCE PUBLISHERS BV., AMSTERDAM, NL, vol. 47, no. 14-15, August 2002 (2002-08-01), pages 1043 - 1064, XP004375020, ISSN: 1383-7621 *
TESSIER R ET AL: "RECONFIGURABLE COMPUTING FOR DIGITAL SIGNAL PROCESSING: A SURVEY", JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY, KLUWER ACADEMIC PUBLISHERS, DORDRECHT, NL, vol. 28, no. 1/2, May 2001 (2001-05-01), pages 7 - 27, XP001116960, ISSN: 0922-5773 *

Also Published As

Publication number Publication date
WO2004040766A2 (de) 2004-05-13
DE10347975B4 (de) 2008-10-09
JP4160956B2 (ja) 2008-10-08
EP1554805A2 (de) 2005-07-20
JP2006504344A (ja) 2006-02-02
US20060055421A1 (en) 2006-03-16
US7161383B2 (en) 2007-01-09
DE10347975A1 (de) 2004-05-13

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