WO2004038812A1 - Circuits optoelectroniques faisant appel a un ou plusieurs dispositifs de thyristors - Google Patents

Circuits optoelectroniques faisant appel a un ou plusieurs dispositifs de thyristors Download PDF

Info

Publication number
WO2004038812A1
WO2004038812A1 PCT/US2003/033813 US0333813W WO2004038812A1 WO 2004038812 A1 WO2004038812 A1 WO 2004038812A1 US 0333813 W US0333813 W US 0333813W WO 2004038812 A1 WO2004038812 A1 WO 2004038812A1
Authority
WO
WIPO (PCT)
Prior art keywords
digital
signal
input
optical
heterojunction thyristor
Prior art date
Application number
PCT/US2003/033813
Other languages
English (en)
Inventor
Geoff W. Taylor
Jianhong Cai
Original Assignee
University Of Connecticut
Opel, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/280,892 external-priority patent/US6954473B2/en
Priority claimed from US10/323,388 external-priority patent/US6873273B2/en
Priority claimed from US10/323,413 external-priority patent/US6995407B2/en
Priority claimed from US10/323,390 external-priority patent/US6853014B2/en
Priority claimed from US10/323,389 external-priority patent/US7332752B2/en
Application filed by University Of Connecticut, Opel, Inc. filed Critical University Of Connecticut
Priority to AU2003284911A priority Critical patent/AU2003284911A1/en
Publication of WO2004038812A1 publication Critical patent/WO2004038812A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H01L29/155—Comprising only semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
    • H03K17/79—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling bipolar semiconductor switches with more than two PN-junctions, or more than three electrodes, or more than one electrode connected to the same conductivity region
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/667—Recirculation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/808—Simultaneous conversion using weighted impedances using resistors

Definitions

  • This invention relates broadly to the field of optoelectronics devices, and, more particularly to optoelectronic circuits that convert optical signals into electrical signals and/or perform high speed signal sampling operations.
  • Optical networks provide the advantages of increased speed and transmission capacity for carrying voice and data.
  • optical signals e.g., light waves
  • This information is provided by a source typically in electrical form and converted into an optical signal for transmission over the network.
  • the sound waves of the spoken voice are typically converted into an analog electrical signal which is converted into a digital electrical signal consisting of bits of information, wherein each bit is either a logic level 'V (the amplitude of the digital electrical signal is high/ON) or logic level '0' (the amplitude of the digital electrical signal is low/OFF).
  • Data is typically stored in digital form as bits of information, and thus analog-to-digital conversion is not necessary.
  • the digital electrical signal is converted to a digital optical signal by an electrical-to-optical converter, which modulates a laser light source in response to the digital electrical signal.
  • the digital optical signal consists of bits of information, wherein each bit is either a logic level '1' (the light intensity level of the digital optical signal is high/ON) or a logic level '0' (the light intensity level of the digital optical signal is low/OFF).
  • the digital optical signal is then transmitted over a medium (such as a light guide optical fiber).
  • An optical-to-electrical converter receives the digital optical signal produced by the laser source and transmitted over the medium, and generates a digital electrical signal corresponding to the digital optical signal.
  • the digital electrical signal may be converted back to a digital optical signal for transmission over the optical network (such as the case where the optical-to-electrical converter is part of switch/router that operates in the electric domain on digital electrical signals).
  • the digital electrical signal may be converted to an analog electrical signal (such as the case for voice applications where the analog electrical signal is converted back into sound waves that can be interpreted by the person receiving the phone call).
  • the digital electrical signal may be transformed for communication over a data communication link (such as the case for data applications where the digital electrical signal is transformed (e.g. packetized) for communication over a data communication link, such as a Gigabit Ethernet link).
  • FIG. 1 A is a prior art functional block diagram illustrating a typical optical- to-electrical converter including a photodetector 110 (which may be one or more avalanche photodiodes or one or more PIN photodiodes) that converts the light level of the received digital optical signal to a signal current.
  • the photodetector 110 delivers the extracted current to a transimpedance amplifier (TIA) 111, which first converts the current to a voltage.
  • TIA transimpedance amplifier
  • a post amplifier 112 is provided, which in most cases is configured as a limiting amplifier that delivers a certain output- oltage swing whose maximum is independent of the input signal strength.
  • a data recovery circuit 113 performs amplitude-level analysis on the signal output by post amplifier 112 to recover the serial digital data signal (in electrical form) from the received optical signal.
  • Demultiplexing circuit 114 performs a serial-to-parallel conversion on the serial digital data stream generated by the data recovery circuit 113 to generate a multi-bit digital signal (electrical) representing a sequence of bits in the received digital optical signal.
  • the mechanism of FIG. 1A that converts the digital optical signal to a digital electrical signal (the photodetector 110, TIA 111, post amplifier 112 and data recovery circuit 113) is costly to design and manufacture because of the complex nature of the TIA 111, post amplifier 112 and data recovery circuit 113, and because of difficulties in integrating one or more of these components with the photodetector 110.
  • a parallel optical data link consists of a transmit module 120 coupled to a receive module 122 with a multi- fiber connector 124.
  • the transmit module typically employs an array 126 of vertical-cavity- surface-emitting lasers (NCSELs) and a multi-channel laser driver integrated circuit 128 for driving the array of lasers to produced a plurality of synchronous optical bit streams that are transmitted over the multi-fiber connector 124.
  • NCSELs vertical-cavity- surface-emitting lasers
  • multi-channel laser driver integrated circuit 128 for driving the array of lasers to produced a plurality of synchronous optical bit streams that are transmitted over the multi-fiber connector 124.
  • the receive module 122 includes a photodetector array 130 (typically realized with P-I- ⁇ diodes) that receives the synchronous optical bit streams and cooperate with an integrated circuit 132 that provides a corresponding array of low noise transimpedance amplifiers, limiting amplifiers, and data recovery circuits to produce a plurality of electrical bit streams corresponding thereto.
  • the plurality of electrical bit streams are provided to one or more integrated circuits 134 that map parallel bits encoded in the plurality of electrical bit streams into a predetermined data format (such as a SONET frame).
  • a predetermined data format such as a SONET frame
  • the complex nature of the TIA, post amplifier and data recovery circuit in the receive module 122 leads to increased design costs and manufacture costs of the receive module 122, and also leads to difficulties in integrating one or more of these components with the photodetector array as part of the receive module 122.
  • FIG. IC is a functional block diagram illustrating a typical mechanism for performing such conversion operations. Similar to FIG. 1A, a photodetector 110 converts the light level of the received digital optical signal to a signal current. The photodetector 110 delivers the extracted current to a transimpedance amplifier (TIA) 111, which first converts the current to a voltage. This single-ended voltage is amplified by the TIA and typically converted to a differential signal.
  • TIA transimpedance amplifier
  • a post amplifier 112 is provided, which in most cases is configured as a limiting amplifier that delivers a certain output- voltage swing whose maximum is independent of the input signal strength.
  • a data recovery circuit 113 performs amplitude-level analysis on the signal output by post amplifier 112 to recover the serial digital data signal (in electrical form) from the received optical signal.
  • Demultiplexing circuit 114 performs a serial- to-parallel conversion on the serial digital data stream generated by the data recovery circuit 113 to generate a multi-bit digital signal (electrical) representing a sequence of bits in the received digital optical signal.
  • the multi-bit digital signal produced by the demultiplexing circuit 114 is provided to a digital-to-analog converter 115 that converts the multi- bit digital signal to a corresponding analog electrical signal.
  • a parallel optical data link may be used to carry analog information (such as voice).
  • analog information such as voice
  • This approach suffers from the same limitations of the approach of FIGS. 1A and IB, wherein the complex nature of the TIA, post amplifier and data recovery circuit leads to increased design costs and manufacture costs.
  • the large number of complex components that make up the signal processing chain are costly to design and manufacture.
  • digital-to-analog converters and other signal processing circuitry such as analog-to-digital converters, switched-capacitance filters/amplifiers, and switched-capacitance waveform generators typically employ electrically-controlled transistors as on-off switches to perform signal sampling operations. Due to parasitic capacitance and intrinsic capacitances between the input and output nodes of the sampling transistor, feedthrough charge that collects on the sampled signal increases to an intolerable level at high frequencies. Therefore, the electronic sampling technique becomes limited in sensitivity at high sampling rates.
  • devices such as FET transistors, bipolar transistors, lasers, optical modulators, and waveguide devices.
  • devices such as FET transistors, bipolar transistors, lasers, optical modulators, and waveguide devices.
  • devices such as FET transistors, bipolar transistors, lasers, optical modulators, and waveguide devices.
  • devices such as FET ttansistors, bipolar transistors, lasers, optical modulators, and waveguide devices.
  • a heterojunction thyristor device is configured to convert an input digital optical signal to an output digital electtical signal.
  • the input digital optical signal encodes bits of information (each bit representing an OFF logic level or ON logic level) and is part of the Optical IN signal that is resonantly absorbed by the device.
  • a sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal.
  • the sampling clock can be in the form of electtical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device.
  • the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device.
  • the heterojunction thyristor device operates in an OFF state and an ON state. In the OFF state, current does not flow between an anode terminal and a cathode terminal of the device; while in the ON state, current flows between the anode terminal and the cathode terminal.
  • the heterojunction thyristor device switches from its OFF state to its ON state in the event that, during a given sampling period, the light intensity level of the input digital optical signal corresponds to the ON logic level; however, it does not switch into the ON state (and remains in the OFF state) in the event that, during the given sampling period, the light intensity level of the digital optical signal corresponds to the OFF logic level.
  • these sampling pulses can be in the form of downward running electrical pulses (e.g., pulses wherein the relative voltage between the start of the pulse and the peak of the pulse is less than zero) supplied to the n-channel injector terminal(s) of the heterojunction thyristor device, and/or in the form of upward running electrical pulses (e.g., pulses wherein the relative voltage between the start of the pulse and the peak of the pulse is greater than zero) supplied to the p-channel injector terminal(s) of the heterojunction thyristor device.
  • downward running electrical pulses e.g., pulses wherein the relative voltage between the start of the pulse and the peak of the pulse is less than zero
  • upward running electrical pulses e.g., pulses wherein the relative voltage between the start of the pulse and the peak of the pulse is greater than zero
  • the voltage level (e.g., magnitude) of the ON state of the output digital electrical signal produced by the heterojunction thyristor device can be adjusted by a voltage divider network coupled between the cathode terminal of the device and ground potential.
  • a plurality of such heterojunction thyristor devices may be configured to convert a plurality of synchronous digital optical signals to corresponding digital electtical signals for use in high speed applications, such as a receive module in a parallel optical data link.
  • a plurality of heterojunction thyristor devices are configured to convert a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electrical signal whose magnitude corresponds to the digital word.
  • Each heterojunction thyristor device is configured to convert an optical bit in the digital word to a corresponding digital electtical signal.
  • the voltage levels (e.g., magnitudes) of the ON state of the digital electrical signals produced by the heterojunction thyristor devices are varied by voltage divider networks coupled between the cathode terminal of the devices and ground potential. In this manner, the voltage divider networks produce electtical signals whose magnitude corresponds to the contribution of each optical bit in the digital word.
  • the electtical signals produced by the voltage divider networks is summed by a summing network to generate the output analog electtical signal corresponding to the digital word.
  • the summing network includes a chain of two-port adding nodes and sample/hold circuits arranged as pairs, each corresponding to a different voltage divider network.
  • the output electtical signal generated by a given voltage divider network is supplied to an input node of the two-port adding node of the corresponding pair.
  • a heterojunction thyristor device is configured as an optically-controlled (or electtically-conttolled) sampling/switching device.
  • first and second channel regions are disposed between the anode terminal and the cathode terminal of the device, and an electrical input terminal and an electrical output terminal are coupled to opposite ends of the first channel region.
  • At least one optical control signal (or an electrical control signal) is supplied to the device.
  • the light intensity level of the at least one optical control signal corresponds to a predetermined ON condition
  • sufficient charge is stored in the second channel region to cause the heterojunction thyristor device to operate in an ON state whereby current flows between the anode terminal and the cathode terminal and the electrical input terminal is electrically coupled to the electrical output terminal.
  • the heterojunction thyristor device When the light intensity level of the at least one optical control signal (or magnitude of the electrical control signal) corresponds to a predetermined OFF condition, the heterojunction thyristor device operates in an OFF state whereby current does not flow between the anode terminal and the cathode terminal and the electrical input terminal is electrically isolated from the electrical output terminal.
  • the optical control signal can be an optical sampling clock, a digital optical signal encoding bits of information, or the combination of a digital optical signal and an optical sampling clock (which defines sampling periods that overlap the bits of information in the digital optical signal).
  • the electtical control signal can be an electtical sampling clock injected into the second channel of the device that operates alone to supply charge that induces ON state operation.
  • an electrical sampling clock can be injected into the second channel of the device to contribute to the supply of charge therein that induces ON state operation (when the light intensity level of the optical control signal corresponds to the predetermined ON condition).
  • optically-conttoUed (or electtically-conttolled) sampling/switching devices are suitable for use as sample and hold circuitry in the photonic digital-to-analog converters described herein, and in a wide variety of signal processing applications, such as analog-to-digital converters, switched-capacitor filters, and switched-capacitor waveform shaping circuits.
  • a plurality of heterojunction thyristor devices are configured to convert a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electtical signal whose magnitude corresponds to the digital word.
  • Each heterojunction thyristor device is configured as a sampling device to convert an optical bit in the digital word to a corresponding digital electtical signal.
  • the voltage levels (e.g., magnitudes) of the ON state of the digital electtical signals produced by the heterojunction thyristor devices are provided by reference voltage sources operably coupled to the input terminals of the heterojunction thyristor devices.
  • the heterojunction thyristor devices and corresponding voltage reference sources produce electtical signals whose magnitude corresponds to the contribution of each optical bit in the digital word.
  • These electrical signals are summed by a summing circuit, which is preferably implemented by another heterojunction-thyristor-based sampling device, to generate the output analog electrical signal corresponding to the digital word.
  • a heterojunction thyristor device configured for optically-controlled sampling/switching is used as the basis for converting a digital word encoded by a serial digital optical data signal (e.g., serial optical bit stream) into a corresponding analog electrical signal.
  • a voltage reference is operably coupled to the electrical input terminal of the heterojunction thyristor device.
  • the voltage reference cooperates with the heterojunction thyristor device to sequentially generate at its electrical output terminal a voltage signal representing the contribution of each bit of the digital word encoded in the serial digital optical data signal.
  • a summing network is operably coupled to the electtical output terminal of the device. The summing network sequentially sums the voltage signal over the sequence of bits to produce an analog electtical signal corresponding to the digital word for output therefrom.
  • the summing network includes an adding node, sample and hold circuit, and a feedback path between the sample and hold circuit and the adding node.
  • the voltage reference preferably supplies a voltage level corresponding to the maximum voltage level of the analog electrical signal divided by where N is the number of bits in said digital word, and the feedback path comprises an amplifier that amplifies the output of the sample and hold circuit by a factor of 2.
  • monolithic optoelectronic integrated circuits that include one or more heterojunction thyristor devices as described herein are integrated with electronic devices (such as transistors) and/or optical devices (such as waveguide devices).
  • FIG. 1 A is a functional block diagram illustrating a prior art mechanism that converts a digital optical signal to a digital electtical signal.
  • FIG. IB is a functional block diagram illustrating a prior art parallel optical data link.
  • FIG. IC is a functional block diagram illustrating a prior art mechanism that converts a digital optical signal to an analog electrical signal.
  • FIG. 2A is a cross-sectional schematic showing a layer structure in accordance with the present invention, and from which devices of the present invention can be made.
  • FIG. 2B 1 is a pictorial illustration of a heterojunction thyristor device that is used to convert an input digital optical signal to an output digital electtical signal in accordance with the present invention; in this configuration, the input digital optical signal is part of the Optical IN signal that is resonantly absorbed by the device, and a sampling clock (electrical) is supplied to the injector terminal of the device.
  • a sampling clock electrical
  • FIG. 2B2 is a pictorial illustration of a heterojunction thyristor device that is used to convert an input digital optical signal to an output digital electrical signal in accordance with the present invention; in this configuration, the input digital optical signal and a sampling clock (optical) are part of the Optical IN signal that is resonantly absorbed by the device.
  • FIG. 2B2 is a pictorial illustration of a heterojunction thyristor device that is used to convert an input digital optical signal to an output digital electrical signal in accordance with the present invention; in this configuration, the input digital optical signal and a sampling clock (optical) are part of the Optical IN signal that is resonantly absorbed by the device.
  • 2B3 is a pictorial illustration of a heterojunction thyristor device that is used to convert an input digital optical signal to an output digital electrical signal in accordance with the present invention
  • a voltage divider network is used to adjust magnitude of the ON state of the digital electrical signal; in this configuration, the input digital optical signal is part of the Optical IN signal that is resonantly absorbed by the device, and a sampling clock (electtical) is supplied to the injector terminal of the device.
  • FIG. 2B4 is a pictorial illustration of a heterojunction thyristor device that is used to convert an input digital optical signal to an output digital electrical signal in accordance with the present invention; a voltage divider network is used to adjust magnitude of the ON state of the digital electrical signal; in this configuration, the input digital optical signal and a sampling clock (optical) are part of the Optical IN signal that is resonantly absorbed by the device.
  • a sampling clock optical
  • FIG. 2C is a graph showing the current- voltage characteristics of the heterojunction thyristor device of the present invention over varying injector currents (I g ), and the bias line that depicts operation of the heterojunction thyristor device in converting the input digital optical signal to an output digital electrical signal.
  • FIG. 2D 1 is a graph depicting the operation of the heterojunction thyristor device in converting an input digital optical signal (in the ON state) to a corresponding output digital electtical signal (in the ON state) during a sampling period defined by an electrical sampling clock supplied to the injector terminal of the device; conversely, when the input digital optical signal is in the OFF state, the heterojunction thyristor remains in its NON-CONDUCTING/OFF state and produces an output digital electrical signal in the OFF state during the corresponding sampling period defined by the electrical sampling clock.
  • FIG. 2D2 is a graph depicting the operation of the heterojunction thyristor device in converting an input digital optical signal (in the ON state) to a corresponding output digital electtical signal (in the ON state) during a sampling period defined by an optical sampling clock; conversely, when the input digital optical signal is in the OFF state, the heterojunction thyristor remains in its NON-CONDUCTING/OFF state and produces an output digital electrical signal in the OFF state during the corresponding sampling period defined by the optical sampling clock.
  • FIG. 3A is a schematic showing an exemplary layer structure made with group III-V material in accordance with the present invention, and from which devices of the present invention can be made.
  • FIG. 3B shows the energy band diagram of the structure of FIG. 3 A.
  • FIG. 3C is a cross-sectional schematic view showing the generalized construction of an exemplary heterojunction thyristor formed from the layer structure of FIG. 3 A.
  • FIG. 3D is a schematic showing an alternate layer structure made with group III-V material in accordance with the present invention, and from which devices of the present invention can be made.
  • FIG. 3E shows the energy band diagram of the structure of FIG. 3D.
  • FIG. 3F is a cross-sectional schematic view showing the generalized construction of an exemplary heterojunction thyristor formed from the layer structure of FIG. 3D.
  • FIG. 4A is a functional block diagram illustrating a photonic digital-to-analog converter that converts a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electrical signal whose magnitude corresponds to the digital word in accordance with the present invention; in this configuration, electrical clock signals are used to perform the conversion operations.
  • a parallel digital optical signal e.g., a plurality of synchronous optical bits
  • FIGS. 4B(i), 4B(ii), and 4B(iii) is a timing diagram illustrating the encoding of a 4-bit digital word by 4 input digital optical signals and associated electrical timing signals relative thereto;
  • FIG. 4B(i) is a signal diagram that illusttates the encoding of a 4-bit digital word by 4 input digital optical signals supplied to the heterojunction thyristor devices of FIG. 4A;
  • FIG. 4B(ii) is a signal diagram that illusttates an electrical timing signal A supplied to the injector terminals of the heterojunction thyristor devices of FIG. 4A;
  • FIG. 4B(iii) is a signal diagram that illusttates an electrical timing signal B supplied to the summing network of FIG. 4A.
  • FIGS. 4C and 4D are cross-sectional schematics showing heterojunction thyristor devices configured to perform electrically-controlled sampling operations in response to an electtical clock signal supplied thereto; each of these configurations is suitable to realize the electrically-controlled sample and hold circuit of FIG. 4A.
  • FIG. 4E is a functional block diagram illustrating a photonic digital-to-analog converter that converts a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electrical signal whose magnitude corresponds to the digital word in accordance with the present invention; in this configuration, electrical clock signals are used to perform the conversion operations.
  • a parallel digital optical signal e.g., a plurality of synchronous optical bits
  • FIG. 5 A is a functional block diagram illustrating a photonic digital-to-analog converter that converts a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electrical signal whose magnitude corresponds to the digital word in accordance with the present invention; in this configuration, optical clock signals are used to perform the conversion operations.
  • a parallel digital optical signal e.g., a plurality of synchronous optical bits
  • FIGS. 5B(i), 5B(ii), and 5B(iii) is a timing diagram illustrating the encoding of a 4-bit digital word by 4 input digital optical signals and associated optical timing signals relative thereto;
  • FIG. 5B(i) is a signal diagram that illustrates the encoding of a 4-bit digital word by the input digital optical signals supplied to the heterojunction thyristor devices of FIG. 5 A;
  • FIG. 5B(ii) is a signal diagram that illustrates an optical timing signal A supplied to the heterojunction thyristor devices of FIG. 5A for resonant abso ⁇ tion therein;
  • FIG. 5B(iii) is a signal diagram that illusttates an optical timing signal B supplied to the summing network of FIG. 5 A.
  • FIGS. 5C and 5D are cross-sectional schematics showing heterojunction thyristor devices configured to perform optically-controlled sampling operations in response to an optical clock signal supplied thereto; each of these configurations is suitable to realize the optically-controlled sample and hold circuit of FIG. 5 A.
  • FIG. 5E is a functional block diagram illustrating a photonic digital-to-analog converter that converts a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electrical signal whose magnitude corresponds to the digital word in accordance with the present invention; in this configuration, optical clock signals are used to perform the conversion operations.
  • a parallel digital optical signal e.g., a plurality of synchronous optical bits
  • FIG. 5F is a cross-sectional schematic view showing the generalized construction of an exemplary heterojunction thyristor device formed from the layer structure of FIG. 3 A, which is readily configured in accordance with FIGS. 4C-4E or 5C-5E to perform sampling operations.
  • FIG. 6A is a functional block diagram illustrating a photonic digital-to-analog converter that converts a digital word encoded by a serial digital optical signal (e.g., a plurality of serial optical bits) to an output analog electtical signal whose magnitude corresponds to the digital word in accordance with the present invention; in this configuration, an electrical clock signal is used to perform the conversion operations.
  • a serial digital optical signal e.g., a plurality of serial optical bits
  • FIGS. 6B(i) and 6B(ii) is a timing diagram illustrating the serial encoding of a 4-bit digital word by the input digital optical signal and associated electtical clock signal relative thereto;
  • FIG. 6B(i) is a signal diagram that illusttates the serial encoding of a 4-bit digital word by the input digital optical signal supplied to the heterojunction thyristor device of FIG. 6A;
  • FIG. 6B(ii) is a signal diagram that illusttates the electrical clock signal supplied to the injector terminal of the first heterojunction thyristor device and supplied to the summing network of FIG. 6A.
  • FIGS. 6C and 6D are cross-sectional schematics showing heterojunction thyristor devices configured to perform optically-controlled sampling operations in response to a digital optical signal and an electtical clock signal supplied thereto; each of these configurations is suitable to realize the first heterojunction sampling device of FIG. 6A.
  • FIG. 7A is a functional block diagram illustrating a photonic digital-to-analog converter that converts a digital word encoded by a serial digital optical signal (e.g., a plurality of serial optical bits) to an output analog electtical signal whose magnitude corresponds to the digital word in accordance with the present invention; in this configuration, an optical clock signal is used to perform the conversion operations.
  • a serial digital optical signal e.g., a plurality of serial optical bits
  • FIGS. 7B(i) and 7B(ii) is a timing diagram illustrating the serial encoding of a 4-bit digital word by the input digital optical signal and associated optical clock signal relative thereto;
  • FIG. 7B(i) is a signal diagram that illusttates the serial encoding of a 4-bit digital word by the input digital optical signal supplied to the heterojunction thyristor device of FIG. 7A;
  • FIG. 7B(ii) is a signal diagram that illustrates the optical clock signal supplied to the first heterojunction thyristor device and supplied to the summing network of FIG. 7A.
  • FIGS. 7C and 7D are cross-sectional schematics showing heterojunction thyristor devices configured to perform optically-controlled sampling operations in response to a digital optical signal and an optical clock signal supplied thereto; each of these configurations is suitable to realize the first heterojunction sampling device of FIG. 7 A.
  • FIG. 8A is a cross-sectional schematic view showing the generalized construction of an exemplary p-type quantum-well-base bipolar ttansistor device formed from the layer structure of FIG. 2A.
  • FIG. 8B is a diagram illustrating a differential amplifier circuit having a gain factor of 2, which is realized with a plurality of p-type quantum- well-base bipolar transistor devices as shown in FIG. 8 A; this configuration is suitable for the feedback amplifier in the summing network of FIGS. 6A and 7A.
  • FIG. 9A is a functional block diagram illustrating an optical-to-electrical converter that converts a digital optical signal (e.g., serial optical bit stream) to a digital electrical signal; in this configuration, electrical clock signals are used to perform the conversion operations.
  • FIGS. 9B(i) and 9B(ii) is a timing diagram illustrating the serial encoding of a 4-bit digital word by the input digital optical signal and associated electrical timing signals relative thereto;
  • FIG. 9B(i) is a signal diagram that illustrates the serial encoding of bits in the digital optical signal supplied to the heterojunction thyristor device of FIG. 9A; and FIG. 9B(ii) is a signal diagram that illusttates the electtical timing signal A supplied to the injector terminal of the heterojunction thyristor device of FIG. 9A.
  • FIG. 9C is a functional block diagram illustrating an optical-to-electtical converter that converts a digital optical signal (e.g., serial optical bit stream) to a digital electtical signal; in this configuration, optical clock signals are used to perform the conversion operations.
  • a digital optical signal e.g., serial optical bit stream
  • optical clock signals are used to perform the conversion operations.
  • FIGS. 9D(i) and 9D(ii) is a timing diagram illustrating the serial encoding of a 4-bit digital word by the input digital optical signal and associated optical timing signals relative thereto;
  • FIG. 9D(i) is a signal diagram that illusttates the serial encoding of bits in the digital optical signal supplied to the heterojunction thyristor device of FIG. 9C;
  • FIG. 9D(ii) is a signal diagram that illusttates the optical clock signal A supplied to the heterojunction thyristor device of FIG. 9C.
  • FIG. 9E is a functional block diagram of a receive module of a parallel data link, the receive module employing a plurality of the optical-to-electtical converters of FIG. 9A (or FIG. 9C) to convert a plurality of synchronous optical bit stteams to corresponding digital electtical signals.
  • Modulation-doped quantum well heterojunction ttansistors including well known Pseudomo ⁇ hic Pulsed Doped High Electton Mobility Transistors (Pulsed Doped PHEMT), which are sometimes referred to as Pulsed Doped Modulation Doped Field Effect Transistors (Pulsed Doped MODFET) or Pulsed Doped Two Dimensional Gas Field Effect Transistors (Pulsed Doped TEGFET) - have become well recognized for their superior low noise and high frequency performance and are now in demand in many high frequency applications (e.g., front end amplifier in wireless communications systems and in Monolithic Microwave and Millimeterwave IC (MMIC) designs).
  • PHEMT Pulsed Doped Pulsed Doped PHEMT
  • Pulsed Doped MODFET Pulsed Doped Modulation Doped Field Effect Transistors
  • Pulsed Doped TEGFET Pulsed Doped Two Dimensional Gas Field Effect Transistors
  • GaAs/TnGaAs/Al x Ga ⁇ x As or InP/InGaAs/InAlAs is the III-V material system of choice for these devices because of the ability to grow high optical/electrical quality epitaxial layers by molecular beam epitaxy (MBE).
  • MBE molecular beam epitaxy
  • strained silicon heterostructures employing silicon- germanium (SiGe) layers have been used to produce such devices.
  • U.S. Patent No. 4,827,320 to Morkoc et al. discloses a pseudomo ⁇ hic HEMT (PHEMT) structure that employs a layer of strained InGaAs (undoped) between a GaAs substrate and a layer of undoped AlGaAs to form a quantum well defined by the strained InGaAs layer.
  • a layer of n+ doped AlGaAs is formed on the undoped AlGaAs layer.
  • a layer of n+ GaAs is formed on the layer of n+ doped AlGaAs.
  • the layer of n+ GaAs facilitates an ohmic contact to source/drain electrodes.
  • a gate electrode of aluminum is recessed below the layer of n+ GaAs and a portion of the n+ AlGaAs layer by wet chemical etch and evaporation of aluminum.
  • the PHEMT structure has been very successful in producing microwave transistors that operate well into the multi-gigahertz regime, initially being used extensively in military systems and now finding their way into commercial products, particularly in the area of cellular communications.
  • the PHEMT has been a growing interest in combining the PHEMT with optical capability because of the difficulty in propagating very high frequency signals to and from the integrated circuit by coaxial lines.
  • Combining electronic with optoelectronic components monolithically gives rise to the concept of the optoelectronic integrated circuit (OEIC).
  • OEIC optoelectronic integrated circuit
  • inversion channel heterojunction structures created from a single epitaxial growth have been used to realize a range of optoelectronic devices including lasers, detectors and field effect transistors (FETs).
  • FETs field effect transistors
  • An exemplary inversion channel heterojunction structure is described in Taylor and Kiely, "Theoretical and Experimental Results for the Inversion Channel Heterostructure Field Effect Transistors", IEE Proceedings-G, Vol. 140, No. 6, December 1993.
  • the doping of this region is substantially p type in order to provide a low resistance ohmic contact for the gate of the FET.
  • the high p-type doping of this region creates many problems, including: i) the effects of free carrier abso ⁇ tion makes formation of a vertical cavity laser difficult; ii) forming depletion-type FETs by implanting n-type dopant is difficult; this difficulty stems from the difficulty in controlling the dopant density in the bulk region; more specifically, compensating a large p density with a large n density to obtain a lower p density is difficult to control in a bulk region (but much easier in a delta doped region); iii) controlling the threshold voltage of an enhancement type FET is difficult because the input capacitance is a function of doping which is harder to control than layer thickness; and iv) producing effective current funneling for inducing lasing is difficult; more specifically, it is very desirable to create a pn junction by N type implantation to steer the current in this structure since this would be compatible with the overall approach to building the FET devices; the heavy p doping bulk layers makes it difficult to create junction isolation that has
  • the present invention builds upon novel device structures utilizing modulation-doped quantum well heterojunctions that do not suffer from the problems associated with the prior art PHEMT devices.
  • Such novel device structures are described in detail in U.S. Patent 6,031,243; U.S. Patent Application No. 09/556,285, filed on April 24, 2000; U.S. Patent Application No. 09/798,316, filed on March 2,2001; U.S. Patent Application No. 08/949,504, filed on October 14, 1997, U.S. Patent Application No. 10/200,967, filed on July 23,2002; U.S. Application No. 09/710,217, filed on November 10,2000; U.S. Patent Application No. 60/376,238, filed on April 26,2002; U.S. Patent Application No. 10/280,892, filed on October 25, 2002; each of these references herein inco ⁇ orated by reference in its entirety.
  • the general structure of the heterojunction thyristor device is illustrated in the cross-section of FIG. 2A.
  • the general structure of FIG. 2A can be configured to operate as a field effect transistor, bipolar ttansistor, and as a passive waveguide such that these devices can be integrated to form a monolithic optoelectronic integrated circuit as described herein.
  • the heterojunction thyristor device 1 of the present invention includes a bottom dielectric distributed bragg reflector (DBR) mirror 12 formed on substrate 10.
  • the bottom DBR mirror 12 typically is formed by depositing pairs of semiconductor or dielectric materials with different refractive indices. When two materials with different refractive indices are placed together to form a junction, light will be reflected at the junction. The amount of light reflected at one such boundary is not necessarily large.
  • the reflections from each of the boundaries will be added in phase to produce a large amount of reflected light (e.g., a large reflection coefficient) at the particular center wavelength _D- Deposited upon the bottom DBR mirror 12 is the active device structure which consists of two HFET devices.
  • the first of these is a p-channel HFET 11 (comprising layers 14,16,18,20 and 22) which has a p- type modulation doped quantum well and is positioned with the gate terminal on the lower side (i.e. on the mirror as just described) and the collector terminal on the upper side.
  • the second of these is an n-channel HFET 13 (comprising layers 22,24,26,28,30) which has an n-type modulation doped quantum well and is positioned with the gate terminal on the top side and the collector terminal on the lower side which is the collector of the p-channel device. Therefore a non-inverted N-channel device is stacked upon an inverted p-channel device to form the active device structure.
  • the active device layer structure begins with n-type ohmic contact layer(s) 14 which enables the formation of ohmic contacts thereto.
  • ohmic contact layer 14 is operably coupled to cathode terminal 40 of the heterojunction thyristor device (which corresponds to the gate electrode of the p-channel HFET device).
  • Deposited on layer 14 is one or more n-type layers 16 and an undoped spacer layer 18 which serve electrically as part of the P-channel HFET gate and optically as lower waveguide cladding layers.
  • Deposited on layer 18 is a p-type modulation doped heterojunction structure 20 that defines one or more quantum wells (which may be formed from strained or unstrained heterojunction materials).
  • p-type modulation doped heterojunction structure 20 Deposited on p-type modulation doped heterojunction structure 20 is an undoped spacer layer 22, which forms the collector of the P- channel HFET device. All of the layers grown thus far form the P-channel HFET device with the gate ohmic contact on the bottom.
  • Undoped spacer layer 22 also forms the collector region of the N-channel HFET device.
  • a n-type modulation doped heterojunction structure 24 that defines one or more quantum wells (which may be formed from strained or unstrained heterojunction materials).
  • Deposited on the n-type modulation doped heterojunction structure 24 is an undoped spacer layer
  • the p-type layers 28 include two sheets of planar doping of highly doped p-material separated by a lightly doped layer of p-material.
  • p-type layers are separated from the N-type modulation doped quantum well (QW) heterostructure 24 by undoped spacer material 26.
  • QW quantum well
  • the top charge sheet achieves low gate contact resistance and the bottom charge sheet defines the capacitance of the n- channel HFET with respect to the N-type modulation doped QW heterostructure 24.
  • Deposited on p-type layer(s) 28 is a p-type ohmic contact layer(s) 30 which enables the formation of ohmic contacts thereto.
  • ohmic contact layer(s) 30 is operably coupled to the anode terminal 36 of the heterojunction thyristor device (which corresponds to the gate electrode of the n-channel
  • the injector terminal 38 of the heterojunction thyristor device (which is analogous to the gate terminal of conventional thyristor devices) preferably is operably coupled to the QW channel(s) realized in the N-type modulation doped QW(s) heterostructure 24 as shown in FIG. 2A.
  • the injector terminal of the heterojunction thyristor device may be operably coupled to the QW channel(s) realized in the P-type modulation doped QW(s) heterostructure 20.
  • the polarity of the control signals applied to the injector terminal 38 are reversed, and the bias current is configured to move charge from the QW channel(s) realized in the P-type modulation doped QW(s) heterostructure 24 to ground potential.
  • a first injector terminal may be operably coupled to the QW channel(s) realized in the N-type modulation doped QW(s) heterostructure 24 while a second injector terminal is operably coupled to the P-type modulation doped QW(s) heterostructure 20.
  • the polarity of the control signals applied to the second injector terminal are reversed, and the bias current is configured to move charge from the QW channel(s) realized in the P-type modulation doped QW(s) heterostructure 20 to ground potential.
  • a diffraction grating and top DBR mirror are formed over the active device structure described above.
  • the diffraction grating performs the function of diffracting incident light that is propagating in the lateral direction into the vertical cavity mode, where it is absorbed resonantly in the vertical cavity.
  • light may enter the resonant vertical cavity through an optical aperture (not shown) in the top surface of the device.
  • the diffraction grating is omitted, the top DBR mirror defines a cavity for the vertical abso ⁇ tion of light, and the device operates as a vertical cavity detector.
  • the distance between the top DBR mirror and bottom DBR mirror preferably represents an integral number of 1/2 wavelengths at the designated wavelength. This distance is controlled by adjusting the thickness of one or more of the layers therebetween to enable this condition.
  • These configurations define an optically active region 44 that encompasses the QW channel(s) of structures 24 and 20.
  • the optical signal IN 42 (which propagates in the vertical direction, or which propagates in the lateral direction and is diffracted from the lateral direction into a vertical propagation direction by diffraction grating 32) is resonantly absorbed in region 44.
  • the operation of the heterojunction thyristor device can also be controlled by injection of electrical energy (e.g., an electtical input pulse signal) into the QW channel(s) of structure 24 (and/or the QW channel(s) of structure 20).
  • electrical energy e.g., an electtical input pulse signal
  • Such injection contributes to the generation of electron- hole pairs in the QW channel(s) thereby causing charge to build up therein.
  • FIGS. 2B1 through 2B4, 2C, 2D1 and 2D2 illustrate the operational characteristics of the heterojunction thyristor device of FIG. 2A in accordance with the present invention.
  • the device switches from a non-conducting/OFF state (where the current I is substantially zero) to a conducting/ON state (where current I is substantially greater than zero) when: i) the anode terminal 36 is forward biased (e.g.
  • QCR is unique to the geometries and doping levels of the device.
  • the forward breakdown voltage of the device varies over the injector current I g as shown in FIG. 2C.
  • the device switches from the conducting/ON state to a non-conducting/OFF state when the current I through the device falls below the hold current I H of the device for a sufficient period of time such that the charge in the N-type modulation doped QW structure 24 decreases below the holding charge Q H -
  • the holding charge Q H is the critical value of the channel charge which will sustain holding action.
  • the device is configured to convert an input digital optical signal to an output digital electrical signal as follows.
  • the input digital optical signal encodes bits of information (each bit representing an OFF logic level or ON logic level) and is part of the Optical IN signal that is resonantly absorbed by the device.
  • a sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal.
  • the sampling clock is in the form of downward running electtical pulses (e.g., pulses wherein the relative voltage between the start of the pulse and the peak of the pulse is less than zero) supplied to the injector terminal 38.
  • FIGS. 1 the sampling clock is in the form of downward running electtical pulses (e.g., pulses wherein the relative voltage between the start of the pulse and the peak of the pulse is less than zero) supplied to the injector terminal 38.
  • the sampling clock is in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device.
  • the device is biased (preferably, by selecting the appropriate load resistance/voltage divider network as shown in FIGS. 2B1 through 2B4) such that the current I through the device in the ON state is substantially greater than zero but substantially below the threshold current for lasing I (preferably about one-third of I I ) as shown in FIG. 2C.
  • the injector terminal 38 is forward biased with respect to the anode terminal 36 through a current source that generates a bias current IBI AS as shown.
  • the length and width of the device is sized such that it operates during a given sampling period defined by the electrical sampling clock as follows.
  • the bias current IBIA S exceeds the bias current IBIA S to produce the critical switching charge Q CR in the N-type modulation doped QW structure 24.
  • This causes the heterojunction thyristor to switch to its conducting/ON state where the current I through the device is substantially greater than zero but below the threshold for lasing I . This operation is shown graphically in FIG. 2D1.
  • the bias current I BI A S exceeds the channel current produced by the electrical sampling clock alone and thus draws on the injector terminal 38 to drain charge from the N-type modulation doped QW structure 24, which causes the chamiel charge to fall below the holding charge Q H - This causes the heterojunction thyristor to switch to its non-conducting/OFF state where the current I through the device is substantially zero.
  • the bias current I B I AS exceeds the combination of the channel current produced by the input digital optical signal and the electrical sampling clock and thus draws on the injector terminal 38 to drain charge from the N-type modulation doped QW structure 24, which causes the channel charge to remain below the holding charge Q H .
  • This causes the device to remain in its non- conducting/OFF state where the current I through the device is substantially zero.
  • the logic levels (ON state/OFF state) of the output digital electrical signal produced at the cathode terminal 50 correspond to the logic levels of the input digital optical signal.
  • the length and width of the device must also be selected such that the output current produced at the cathode terminal 40 is large enough to drive the capacitive load of the circuit element(s) coupled thereto, and leakage currents at the periphery of the device does not degrade the signal to noise ratio of the device to unacceptable levels.
  • the voltage level (e.g., magnitude) of the ON state of the output digital electtical signal produced by the device can be adjusted by a voltage divider network coupled between the cathode terminal 40 and ground potential as shown in FIG. 2B3.
  • the length and width of the device are sized such that it operates during a given sampling period defined by the optical sampling clock as follows.
  • the bias current I BIAS to produce the critical switching charge Q CR in the N- type modulation doped QW structure 24.
  • This causes the heterojunction thyristor to switch to its conducting/ON state where the current I through the device is substantially greater than zero but below the threshold for lasing I I - This operation is shown graphically in FIG. 2D2.
  • the bias current I B I AS exceeds the channel current produced by the optical sampling pulse alone and thus draws on the injector terminal 38 to drain charge from the N-type modulation doped QW structure 24, which causes the channel charge to fall below the holding charge Q H - This causes the heterojunction thyristor to switch to its non-conducting/OFF state where the current I through the device is substantially zero.
  • the bias current I BI A S exceeds the combination of the channel current produced by the input digital optical signal and the optical sampling clock and thus draws on the injector terminal 38 to drain charge from the N-type modulation doped QW structure 24, which causes the channel charge to remain below the holding charge QH- This causes the device to remain in its non- conducting/OFF state where the current I through the device is substantially zero.
  • the logic levels (ON state/OFF state) of the output digital electrical signal produced at the cathode terminal 40 correspond to the logic levels of the input digital optical signal.
  • the length and width of the device must also be selected such that the output current produced at the cathode terminal 40 is large enough to drive the capacitive load of the circuit element(s) coupled thereto, and leakage currents at the periphery of the device does not degrade the signal to noise ratio of the device to unacceptable levels.
  • the voltage level (e.g., magnitude) of the ON state of the output digital electrical signal produced by the device can be adjusted by a voltage divider network coupled between the cathode terminal 40 and ground potential as shown in FIG. 2B4.
  • the injector terminal 38 of the device may be operably coupled to the p-type QW channel(s) realized in the P-type modulation doped QW(s) structure 20.
  • the electtical sampling clock of FIGS. 2B1 and 2B3 is in the form of upward running electtical pulses (e.g., pulses wherein the relative voltage between the start of the pulse and the peak of the pulse is greater than zero) supplied to the injector terminal of the device.
  • the bias current source of FIGS. 2B1 through 2B4 draws charge from the p-type QW channel(s) to ground potential.
  • a first injector terminal may be operably coupled to the n-type QW channel(s) realized in the N-type modulation doped QW structure 24 while a second injector terminal is operably coupled to the p-type QW channel(s) in the P-type modulation doped QW(s) structure 20.
  • the electrical sampling clock supplied to the p-type QW channel(s) is in the form of upward running electtical pulses (e.g., pulses wherein the relative voltage between the start of the pulse and the peak of the pulse is greater than zero) supplied to the second injector terminal of the device.
  • the bias current source operably coupled to the p-type QW channel(s) draws charge from the p-type QW channel(s) to ground potential.
  • the structure of FIG. 2A may also be used to produce various ttansistor devices, including n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar ttansistor devices and n-type quantum-well-base bipolar transistor devices.
  • ohmic metal source and drain electrodes are electrically coupled to spaced apart N-type implants, which are electtically coupled to the n-type QW structure 24 to form a channel region there between.
  • An ohmic metal gate electrode is formed on the p-type ohmic contact layer 30 and covers the channel region.
  • An ohmic metal collector electrode is electrically coupled to at least one P-type implant, which is electrically coupled to the p-type QW structure 20 below the channel region.
  • ohmic metal source and drain electrodes are electtically coupled to spaced apart p-type implants, which are electtically coupled to the p-type QW structure 20 to form a channel region there between.
  • an ohmic metal gate electrode is deposited on the n-type ohmic contact layer 14.
  • An n-type implant is deposited above layer 22 and preferably into layer 24.
  • An ohmic metal collector electrode is formed on the n-type implant.
  • one or more base electrodes are electrically coupled to spaced apart P-type implants, which are electrically coupled to the p-type QW structure 20. Outside the p-type implants, one or more emitter electrodes are deposited on the n-type ohmic contact layer 14.
  • a collector electrode is electrically coupled to an n-type implant, which is electtically coupled to the n-type QW structure 24.
  • An additional collector electrode may be electrically coupled to another n-type implant into the p-type material of layer 28 or into the undoped spacer 26.
  • one or more base electtodes are electrically coupled to spaced apart n-type implants, which are electrically coupled to the n-type QW structure 24.
  • One or more collector electrodes are electtically coupled to corresponding p-type implants, which are electrically coupled to the p-type QW structure 20.
  • An emitter electrode is deposited on the n-type ohmic contact layer 30.
  • the structure of FIG. 2A may be used to produce various optoelectronic components, such as a laser device or an in-plane passive waveguide.
  • the heterojunction thyristor device is biased (preferably, by selection of load resistance operably coupled between the cathode terminal 40 and ground potential) such that the current I flowing the through the device in the conducting/ON state is above the lasing threshold II shown in FIG. 2C.
  • the conducting-ON state is controlled by abso ⁇ tion of an optical control signal incident on the device (and/or by injection of an electtical control signal supplied to the injector terminal 38) which causes charge to build up in the QW channel(s) of the device sufficient to induce a change in current flowing through the device from the anode terminal 36 to the cathode terminal 40.
  • an optical control signal incident on the device and/or by injection of an electtical control signal supplied to the injector terminal 38
  • the QW channel(s) of the device sufficient to induce a change in current flowing through the device from the anode terminal 36 to the cathode terminal 40.
  • the waveguide ridge cross-section is formed by a combination of several mesas, which are formed by vertical/horizontal surfaces formed in the layers between the top DBR mirror 34 and the bottom DBR mirror 12, to provide both laterally guiding and vertical guiding of light therein.
  • the heterojunction thyristor described above may be realized with a material system based on III-V materials (such as a GaAs/Al x Ga ⁇ -x As).
  • FIG. 3 A illustrates an exemplary epitaxial growth structure utilizing group III-V materials for realizing a heterojunction thyristor and associated optoelecttical optical devices in accordance with the present invention.
  • strained silicon heterostructures employing silicon-germanium (SiGe) layers may be used to realize the heterojunction thyristor devices and associated optoelecttical/optical devices described herein.
  • FIG. 3 A The structure of FIG. 3 A can be made, for example, using known molecular beam epitaxy (MBE) techniques.
  • a first semiconductor layer 151 of AlAs and a second semiconductor layer 152 of GaAs are alternately deposited (with preferably at least seven pairs) upon a semi-insulating gallium arsenide substrate 149 in sequence to fonn the top dielectric distributed bragg reflector (DBR) mirror 12.
  • DBR distributed bragg reflector
  • the number of AlAs layers will preferably always be one greater than the number of GaAs layers so that the first and last layers of the mirror are shown as layer 151.
  • the AlAs layers 151 are subjected to high temperature steam oxidation to produce the compound Al x O y so that a mirror will be formed at the designed center wavelength.
  • the thicknesses of layers 151 and 152 in the mirror are chosen so that the final optical thickness of GaAs and Al x O y is a quarter wavelength of the center wavelength ⁇ ,.
  • the mirrors could be grown as alternating layers of one quarter wavelength thickness of GaAs and AlAs at the designed wavelength so that the oxidation step is not used. In that case, many more pairs are required (with typical numbers such as 22 pairs) to achieve the reflectivity needed for efficient lasing.
  • the active device structure which consists of two HFET devices.
  • the first of these is the above-described p-channel HFET (PHFET) 11, which has a p-type modulation doped quantum well and is positioned with the gate terminal on the bottom (i.e. on the mirror 12 just described) and the collector terminal above.
  • the second of these is an n-chamiel HFET (NHFET) 13, which has an n-type modulation doped quantum well and is positioned with the gate terminal on top and the collector terminal below.
  • the collector region of the NHFET device 13 also functions as the collector region of the PHFET device 11.
  • the collector terminal of the NHFET device 13 is a p-type contact to p-type quantum well(s) disposed below (above) the collector region, while the collector terminal of the PHFET device 11 is a n-type contact to n-type quantum well(s) disposed above the collector region. Therefore a non-inverted n-channel device is stacked upon an inverted p-channel device to form the active device structure.
  • the active device layer structure begins with layer 153 of heavily N+ doped GaAs of about
  • the N+ doped GaAs layer 153 corresponds to the ohmic contact layer 14 of FIG. 2A.
  • layer 154 of n-type with a typical thickness of 500-3000 A arid a typical doping of 5xl0 17 cm “3 .
  • the parameter xl is in the range between 15% and 80%, and preferably in the range of 30%-40% for layer 154.
  • This layer serves as part of the PHFET gate and optically as part of the lower waveguide cladding layers for all laser, amplifier and modulator structures.
  • 4 layers 155a, 155b, 155b, and 155b) of Al x2 Ga ⁇ -x2 As. These 4 layers
  • the first layer 155a is about 60-80 A thick and is doped N+ type in the form of delta doping.
  • the second layer 155b is about 200-300 A thick and is undoped.
  • the third layer 155c is about 80 A thick and is doped P+ type in the form of delta doping.
  • the fourth layer 155d is about 20-30 A thick and is undoped to form a spacer layer. This layer forms the lower separate confinement heterostructure
  • SCH for the laser, amplifier and modulator devices.
  • the n-type AlGaAs layer 154 and n- type AlGaAs layer 155a correspond to the n-type layer(s) 16 of FIG. 2A, and the undoped AlGaAs layer 155b corresponds to the undoped spacer layer 18 of FIG. 2A.
  • the next layers define the quantum well(s) that form the inversion channel(s) during operation of the PHFET 11.
  • this consists of a spacer layer 156 of undoped GaAs that is about 10-25 A thick and then combinations of a quantum well layer 157 that is about 40-80 A thick and a barrier layer 158 of undoped GaAs.
  • the quantum well layer 157 may be comprised of a range of compositions.
  • the quantum well is formed from a Ino. 2 Ga 0 . 8 AsN composition with the nitrogen content varying from 0%o to 5% depending upon the desired natural emission frequency.
  • the nittogen content will be 0%; for a natural emission frequency of 1.3 ⁇ m, the nittogen content will be approximately 2%; and for a natural emission frequency of 1.5 ⁇ m, the nitrogen content will be approximately 4-5%.
  • the well barrier combination will typically be repeated (for example, three times as shown), however single quantum well structures may also be used. Unstrained quantum wells are also possible.
  • a layer 159 of undoped Al x2 Ga ⁇ - x2 As which forms the collector of the PHFET device 11 and is about 0.5 ⁇ m in thickness. All of the layers grown thus far form the PHFET device 11 with the gate contact on the bottom.
  • the layers between the P+ AlGaAs layer 155c and the last undoped GaAs barrier layer 158 correspond to the p-type modulation doped heterojunction QW structure 20 of FIG. 2 A.
  • AlGaAs layer 159 corresponds to the undoped spacer layer 22 of FIG. 2A.
  • Layer 159 also forms the collector region of the NHFET device 13.
  • Deposited on layer 159 are two layers (collectively 160) of undoped GaAs of about 200-250 A total thickness, which form the barrier of the first n-type quantum well.
  • Layer 160 is thicker than the normal barrier layer of about 100 A because it accommodates the growth interruption to change the growth temperature from 610° C (as required for optical quality Al x2 Ga ⁇ - x2 As layers) to about 530°C for the growth of InGaAs. Therefore layer 160 includes a single layer 160a of about 150 A and a repeating barrier layer 160b of about 100 A.
  • the next layer 161 is the quantum well of In 0 . 2 Ga 0 .
  • n-type quantum well layer 161 need not be of the same formulation as the p-type quantum well layer 157.
  • the barrier layer 160b of 100 A and quantum well layer 161 may be repeated, e.g., three times.
  • a barrier layer 162 of about 10-30 A of undoped GaAs which accommodates a growth interruption and a change of growth temperature.
  • These four layers (163) include a spacer layer 163a of undoped Al X2 Ga 1-x2 As that is about 20-30 A thick, a modulation doped layer 163b of N+ type doping of Al x Ga!- x2 As (with doping about 3.5xl0 18 cm “3 ) that is about 80 A thick, a capacitor spacing layer 163 c of undoped Al x2 Ga ⁇ - x2 As that is about 200-300 A thick, and a P+ type delta doped layer (with doping about 3.5xl0 18 cm “3 ) that is about 60-80 A to form the top plate of the capacitor.
  • the doping species for layer 163 d is preferably carbon (C) to ensure diffusive stability.
  • layer 163d In contrast to layer 163b which is always depleted, layer 163d should never be totally depleted in operation.
  • Layers 163 d and 163b form the two plates of a parallel plate capacitor which forms the field-effect input to all active devices.
  • layer 163 is the upper SCH region.
  • Layer 163 must be thin to enable very high frequency operation. In the illustrated embodiment, for a transistor cutoff frequency of 40 GHz, a thickness of 300 A would be used, and for 90 GHz a thickness of 200 A would be more appropriate.
  • the layers between the undoped GaAs barrier layer 160a and the N+ AlGaAs layer 163b correspond to the n-type modulation doped heterojunction QW structure 24 of FIG. 2A.
  • Undoped AlGaAs layer 163c corresponds to the undoped spacer layer 26 of FIG 2A.
  • One or more layers (collectively 164) of p-type Al x iGai- x iAs are deposited next to form part of the upper waveguide cladding layer for the laser, amplifier and modulator devices. It has a typical thickness of 500-1500 A.
  • Layer 164 may have a first thin sublayer 164a of, e.g., 10-20 A thickness and having a P+ typical doping of 10 19 cm "3 .
  • a second sublayer 164b has a P doping of lxlO 17 - 5xl0 17 cm "3 and a typical thickness of 700 A.
  • the parameter xl of layer 164 is preferably about 70%).
  • the p-type layers 163b, 164a, 164b correspond to the p-type layer(s) 28 of FIG. 2A.
  • an ohmic contact layer 165 (which may comprise a single layer of GaAs or a combination of GaAs (165a) and InGaAs (165b) as shown), which is about 50-100 A thick and doped to a very high level of P+ type doping (about lxlO 20 cm "3 ) to enable the best possible ohmic contact.
  • FIG. 3B The band diagram of the FIG. 3 A structure is shown in FIG. 3B.
  • a diffraction grating (as described in more detail in U.S. Patent 6,021,243, inco ⁇ orated by reference above in its entirety) and top DBR mirror are formed over the active device structure described above.
  • the diffraction grating When the heterojunction thyristor device is operating in the lasing mode, the diffraction grating performs the function of diffracting light produced by the vertical cavity into light propagating laterally in a waveguide which has the top DBR mirror and bottom DBR mirror as waveguide cladding layers and which has lateral confinement regions (typically formed by implants as described herein in more detail).
  • the diffraction grating When the heterojunction thyristor device is operating in the optical detection mode, the diffraction grating performs the function of diffracting incident light that is propagating in the lateral direction into the vertical cavity mode, where it is absorbed resonantly in the vertical cavity.
  • light may enter and exit the resonant vertical cavity vertically through an optical aperture in the top surface of the device.
  • the diffraction grating is omitted
  • the top DBR mirror defines a cavity for the vertical emission and abso ⁇ tion of light
  • the device operates as a vertical cavity surface emitting laser/detector.
  • the distance between the top DBR mirror and bottom DBR mirror preferably represents an integral number of 1/2 wavelengths at the designated wavelength.
  • the thickness of layer 164 or 159 is adjusted to enable this condition.
  • a heterojunction thyristor can be realized as shown in Fig. 3C.
  • alignment marks (not shown) are defined by etching, and then a layer of Si 3 N or Al 2 O 3 or other suitable dielectric (not shown) is deposited to act as protection for the surface layer and as a blocking layer for subsequent ion implants.
  • This dielectric layer also forms the first layer of the top DBR mirror.
  • an ion implant 175 of n-type is performed using a photomask that is aligned to the alignments marks, and an optical aperture is defined by the separation between the implants 175.
  • the implants 175 create a p-n junction in the layers between the n-type quantum wells and the surface, and the aperture between the implants defines the region in which the current may flow, and therefore the optically active region 177 as shown.
  • the current cannot flow into the n-type implanted regions 175 because of the barrier to current injection.
  • the current flow trajectory is shown in FIG. 3C as arrows.
  • the laser threshold condition is reached before the voltage for turn-on of this barrier.
  • the refractory anode terminals 36A and 36B (which collectively form the anode temiinal 36 of the device) are deposited and defined.
  • N+ ion implants 170 are used to form self-aligned channel contacts to the n-type QW inversion channel(s). More specifically, the N+ implants are used as an etch stop to form a mesa via etching down (for example, to layer 163c) near the n-type QW channel(s).
  • the N+ ion implants 170 are electrically coupled to the injector tenninals 38A and 38B (which collectively form the injector tenninal 38 of the device).
  • the injector terminals 38A and 38B are preferably formed via deposition of an n-type Au alloy metal on the N+ ion implants 170 to form ohmic contacts thereto.
  • injector terminals of the device are coupled to the p-type QW inversion channel(s)
  • P+ ion implants are used to form self-aligned channel contacts to the p-type QW inversion channel(s).
  • injector terminals 38A and 38B are preferably formed via deposition of an p-type Au alloy metal on the P+ ion implants to fonn ohmic contacts thereto.
  • first injector terminals may be operably coupled to the n-type QW channel(s) while second injector terminals are operably coupled to the P-type QW channel(s).
  • connection to the cathode terminals 40A and 40B (which collectively form the cathode terminal 40 of the device) is provided by etching to the N+ bottom layer 153, and depositing a metal layer (for example AuGe/Ni/Au) to form an ohmic contact to N+ bottom layer
  • the resulting structured is isolated from other devices by etching down to the substrate 149.
  • the structure is then subject to rapid thermal anneal (RTA) to activate the implants.
  • RTA rapid thermal anneal
  • a diffraction grating (as described in more detail in U.S. Patent 6,021,243, inco ⁇ orated by reference above in its entirety) and top DBR mirror are formed on this structure as described above.
  • the diffraction grating is omitted.
  • the diffraction grating when used, is created over the active device structure described above.
  • the top DBR mirror is preferably created by the deposition of one or more dielectric layer pairs (179,180), which typically comprise SiO 2 and a high refractive index material such as GaAs, Si, or GaN, respectively.
  • FIG. 3D illustrates an alternate epitaxial growth structure utilizing group III-V materials for realizing a heterojunction thyristor and associated optoelecttical/optical devices in accordance with the present invention.
  • the structure of FIG. 3D can be made, for example, using known molecular beam epitaxy (MBE) techniques.
  • MBE molecular beam epitaxy
  • a first semiconductor layer 151 of AlAs and a second semiconductor layer 152 of GaAs are alternately deposited (with preferably at least seven pairs) upon a semi-insulating gallium arsenide substrate 149 in sequence to form the top dielectric distti Vietnamese bragg reflector (DBR) mirror 12.
  • DBR dielectric disttimped bragg reflector
  • the number of AlAs layers will preferably always be one greater than the number of GaAs layers so that the first and last layers of the mirror are shown as layer 151.
  • the AlAs layers 151 are subjected to high temperature steam oxidation to produce the compound Al x O y so that a mirror will be formed at the designed center wavelength. Therefore the thicknesses of layers 151 and 152 in the mirror are chosen so that the final optical thickness of GaAs and Al x O y is a quarter wavelength of the center wavelength ⁇ o.
  • the mirrors could be grown as alternating layers of one quarter wavelength thickness of GaAs and AlAs at the designed wavelength so that the oxidation step is not used. In that case, many more pairs are required (with typical numbers such as 22 pairs) to achieve the reflectivity needed for efficient lasing.
  • the active device structure which consists of two HFET devices.
  • the first of these is the above-described p-channel HFET (PHFET) 11, which has one or more p-type modulation doped quantum wells and is positioned with the gate tenninal on the bottom (i.e. on the mirror 12 just described) and the collector terminal above.
  • the second of these is an n-channel HFET (NHFET) 13, which has one or more n-type modulation doped quantum wells and is positioned with the gate tenninal on top and the collector terminal below.
  • the collector region of the NHFET device 13 also functions as the collector region of the PHFET device 11.
  • the collector tenninal of the NHFET device 13 is a p-type contact to p-type quantum well(s) disposed below (above) the collector region, while the collector terminal of the PHFET device 11 is a n-type contact to n-type quantum well(s) disposed above the collector region. Therefore a non-inverted n-channel device is stacked upon an inverted p-channel device to form the active device structure.
  • the active-device layer structure begins with layer 153 of N+ type GaAs that enables the formation of ohmic contacts thereto (for example, when contacting to the cathode terminal of a heterojunction thyristor device, the gate terminal of an inverted p-channel HFET device, the sub- collector terminal of an n-channel HFET device, or the emitter terminal of a p-type quantum-well- base bipolar transistor device).
  • Layer 153 has a typical thickness of 1000-2000 A and a typical n- type doping of 3.5xl0 18 cm "3 .
  • the N+ doped GaAs layer 153 corresponds to the ohmic contact layer 14 of FIG. 2 A.
  • layer 166a of n-type AlAs having a typical thickness of 30-200 A and a typical n-type doping of 3.5xl0 18 cm “3 .
  • This layer 166a serves optically as the lower waveguide cladding layers for all laser, amplifier and modulator structures. In addition, it also acts as a etch stop layer (described below in more detail) when forming contacts to the ohmic contact layer 153.
  • layer 166a Another constraint on the thickness of layer 166a is that it must be made sufficiently thin to enable hole current to flow through it by tunneling. In this manner, the thickness of this layer 166a determines the current gain of an inverted p-type quantum- well-base bipolar transistor device realized in this growth structure.
  • a layer 166b of undoped GaAs having a typical thickness of 6-20 A.
  • This layer 166b serves to prevent oxidation of the layer 166a during subsequent oxidation operations (e.g., where the bottom DBR mirror layers 151/152 are oxidized).
  • undoped GaAs layer 166b is advantageous in a single aluminum effusion cell MBE system because it accommodates a growth interruption to change the growth temperature between layers 166a and 155b as required.
  • the N+ AlAs layer 166a corresponds to the n-type layer 16 of FIG.
  • the undoped GaAs layer 166b and the undoped GaAs layer 155b corresponds to the undoped spacer layer 18 of FIG. 2 A.
  • the thickness of layers 166b and 155b are preferably on the order of 300 A.
  • the thickness of layers 166b and 155b are preferably on the order of 250 A.
  • the next layers define the quantum well(s) that form the inversion channel(s) during operation of the PHFET 11.
  • this consists of a spacer layer 156 of undoped GaAs that is about 10-25 A thick and then combinations of a quantum well layer 157 (that is about 40-80 A thick) and a barrier layer 158 of undoped GaAs.
  • the quantum well layer 157 may be comprised of a range of compositions.
  • the quantum well is formed from a In 0.2 Ga 0 . 8 AsN composition with the nitrogen content varying from 0% to 5% depending upon the desired natural emission frequency.
  • the nitrogen content will be 0%; for a natural emission frequency of 1.3 ⁇ m, the nittogen content will be approximately 2%; and for a natural emission frequency of 1.5 ⁇ m, the nitrogen content will be approximately 4-5%.
  • the well-barrier combination will typically be repeated (for example, three times as shown) to define the quantum wells that fonn the inversion channels during operation of the PHFET 11 (however single quantum well structures are also possible). Unstrained quantum wells are also possible. Following the last barrier of undoped GaAs is a layer 167 of undoped GaAs and a layer 159 of undoped Al x2 Ga ⁇ -x2 As.
  • the undoped GaAs layer 167 has a typical thickness of
  • the undoped Al x Ga ⁇ -x2 As layer 159 has a typical thickness of 0.5 ⁇ m.
  • the pu ⁇ ose of the GaAs layer 167 is to accommodate a change in the growth temperature from about 530°C (as required for the InGaAs quantum well structure of layer 157) to about 610°C (as required for Al x2 Ga ⁇ - x2 As layer 159).
  • layer 167 performs no electrical pu ⁇ ose and so it should be electrically totally transparent to all current flows. Therefore, layer 167 is thin enough that currents may conduct through it by tunneling with negligible voltage drop. All of the layers grown thus far form the PHFET device 11 with the gate contact on the bottom.
  • the layers between the P+ AlGaAs layer 155c and the last undoped GaAs barrier layer 158 correspond to the p-type modulation doped heterojunction QW structure 20 of
  • Undoped GaAs layer 167 and undoped AlGaAs layer 159 corresponds to the undoped spacer layer 22 of FIG. 2A.
  • Layers 167 and 159 also form the collector region of the NHFET device 13.
  • Deposited on layer 159 are two layers 160a, 160b (collectively 160) of undoped GaAs of about 200-250 A total thickness, which form the barrier of the first n-type quantum well.
  • Layer 160 is thicker than the nonnal barrier layer of about 100 A because it accommodates a change of the growth temperature from 610°C (as required for the Al x2 Ga ⁇ - x2 As layer 159) to about 530°C (as required for the In 0 . 2 Gao. 8 As quantum well layer 161).
  • the next layer 161 is the quantum well of In 0 . 2 Ga 0 . 8 As, which is undoped and about 40-80 A in thickness.
  • the quantum well layer 161 may be comprised of a range of compositions as described above with respect to the quantum well layer 157.
  • the quantum well is formed from an In 0 . 2 Gao. 8 AsN composition with the nitrogen content varying from 0% to 5% depending upon the desired natural emission frequency.
  • the n-type quantum well layer 161 need not be of the same formulation as the p-type quantum well layer 157.
  • the barrier- well combination will typically be repeated (for example, three times as shown) to define the quantum wells that form the inversion channel(s) during operation of the NHFET 13. Then there is a barrier layer 162 of about 10-30 A of undoped GaAs which accommodates a growth interruption and a change of growth temperature.
  • Three layers (163a, 163b, 163c) of Al ⁇ Ga ⁇ As of about 300-500 A total thickness include a spacer layer 163a of undoped Al x2 Ga ⁇ - x2 As that is about 20- 30 A thick, a modulation doped layer 163b of N+ type doping of Al x2 Ga 1 . x2 As (with doping about 3.5xl0 18 cm “3 ) that is about 80 A thick, and a spacer layer 163c of undoped Al ⁇ Ga ⁇ As that is about 200-300 A thick.
  • a layer 168a of undoped GaAs that is about 6-20 A thick, and a P+ type doped layer 168b of AlAs (with doping about 3.5xl0 18 cm “3 ) that is about 300 A.
  • layer 168b should never be totally depleted in operation (i.e., the total doped charge in layer 168b should always exceed that in layer 163b).
  • Layers 168b and 163b (and the undoped spacer layers 163c and 168a therebetween) form the two plates of a parallel plate capacitor which forms the field-effect input to all active devices.
  • layer 163a is the upper SCH region.
  • Layer 168b also acts as a etch stop layer (described below in more detail) when forming contacts to the N-type inversion channel(s) of the NHFET 13 (for example, when contacting to the N-channel injector terminal(s) of a heterojunction thyristor device, the source/drain terminals of an n-channel HFET device, the base terminal of an n-type p- type quantum- well-base bipolar ttansistor, or the collector terminal of a p-type quantum-well-base bipolar ttansistor device).
  • Layer 168a serves to prevent oxidation of previous layers 163a, 163b, 163c of Al x2 Ga 1 - x2 As during subsequent oxidation operations (e.g., where the bottom DBR mirror layers are oxidized). Moreover, similar to layer 166b, layer 168a must be made sufficiently thin to enable electron current to flow through it by tunneling. In this manner, the thickness of this layer 168a determines the current gain of an n-type quantum-well-base bipolar ttansistor device realized in this growth structure. In addition, undoped GaAs layer 168a is advantageous in a single aluminum effusion cell MBE system because it accommodates a growth interruption to change the growth temperature between layers 163c and 168b as required.
  • the layers between the undoped GaAs barrier layer 160a and the N+ AlGaAs layer 163b correspond to the n-type modulation doped heterojunction QW structure 24 of FIG. 2A.
  • Undoped AlGaAs layer 163 c and undoped GaAs layer 168a corresponds to the undoped spacer layer 26 of FIG. 2A.
  • the thickness of layers 163c and 168a are preferably on the order of 300 A.
  • the thickness of layers 163c and 168a are preferably on the order of 250 A.
  • a layer 164 of p-type GaAs is deposited next to form part of the upper waveguide cladding layer for the laser, amplifier and modulator devices. It also forms a spacer layer in which to accommodate the aperture implant which steers the current into the VCSEL active region. It should provide a low resistance access to the top contact. It has a typical thickness of 300 A.
  • the p-type layers 168b and 164 correspond to the p-type layer(s) 28 of FIG. 2A.
  • an ohmic contact layer 165 (which may comprise a single layer of GaAs or a combination of GaAs (165a) and InGaAs (165b) as shown).
  • GaAs layer 165a is about 50-100 A thick and doped to a very high level of P+ type doping (about lxl 0 20 cm "3 ) and InGaAs layer 165b is about 25-50 A thick and doped to a very high level of P+ type doping (about lxl 0 20 cm "3 ) to enable the best possible ohmic contact.
  • FIG. 3E The band diagram of the FIG. 3D structure is shown in FIG. 3E.
  • a diffraction grating (as described in more detail in U.S. Patent 6,021,243, inco ⁇ orated by reference above in its entirety) and top DBR mirror are formed over the active device structure described above.
  • the diffraction grating When the heterojunction thyristor device is operating in the lasing mode, the diffraction grating performs the function of diffracting light produced by the vertical cavity into light propagating laterally in a waveguide which has the top DBR mirror and bottom DBR mirror as waveguide cladding layers and which has lateral confinement regions (typically formed by implants as described herein in more detail).
  • the diffraction grating When the heterojunction thyristor device is operating in the optical detection mode, the diffraction grating performs the function of diffracting incident light that is propagating in the lateral direction into the vertical cavity mode, where it is absorbed resonantly in the vertical cavity.
  • light may enter and exit the resonant vertical cavity vertically through an optical aperture in the top surface of the device.
  • the diffraction grating is omitted
  • the top DBR mirror defines a cavity for the vertical emission and abso ⁇ tion of light
  • the device operates as a vertical cavity surface emitting laser/detector.
  • the distance between the top DBR mirror and bottom DBR mirror preferably represents an integral number of 1/4 wavelengths at the designated wavelength.
  • the thickness of layer 164 or 159 is adjusted to enable this condition.
  • a heterojunction thyristor can be realized as shown in FIG. 3F.
  • alignment marks (not shown) are defined by etching, and then a layer of Si N or Al 2 O 3 or other suitable dielectric (not shown) is deposited to act as protection for the surface layer and as a blocking layer for subsequent ion implants.
  • this dielectric layer also forms the first layer of the top DBR mirror.
  • an ion implant 175 of n-type is performed using a photomask that is aligned to the alignments marks, and an optical aperture is defined by the separation between the implants 175.
  • the implants 175 create a p-n junction in the layers between the n-type quantum well(s) and the surface, and the aperture between the implants defines the region in which the current may flow, and therefore the optically active region 177 as shown.
  • the current cannot flow into the n-type implanted regions 175 because of the barrier to current injection.
  • the current flow trajectory is shown in FIG. 3F as arrows.
  • the laser threshold condition is reached before the voltage for turn-on of this barrier.
  • the refractory anode terminals 36A and 36B (which collectively form the anode terminal 36 of the device) are deposited and defined.
  • an ion implant 170 of n+-type is performed using a photomask that is aligned to the alignments marks, to thereby form contacts to the n-type QW inversion channel(s).
  • a chlorine-based gas mixture that includes fluorine is used as an etchant to etch down to the etch-stop layer 168b.
  • the etch rate through the InGaAs layer 165b and GaAs layers (165a and 164) is fairly rapid. However, because of the presence of fluorine in the etchant, the etch rate decreases drastically when the AlAs layer 168b is encountered. This is because the AlAs layer 168b has a high percentage of Aluminum, which forms A1F in the presence of the etch mixture.
  • the A1F deposits on the surface of the structure and prevents further etching (because it is nonvolatile and not etched by any of the conventional etchants).
  • the AlAs layer 168b operates as an etch stop layer.
  • This layer is then easily dissolved in de-ionized (Dl) water or wet buffered hydrofluoric acid (BHF) to form mesas at the undoped GaAs layer 168a.
  • Dl de-ionized
  • BHF wet buffered hydrofluoric acid
  • the resulting mesas at the undoped GaAs layer 168a is subject to the N+ ion implants 170, which are electrically coupled to the N-channel injector terminals 38A and 38B.
  • the N-channel injector terminals 38A and 38B are preferably formed via deposition of an n-type Au alloy metal on the N+ ion implants
  • an ion implant 171 of p+-type is performed using a photomask that is aligned to the alignments marks, to thereby form contacts to the p-type QW inversion channel(s).
  • mesas are formed by etching preferably down to the undoped GaAs layer 158.
  • the resulting mesas are then subject to P+ ion implants 171, which are electtically coupled to the P- channel injector terminals 38C and 38D.
  • the P-channel injector terminals 38C and 38D are preferably formed via deposition of an p-type alloy metal on, the P+ ion implants 171 to form ohmic contacts thereto.
  • the P+ ion implants 171 may be omitted.
  • the N-channel injector terminals 38A and 38B (which are coupled to the n-type inversion QW channel(s) of the NHFET 13 device by the N+ ion implants 170) are used to control charge in such n-type inversion QW channel(s) as described herein.
  • the N+ ion implants 170 (and corresponding N-channel injector terminals 38A and 38B) may be omitted.
  • the P-channel injector terminals 38C and 38D (which are coupled to the p-type inversion QW channel(s) of the PHFET 11 device by the P+ ion implants 171) are used to control charge in such p-type inversion QW channel(s) as described herein.
  • connection to the cathode terminals 40A and 40B the device is made by etching with a chlorine-based gas mixture that includes fluorine. This etch is performed down to the AlAs etch stop layer 166a as described above. This layer 166a is then easily dissolved in de-ionized (Dl) water or wet buffered hydrofluoric acid (BHF) to form resulting mesas in the N+ layer 153. A metal layer (for example AuGe/Ni/Au) is deposited on the mesas at the N+ layer 153 to formed an ohmic contact thereto. The resulting structured is isolated from other devices by etching down to the substrate 149. The structure is then subject to rapid thermal anneal (RTA) to activate the implants.
  • RTA rapid thermal anneal
  • a diffraction grating 32 (as described in more detail in U.S. Patent 6,021,243, inco ⁇ orated by reference above in its entirety) and top DBR mirror is deposited on this structure as described above.
  • the diffraction grating 32 is omitted.
  • the top DBR mirror is preferably created by the deposition of one or more dielectric layer pairs (179,180), which typically comprise SiO 2 and a high refractive index material such as GaAs, Si, or GaN, respectively.
  • a heterojunction thyristor device which is configured to convert a digital optical signal to a corresponding digital electrical signal as described above, is used as the basis for a photonic digital-to-analog converter that converts a digital word encoded by a plurality of input digital optical signals to an output analog electrical signal corresponding to the digital word.
  • FIG. 4A A first exemplary embodiment of the photonic digital- to analog converter 201 is shown in FIG. 4A.
  • the input digital optical signals synchronously encode a plurality of bits of information that are logically arranged from a most-significant-bit (MSB) to a least-significant-bit (LSB) as shown in FIGS. 4A and 4B(i). These bits form a digital word.
  • four (4) input digital optical signals encode four (4) bits of infonnation logically arranged from a most-significant-bit (MSB) to a least-significant-bit (MSB- 3 ).
  • a plurality of heterojunction thyristor devices (4 shown as 202 M SB, 202MSB-I, 202 M SB-2, 202 M SB-3), each corresponding to a different input digital optical signal/bit, are formed in resonant cavities on at least one substrate.
  • the plurality heterojunction thyristor devices are integrally fonned in resonant cavities on a common substrate.
  • a plurality of voltage divider networks (4 shown as 204 SB , 204MSB-I, 204MSB-2, 204 MSB - 3 ), each corresponding to a different heterojunction thyristor device and input digital optical signal/bit, are operably coupled to the cathode terminal of the heterojunction thyristor devices (202 M S B , 202 MSB - I , 202MSB-2, 202MSB-3)-
  • a summing circuit 206 is operably coupled to the voltage divider networks (204 MS B, 204 M SB-I, 204MSB-2, 204MSB-3) as shown.
  • a timing signal generator 207 generates an electrical timing signal A and an electrical timing signal B as shown in FIG.
  • the electrical timing signal A includes a sampling clock pulse whose duration defines a sampling period that overlaps the bits of information encoded in the input digital optical signals.
  • the electrical timing signal B includes a summing clock pulse whose duration defines a summing period that is subsequent to the sampling period.
  • the plurality of input optical signals are injected into the resonant cavities, where such signals are resonantly absorbed by the heterojunction thyristor devices (204 MSB , 202 MSB - I , 202 MSB -2, 202MS B - 3 )-
  • Each heterojunction thyristor device is configured (as described above with respect FIGS. 2B1, 2B3, 2C, and 2D1) to operate during a given sampling period to convert the input digital optical signal supplied thereto to a corresponding digital electrical signal.
  • the voltage divider networks (204 M SB, 204MSB-I, 204MSB-2, 204MSB-3) are configured to scale the magnitude of the digital electtical signals produced by the heterojunction thyristor devices (202 M SB, 202 M SB-I, 202 M SB-2, 202 M SB-3) to produce output electrical signals (VMSB, V M SB-I, V M SB-2, V MSB - 3 ) whose magnitude corresponds to the bits encoded by the input digital optical signals.
  • the voltage divider networks (204MSB, 204MSB-I, 204 M SB-2, 204MSB-3) shown in FIG. 4A scale the magnitude of the digital electrical signals produced by the heterojunction thyristor devices
  • the scaling function for a given voltage divider network can be represented generally by a scale factor of (1/2 X ), where X is the difference between the position of the corresponding bit and the MSB.
  • the summing circuitry 206 operates during the summing period to sum the output electtical signals (VMSB, VMSB-I, VMSB-2, VMSB-3) produced by the voltage divider networks (204 M SB, 204 M SB-I, 204 MSB - 2 , 204 MS B- 3 )-
  • the result of the summing operation performed by the summing circuitry 205 which is output from the summing circuitry 206, is an analog electric signal whose magnitude corresponds to the digital word encoded by the bits of the input digital optical signals.
  • the summing circuit 206 of FIG. 4A sums the four (4) output electrical signals to produce a resultant analog signal whose magnitude corresponds to the digital word encoded by the four(4) bits of the input digital optical signals as shown in the following table II.
  • the summing circuitry 206 includes a chain of two-port adding nodes 208 and sample/hold circuits 210 arranged as pairs, each pair corresponding to a different voltage divider network (204MSB-I, 204MSB-2, 204MSB-3) as shown.
  • the output electtical signal generated by a given voltage divider network is supplied to an input node of the corresponding two- port adding node 208.
  • a single sample/hold circuit 211 supplies an output electrical signal (V MSB ) whose magnitude corresponds to the MSB to the chain of two-port adding nodes 208 and sample/hold circuits 210.
  • each sample and hold circuit 210 and 211 includes an input capacitance that operates to store the electrical signal generated by a given voltage divider network and supplied thereto during a given sampling period for summation during the subsequent summing period.
  • such conversion operations are repeated for another digital word that is subsequently encoded by the input digital optical signals supplied to the converter 201 as described above.
  • each heterojunction thyristor device operates to convert the input digital optical signal supplied thereto to a corresponding digital electrical signal as described above with respect to FIGS. 2B1, 2B3, 2C, and 2D1.
  • the length and width of the given heterojunction thyristor device are sized such that it switches from a non-conducting/OFF state to a conducting/ON state when the combination of i) the injection of electrical energy into the
  • the QW channel(s) of the device from the electrical sampling clock pulse and ii) abso ⁇ tion of optical energy in the QW channel(s) of the device from the ON pulse of the input optical signal produces a channel current that exceeds the bias current I BIAS such that charge in the QW channel(s) of the device build to a level that is greater than the critical switching charge Q CR -
  • the bias current I BIAS reduces the charge in QW channel(s) of the device to a level below the holding charge Q H , thereby causing the device to switch from the conducting/ON state to the non-conducting/OFF state.
  • the device does not switch from the non-conducting/OFF state to the conducting/ON state in the event that either the electrical sampling clock pulse is not present or the input optical signal represents the OFF logic level. This occurs because these signals alone are not sufficient to produce the critical switching charge Q CR .
  • the heterojunction thyristor device can be configured to operate as an electtically-conttolled sampling device (e.g., electrically-controlled switch), which is suitable for use in a sample and hold circuit (such as sample and hold circuits 210/211 in FIG. 4A) and in many other signal processing applications (such as switched capacitance filters and switched capacitance waveform generators).
  • a sample and hold circuit such as sample and hold circuits 210/211 in FIG. 4A
  • signal processing applications such as switched capacitance filters and switched capacitance waveform generators
  • a first p-channel injector terminal 222 (the electtical input terminal) and a second p-channel injector terminal 224 (the electtical output terminal) are operably coupled to opposite ends of the p-type QW channel(s) of structure 20.
  • An electtical sampling clock pulse in the form of a downward running electrical pulse is supplied to the n-channel injector terminal(s) 226 of the device.
  • a bias current source is coupled to the n-channel injector terminal(s) 226 and draws charge from the n-type QW channel(s) to the positive supply voltage potential V D -
  • the anode terminal 228 is forward biased (e.g. biased positively) with respect to the cathode terminal 230.
  • the length and width of the device are sized such that it switches from a non- conducting/OFF state to a conducting/ON state when the electtical energy injected into the n-type QW channel(s) of structure 24 by the electrical sampling clock pulse produces a channel current that exceeds the bias current I BIAS such that charge in the n-type QW channel(s) of structure 24 builds to a level that is greater than the critical switching charge QCR.
  • the bias current I BIAS reduces the charge in the n-type QW channel(s) to a level below the holding charge Q H , thereby causing the device to switch from the conducting/ON state to the non-conducting/OFF state.
  • the device does not switch from the non- conducting/OFF state to the conducting/ON state in the event that the electtical sampling clock pulse is not present. This occurs because there is no injection of electrical energy into the QW channel(s) of the device to produce the critical switching charge Q CR .
  • the electtical input terminal 222 When the device is operating in the non-conducting/OFF state, the electtical input terminal 222 is electtically isolated from the electrical output tenninal 224. However, when the device is operating in the conducting/ON state, the electrical input terminal 222 is electrically coupled to the electrical output terminal 224 (and there is minimal potential voltage differences between input terminal 222 and output terminal 224). In this manner, the heterojunction thyristor device operates as a sampling device (e.g., switch) that is selectively activated and deactivated by an electric control signal (e.g., the sample clock pulse).
  • an electric control signal e.g., the sample clock pulse
  • a first n-channel injector terminal 232 (the electrical input terminal) and a second n-channel injector tenninal 234 (the electrical output terminal) are operably coupled to opposite ends of the n-type QW channel(s) of structure 24.
  • An electrical sampling clock pulse in the form of a upward running electrical pulse is supplied to the p-channel injector terminal(s) 236 of the device.
  • a bias current source is coupled to the p-channel injector terminal(s) 236 and draws charge from the p-type QW channel(s) to the ground potential.
  • the anode terminal 238 is forward biased (e.g. biased positively) with respect to the cathode tenninal 240.
  • the length and width of the device are sized such that it switches from a non-conducting/OFF state to a conducting/ON state when the electrical energy injected into the p-type QW channel(s) of structure 20 by the electtical sampling clock pulse produces a channel current that exceeds the bias cureent I BI A S such that charge in the p-type QW channel(s) of structure 20 builds to a level that is greater than the critical switching charge Q CR .
  • the bias current I BIAS reduces the charge in the p-type QW channel(s) to a level below the holding charge Q H , thereby causing the device to switch from the conducting/ON state to the non- conducting/OFF state.
  • the device does not switch from the non-conducting/OFF state to the conducting/ON state in the event that the electrical sampling clock pulse is not present. This occurs because there is no injection of electrical energy into the QW channel(s) of the device to produce the critical switching charge Q CR .
  • the electrical input terminal 232 When the device is operating in the non-conducting/OFF state, the electrical input terminal 232 is electtically isolated from the electtical output terminal 234. However, when the device is operating in the conducting/ON state, the electrical input terminal 232 is electtically coupled to the electrical output terminal 234 (and there is minimal potential voltage differences between input terminal 232 and output terminal 234). In this manner, the heterojunction thyristor device operates as a sampling device (e.g., switch) that is selectively activated and deactivated by an electric control signal (e.g., the sample clock pulse).
  • an electric control signal e.g., the sample clock pulse
  • FIG. 4E Another photonic digital-to analog converter 201' is shown in FIG. 4E. Similar to the embodiment of FIG. 4A, the input digital optical signals synchronously encode a plurality of bits of information that are logically arranged from a most-significant-bit (MSB) to a least-significant-bit (LSB) as shown in FIGS. 4B(i). These bits form a digital word. In the exemplary embodiment shown, four (4) input digital optical signals encode four (4) bits of information logically arranged from a most-significant-bit (MSB) to a least-significant-bit (MSB. 3 ).
  • MSB most-significant-bit
  • MSB least-significant-bit
  • a plurality of heterojunction thyristor devices (4 shown as 302MSB, 302MSB-I, 302MSB-2, 302MSB-3), each corresponding to a different input digital optical signal/bit, are formed in resonant cavities on at least one substrate.
  • the plurality of heterojunction thyristor devices are integrally formed in resonant cavities on a common substrate.
  • Each heterojunction thyristor device is configured as a sampling device (e.g., switch) in a manner similar to the sampling device described below with respect to FIGS. 6A and 6B, whereby the n-channel injector terminals form the electtical input terminal 304 and the electrical output terminal 306.
  • a bias current source is coupled to the p-channel injector terminal(s) 308 and draws charge from the QW channel(s) coupled thereto.
  • the anode terminal 310 is forward biased (e.g. biased positively) with respect to the cathode terminal 312. As described below in detail with FIGS.
  • each heterojunction-thyristor-based sampling device is sized such that it switches from a non-conducting/OFF state to a conducting/ON state when the combination of i) the injection of electrical energy into the QW channel(s) of the device from the electtical sampling clock pulse and ii) abso ⁇ tion of optical energy in the QW channel(s) of the device from the ON pulse of the input optical signal produces a channel current that exceeds the bias current I BI A S such that charge in the QW channel(s) of the device build to a level that is greater than the critical switching charge Q C R.
  • the bias current I BIAS reduces the charge in QW channel(s) of the device to a level below the holding charge Q H , thereby causing the device to switch from the conducting/ON state to the non- conducting/OFF state. Note that the device does not switch from the non-conducting/OFF state to the conducting/ON state in the event that either the electrical sampling clock pulse is not present or the input optical signal represents the OFF logic level. This occurs because these signals alone are not sufficient to produce the critical switching charge Q CR .
  • a clock generator 207' generates an electrical clock signal that is supplied to the n-channel injector tenninal(s) 308 for injection into the QW channel(s) coupled thereto.
  • the electtical clock signal includes downward running electtical clock pulses that define active sampling periods whose duration overlaps the bits of information encoded in the input digital optical signal as shown in FIG. 4B(i).
  • the input digital optical signals are supplied to the resonant cavities for resonant abso ⁇ tion by the device 201'.
  • a plurality of voltage references (4 shown as 316MSB, 316MSB-I, 316MSB-2, 316MSB-3), each conesponding to a different heterojunction thyristor device, are operably coupled to the electtical input terminal 304 of the corresponding heterojunction thyristor device.
  • the voltage reference and corresponding heterojunction thyristor-based sampling device cooperate to generate at the electtical output terminal 306 a voltage signal (VMSB,NMSB- ⁇ , V MSB - 2 , or V MSB - 3 ) representing the contribution of the bit in the digital word in accordance with the input digital optical signal supplied thereto. Examples of such voltage signals are shown above in table I.
  • a summing circuit 206' is operably coupled to the output tenninals of the heterojunction- thyristor-based sampling devices as shown.
  • the summing circuitry 206' operates during the summing period to sum the voltage signals (VMSB, VMSB-I, VMSB-2, and VMSB-3) produced at the output terminals 306 of the sampling devices.
  • the result of the summing operation performed by the summing circuitry 206', which is output from the summing circuitry 206, is an analog electric signal whose magnitude corresponds to the digital word encoded by the bits of the input digital optical signals.
  • the summing circuitry 206' includes a heterojunction-thyristor-based electrically-controlled sampling device as described above with respect to FIGS. 4C and 4D.
  • the voltage signals (VM S B, VMSB-I, VMSB-2, VMSB-3) produced at the output terminals
  • FIG. 4B(iii)) to thereby effectuate the summing operation, which produces the output analog electtical signal as described above.
  • the heterojunction-thyristor-based sampling device of circuit 206' includes an input capacitance that operates to store the sum of the voltage signals
  • VM S B V MS B-I, V MS B-2, VM S B-3
  • such conversion operations are repeated for another digital word that is subsequently encoded by the input digital optical signals supplied to the converter 201' as described above.
  • VREF maximum voltage level
  • the injector terminal of the device is operably coupled to the N-type QW channel(s) realized in the N-type modulation doped QW(s) structure of the device.
  • the sampling clock pulse of FIG. 4B(ii) is in the form of a downward running electrical pulse supplied to the injector terminal of the device.
  • the bias current source draws charge from the n-type QW channel(s) to the positive supply voltage potential
  • the injector terminal of the device may be operably coupled to the p-type QW channel(s) realized in the P-type modulation doped QW(s) structure of the device. In such a configuration, the sampling clock pulse of FIG.
  • the summing clock pulse of FIG. 4B(iii) is shown as a downward rumiing electtical clock pulse. Such a pulse is suitable to activate a heterojunction-based sample and hold circuit as described above with respect to FIG. 4C.
  • the summing clock pulse of FIG. 4B(iii) can be an upward running electtical clock pulse. Such a pulse is suitable to activate a heterojunction-thyristor-based sample and hold circuit as described above with respect to FIG. 4D.
  • FIG. 5 A Another photonic digital-to analog converter 251 is shown in FIG. 5 A. Similar to the embodiment of FIG. 4A, the input digital optical signals synchronously encode a plurality of bits of information that are logically arranged from a most-significant-bit (MSB) to a least-significant-bit (LSB) as shown in FIGS. 5 A and 5B(i). These bits form a digital word. In the exemplary embodiment shown, four (4) input digital optical signals encode four (4) bits of information logically arranged from a most-significant-bit (MSB) to a least-significant-bit (MSB. 3 ).
  • MSB most-significant-bit
  • MSB least-significant-bit
  • a plurality of heterojunction thyristor devices (4 shown as 252MSB, 252MSB-I, 252MSB-2, 252MSB-3), each corresponding to a different input digital optical signal/bit, are formed in resonant cavities on at least one substrate.
  • the plurality of heterojunction thyristor devices are integrally formed in resonant cavities on a common substrate.
  • a plurality of voltage divider networks (4 shown as 254MSB, 254MSB-I, 254MSB-2, 254M S B-3), each corresponding to a different heterojunction thyristor device and input digital optical signal/bit, are operably coupled to the cathode terminal of the heterojunction thyristor devices (252MSB, 252MSB-I, 252MSB-2, 252MSB-3)-
  • a summing circuit 256 is operably coupled to the voltage divider networks (254MSB, 254MS B -U 254 MS B- 2 , 254 MSB - 3 ) as shown.
  • An optical clock generator (not shown) generates a plurality of optical timing A signals and optical timing B signals as shown in FIG.
  • Each optical timing A signal includes a sampling clock pulse whose duration defines a sampling period that overlaps the bits of information encoded in the input digital optical signals.
  • Each optical timing B signal includes a summing clock pulse whose duration defines a summing period that is subsequent to the sampling period.
  • the plurality of input optical signals and the plurality of optical timing A signals are injected into the resonant cavities, where such signals are resonantly absorbed by the heterojunction thyristor devices (252M S B, 252MSB-I, 252MSB-2, 252MSB-3)-
  • Each heterojunction thyristor device is configured (as described above with respect FIGS. 2B2, 2B4, 2C and 2D2) to operate during a given sampling period to convert the input digital optical signal supplied thereto to a corresponding digital electrical signal.
  • each heterojunction thyristor device switches from the non-conducting/OFF state to the conducting/ON state in the event that both the optical sampling clock pulse is present and the input optical signal represents the ON logic level. This occurs because the combination of these signals are sufficient to produce the critical switching charge Q CR .
  • each heterojunction thyristor device does not switch from the non-conducting/OFF state to the conducting/ON state in the event that either the optical sampling clock pulse is not present or the input optical signal represents the OFF logic level.
  • the voltage divider networks (254MSB, 254MSB-I, 254MSB-2, 254MSB-3) are configured to scale the magnitude of the digital electrical signals produced by the heterojunction thyristor devices (252MSB, 252MSB-I, 252 M SB-2, 252 M SB-3) to produce output electtical signals (VMSB, VMSB-I, VMSB-2, VMSB- 3 ) whose magnitude conesponds to the bits encoded by the input digital optical signals.
  • A scale the magnitude of the digital electrical signals produced by the heterojunction thyristor devices (202MSB, 202MSB-I, 202MSB-2, 202MSB- 3 ) by factors of 1, 1/2, 1/4, and 1/8, respectively, to produce output electrical signals as shown in the Table I above.
  • the scaling function for a given voltage divider network can be represented generally by a scale factor of (1/2 ), where X is the difference between the position of the corresponding bit and the MSB.
  • the summing circuitry 256 operates during the summing period to sum the output electrical signals (VMSB, VMSB-I, VMSB-2, VMSB-3) produced by the voltage divider networks (254 M SB, 254 M SB-I, 254 MSB - 2 , 254 MSB - 3 )-
  • the result of the summing operation performed by the summing circuitry 256, which is output from the summing circuitry 256, is an analog electric signal whose magnitude corresponds to the digital word encoded by the bits of the input digital optical signals.
  • the summing circuit 256 of FIG. 5 A sums the four (4) output electrical signals to produce a resultant analog signal whose magnitude corcesponds to the digital word encoded by the four (4) bits of the input digital optical signals as shown in the Table II above.
  • the summing circuitry 256 includes a chain of two-port adding nodes 258 and sample/hold circuits 260 arranged as pairs, each pair correspond to a different voltage divider network (254MSB-I, 254M S B-2, 254MSB-3) as shown.
  • the output electrical signal generated by a given voltage divider network is supplied to an input node of the corresponding two- port adding node 258.
  • a single sample/hold circuit 261 supplies an output electtical signal (V MSB ) whose magnitude corresponds to the MSB to the chain of two-port adding nodes 258 and sample/hold circuits 260.
  • each sample and hold circuit 260 and 261 includes an input capacitance that operates to store the electtical signal generated by a given voltage divider network and supplied thereto during a given sampling period for summation during the subsequent summing period.
  • such conversion operations are repeated for another digital word that is subsequently encoded by the input digital optical signals supplied to the converter 251 as described above.
  • the heterojunction thyristor device can be configured to operate as an optically-controlled sampling device (e.g., optically-controlled switch), which is suitable for use in a sample and hold circuit (such as sample and hold circuits 260/261 in FIG. 5A) and in many other signal processing applications (such as switched capacitance filters and switched capacitance waveform generators).
  • an optically-controlled sampling device e.g., optically-controlled switch
  • sample and hold circuit such as sample and hold circuits 260/261 in FIG. 5A
  • signal processing applications such as switched capacitance filters and switched capacitance waveform generators
  • a first p-channel injector terminal 272 (the electrical input terminal) and a second p-channel injector terminal 274 (the electrical output tenninal) are operably coupled to opposite ends of the p-channel QW(s) of structure 20.
  • a bias current source is coupled to the n- channel injector terminal(s) 276 and draws charge from the n-type QW channel(s) to the positive supply voltage potential V D -
  • the anode terminal 278 is forward biased (e.g. biased positively) with respect to the cathode terminal 280.
  • An optical clock signal is supplied to the device for resonant abso ⁇ tion in the n-type QW channel(s) of structure 24 (which is part of the optical sampling region 281 as shown).
  • the optical clock signal includes an optical clock pulse that defines an active sampling period.
  • the length and width of the device is sized such that it switches from a non- conducting/OFF state to a conducting/ON state when abso ⁇ tion of the optical energy from the optical clock pulse produces a channel cmrent that exceeds the bias current I BI A S such that charge in the n-type QW(s) of structure 24 builds to a level that is greater than the critical switching charge Q CR .
  • the bias current I BIAS reduces the charge in the n-type QW(s) channels to a level below the holding charge Q H , thereby causing the device to switch from the conducting/ON state to the non-conducting/OFF state.
  • each heterojunction thyristor device does not switch from the non-conducting/OFF state to the conducting/ON state in the event that the optical sampling clock pulse is not present. This occurs because there is no abso ⁇ tion of optical energy in the QW channel(s) of the device to produce the critical switching charge Q CR .
  • the electtical input terminal 272 When the device is operating in the non-conducting/OFF state, the electtical input terminal 272 is electtically isolated from the electrical output terminal 274. However, when the device is operating in the conducting/ON state, the electtical input terminal 272 is electtically coupled to the electrical output terminal 274 (and there is minimal potential voltage differences between input terminal 272 and output terminal 274). In this manner, the heterojunction thyristor device operates as a sampling device (e.g., switch) that is selectively activated and deactivated by an optical control signal (e.g., the optical clock signal).
  • an optical control signal e.g., the optical clock signal
  • a first n-channel injector terminal 282 (the electtical input terminal) and a second n-channel injector terminal 284 (the electrical output terminal) are operably coupled to opposite ends of the n-channel QW(s) of structure 24.
  • a bias current source is coupled to the p- channel injector terminal(s) 286 and draws charge from the p-type QW channel(s) to the ground potential.
  • the anode terminal 288 is forward biased (e.g. biased positively) with respect to the cathode tenninal 290.
  • An optical clock signal is supplied to the device for resonant abso ⁇ tion in the p-type QW channel(s) of structure 20 (which is part of the optical sampling region 291 as shown).
  • the optical clock signal includes an optical clock pulse that defines an active sampling period.
  • the length and width of the device is sized such that it switches from a non-conducting/OFF state to a conducting/ON state when abso ⁇ tion of the optical energy from the optical clock pulse produces a channel current that exceeds the bias current I BI A S such that charge in the p-type QW(s) of structure
  • the bias current I BIAS reduces the charge in the p-type QW(s) channels to a level below the holding charge Q H , thereby causing the device to switch from the conducting/ON state to the non-conducting/OFF state.
  • each heterojunction thyristor device does not switch from the non-conducting/OFF state to the conducting/ON state in the event that the optical sampling clock pulse is not present. This occurs because there is no abso ⁇ tion of optical energy in the 'QW channel(s) of the device to produce the critical switching charge Q CR .
  • the electrical input terminal 282 When the device is operating in the non-conducting/OFF state, the electrical input terminal 282 is electrically isolated from the electtical output terminal 284. However, when the device is operating in the conducting/ON state, the electrical input terminal 282 is electtically coupled to the electrical output tenninal 284 (and there is a minimal potential voltage difference between the input terminal 282 and the output terminal 284). In this manner, the heterojunction thyristor device operates as a sampling device (e.g., switch) that is selectively activated and deactivated by an optical control signal (e.g., the optical clock signal).
  • an optical control signal e.g., the optical clock signal
  • FIG. 5E Another photonic digital-to analog converter 251' is shown in FIG. 5E. Similar to the embodiment of FIG. 5 A, the input digital optical signals synchronously encode a plurality of bits of information that are logically arranged from a most-significant-bit (MSB) to a least-significant-bit (LSB) as shown in FIGS. 5B(i). These bits form a digital word. In the exemplary embodiment shown, four (4) input digital optical signals encode four (4) bits of information logically arranged from a most-significant-bit (MSB) to a least-significant-bit (MSB -3 ).
  • MSB most-significant-bit
  • MSB least-significant-bit
  • a plurality of heterojunction thyristor devices (4 shown as 302 M SB, 302MSB-I, 302MSB-2, 302M S B-3), each corresponding to a different input digital optical signal/bit, are formed in resonant cavities on at least one substrate.
  • the plurality of heterojunction thyristor devices are integrally formed in resonant cavities on a common substrate.
  • Each heterojunction thyristor device is configured as an optically-controlled sampling device (e.g., switch) in a manner similar to the sampling device described below with respect to FIGS. 7A and 7B, whereby the n-channel injector terminals form the electrical input terminal 304 and the electrical output terminal 306.
  • a bias current source is coupled to the p-channel injector terminal(s) 308 and draws charge from the QW channel(s) coupled thereto.
  • the anode terminal 310 is forward biased (e.g. biased positively) with respect to the cathode terminal 312. As described below in detail with FIGS.
  • each heterojunction-thyristor-based sampling device are sized such that it switches from a non- conducting/OFF state to a conducting/ON state when combination of i) abso ⁇ tion of optical energy in the QW channel(s) of the device from the sampling optical clock pulse of the optical timing signal A and ii) abso ⁇ tion of optical energy in the QW channel(s) of the device from the ON pulse of the input optical signal produces a channel current that exceeds the bias current I BIAS such that charge in the QW channel(s) of the device build to a level that is greater than the critical switching charge Q CR -
  • the bias current I BIAS reduces the charge in QW channel(s) of the device to a level below the holding charge Q H , thereby causing the device to switch from the conducting/ON state to the non-conducting/OFF state.
  • the device does not switch from the non-conducting/OFF state to the conducting/ON state in the event that either the optical sampling clock pulse is not present or the input optical signal represents the OFF logic level. This occurs because these signals alone are not sufficient to produce the critical switching charge QC R .
  • the optical timing signal A includes an optical sampling clock pulse that define an active sampling period whose duration overlaps the bits of information encoded in the input digital optical signal as shown in FIG. 4B(i).
  • the optical timing signal A and the input digital optical signals are supplied to the resonant cavities for resonant abso ⁇ tion by the corresponding heterojunction thyristor devices as shown in FIG. 5E.
  • a plurality of voltage references (4 shown as 316MSB, 316MSB-I, 316MSB-2, 316MSB-3), each corresponding to a different heterojunction thyristor device, are operably coupled to the electrical input terminal 304 of the corresponding heterojunction thyristor device.
  • the voltage reference and corresponding heterojunction thyristor-based sampling device cooperate to generate at the electtical output terminal 306 a voltage signal (NMSBNMSB-i, VMSB-2, or VMSB- 3 ) representing the contribution of the bit in the digital word in accordance with the input digital optical signal supplied thereto. Examples of such voltage signals are shown above in table I.
  • a summing circuit 256' is operably coupled to the output terminals of the heterojunction-thyristor-based sampling devices as shown. The summing circuitry 256' operates during the summing period to sum the voltage signals (VMSB,
  • VMSB- I , V MS B- 2 , and V MSB - 3 produced at the output terminals 306 of the sampling devices.
  • the result of the summing operation performed by the summing circuitry 256', which is output from the summing circuitry 256,' is an analog electric signal whose magnitude corresponds to the digital word encoded by the bits of the input digital optical signals.
  • the summing circuit 256' of FIG. 5E sums the four (4) output electrical signals to produce a resultant analog signal whose magnitude corresponds to the digital word encoded by the four(4) bits of the input digital optical signals as shown above in table II.
  • the summing circuitry 256' includes a heterojunction-thyristor-based optically- controlled sampling device as described above with respect to FIGS. 5C and 5D.
  • the voltage signals (VMSB, VMSB-I, VMSB-2, VMSB-3) produced at the output terminals 306 of the plurality of heterojunction-thyristor-based sampling devices are supplied to the input terminal 332 of the sampling device of circuit 256', which is activated during the summing period (which is defined by the duration of the summing clock pulse in the timing signal B as shown in FIG. 5B(iii)) to thereby effectuate the summing operation, which produces the output analog electrical signal as described above.
  • the heterojunction-thyristor-based sampling device of circuit 256' includes an input capacitance that operates to store the sum of the voltage signals (V M SB, VM S B-I, V MS B- 2 , VMSB-3) produced at the output terminals 306 of the plurality of heterojunction-thyristor-based sampling devices and supplied to the input terminal 332 of the sampling device of circuit 256' for output during the subsequent summing period.
  • such conversion operations are repeated for another digital word that is subsequently encoded by the input digital optical signals supplied to the converter 251' as described above.
  • V R EF maximum voltage level
  • the injector terminal of the device is operably coupled to N-type QW channel(s) realized in the N-type modulation doped QW(s) structure of the device.
  • the bias current source draws charge from the n-type QW channel(s) to the positive supply voltage potential V D -
  • the injector terminal of the device may be operably coupled to the p-type QW channel(s) realized in the P-type modulation doped QW(s) structure of the device. In such a configuration, the bias current source draws charge from the p-type QW channel(s) to ground potential.
  • 5B(iii) is shown as a downward running electrical clock pulse. Such a pulse is suitable to activate a heterojunction-based sample and hold circuit as described above with respect to FIG. 5C.
  • the summing clock pulse of FIG. 4B(iii) can be an upward running electtical clock pulse. Such a pulse is suitable to activate a heterojunction-thyristor-based sample and hold circuit as described above with respect to FIG. 5D.
  • FIGS. 4C - 4E and 5C - 5E as described above may be realized with a material system based on III-V materials (such as a GaAs/AlxGa ⁇ x As).
  • FIGS. 3 A through 3F illustrate an exemplary structures utilizing group III-V materials for realizing the heterojunction-thyristor-based sampling device in accordance with the present invention.
  • strained silicon heterostructures employing silicon-germanium (SiGe) layers may be used to realize the heterojunction-thyristor-based sampling devices described herein. Using the structure described above with respect to FIGS.
  • a heterojunction- thyristor-based sampling device can be realized as shown in FIG. 5F.
  • This device is similar to the heterojunction thyristor device of FIG. 3C, but includes additional mesas 294, 295 (preferably formed by etching down near the bottom of layer 159 as shown) into which is implanted P+ ion implants 296, 297 that form self-aligned channel contacts to the p-type QW inversion channel(s).
  • p-channel injector terminals 38C and 38D are formed via deposition of p-type Au alloy metal layers 298, 299 on the P+ ion implants 296, 297 to form ohmic contacts thereto.
  • a heterojunction-thyristor-based sampling device is used as the basis for a photonic digital-to-analog converter that converts a digital word encoded by a serial digital bit stream in optical form to an output analog electtical signal conesponding to the digital word.
  • the serial digital bit stream is an optical signal that sequentially encodes a plurality of bits of information which are logically arranged from a most-significant-bit (MSB) to a least-significant-bit (LSB) as shown in FIG. 6B(i). These bits form a digital word.
  • the serial digital bit stream sequentially encodes four (4) bits of infonnation logically ananged from a most-significant-bit (MSB) to a least-significant-bit (MSB- ).
  • a first heterojunction thyristor device 302 is formed in a resonant cavity on a substrate as shown in FIG. 6C.
  • the first heterojunction thyristor device is configured as an optically-controlled sampling device (e.g., optically-controlled switch) in a manner similar to the device described above with respect to FIGS. 5C, 5D, and 5E. More specifically, as shown in FIG. 6C, a first p-channel injector tenninal 304 (the electtical input tenninal) and a second p-channel injector terminal 306 (the electrical output terminal) are operably coupled to opposite ends of the p-channel QW(s) of the device 302. A bias current source is coupled to the n-channel injector terminal(s) 308 and draws charge from the n-type QW channel(s) to the positive supply voltage potential No.
  • optically-controlled sampling device e.g., optically-controlled switch
  • the anode terminal 310 is forward biased (e.g. biased positively) with respect to the cathode terminal 312. Yet, this configuration differs from that in FIGS. 5C and 5D, and 5E, in that a clock generator 314 generates an electtical clock signal that is supplied to the n-channel injector terminal(s) 308 for injection into the n-type QW channel(s) of device 302.
  • the electrical clock signal includes downward running electtical clock pulses that define active sampling periods whose duration overlaps the bits of information encoded in the serial digital bit stream as shown in FIG. 6B(ii).
  • the serial digital bit stream is supplied to the resonant cavity of device 302 for resonant abso ⁇ tion by the device 302.
  • a voltage reference 316 is operably coupled to the electrical input terminal 304.
  • the voltage reference 316 and the heterojunction thyristor-based sampling device 302 cooperate to sequentially generate at the electrical output terminal 306 a voltage signal representing the contribution of each bit of the digital word in accordance with the serial digital bit stream as described below in more detail.
  • a summing circuit 318 which is operably coupled to the electrical output terminal 306, sequentially sums contribution of the voltage signal produced at the output terminal 306 over the sequence of bits in the serial digital bit stream to produce an output analog electrical signal corresponding to the digital word.
  • the length and width of the device 302 is sized such that it operates during a given sampling period defined by the electrical sampling clock as follows.
  • channel current produced by the combination of i) injection of electtical energy supplied by the electrical clock pulse and ii) abso ⁇ tion of optical energy supplied by the serial digital bit stream exceeds the bias current I B IA S to produce the critical switching charge QC R in the N-type modulation doped QW structure of device 302.
  • This causes the heterojunction thyristor device 302 to switch to its conducting/ON state where the current I through the device is substantially greater than zero but below the threshold for lasing I I .
  • the bias current I BI A S exceeds the channel current produced by the electtical clock pulse alone and thus draws on the injector terminal 308 to drain charge from the N-type modulation doped QW structure of device 302, which causes the channel charge to fall below the holding charge Q H .
  • the bias current I BIAS exceeds the channel current produced by the combination of injection of electrical energy supplied by the electrical clock pulse and abso ⁇ tion of optical energy supplied by the serial digital bit stream and thus draws on the injector terminal 308 to drain charge from the N-type modulation doped QW structure of device 302, which causes the channel charge to remain below the holding charge Q H .
  • This causes the device to remain in its non-conducting/OFF state where the current I through the device is substantially zero.
  • the electtical input terminal 304 (and the voltage reference 316 coupled thereto) is electrically isolated from the electrical output terminal 306.
  • the electrical input terminal 304 (and the voltage reference 316 coupled thereto) is electrically coupled to the electrical output terminal 306 (and there is a minimal potential voltage difference between the input terminal 304 and the output terminal 306).
  • the device 302 operates as a sampling device (e.g., switch) that is selectively activated and deactivated by binary logic level of the optical bits encoded in the serial digital bit stream, and produces at the output terminal 306 a voltage signal that representing contribution of each optical bit of the digital word.
  • the summing circuit 318 sequentially sums the voltage signal produced at the output terminal 306 over the sequence of bits in the serial digital bit stream to produce an output analog electrical signal corresponding to the digital word.
  • the summing circuitry 206 includes an adder node 320, a sample and hold circuit 322, and a feedback amplifier 324 coupled between the sample and hold circuit 322 and the adder node 320.
  • the adder node has a first input port 326, a second input port 328, and an output port 330.
  • the sample and hold circuit 322 has an input 332 and an output 334, and is activated by the electtical clock pulse.
  • the first input port 326 of the adder node 320 is operably coupled to said electrical output terminal 306 of the heterojunction thyristor device 302
  • the output port 330 of the adder node 320 is operably coupled to the input 332 of the sample and hold circuit 322
  • the feedback amplifier 324 is operably coupled between the output node 334 of the sample and hold circuit 322 and the second input port 328 of the adder node 320.
  • the analog value corresponding to the four (N) bit digital word is produced at output 334 of the sample and hold circuit 322.
  • the voltage reference 316 supplies a voltage level corresponding to maximum voltage level (V REF ) of the analog electrical signal divided by 2 fN"1) , where N is the number of bits in the digital word.
  • the feedback amplifier 324 amplifies output 334 of the sample and hold circuit by a factor of 2.
  • the sample and hold circuit 322 is preferably realized with an electrically-controlled heterojunction-thyristor-based sampling device as described above with respect to FIGS. 4C and 4D.
  • the configuration of the device 302 as described above with respect to FIG. 6A through 6C can be modified such that the first and second n-channel injector terminals are used as electtical input and output tenninals, and the electrical clock signal injects upward running clock pulses into the p-type QW channel(s) in structure 20.
  • the bias current draws charge from the p-type QW channel(s) to ground potential as shown.
  • the combination of injection of electtical energy supplied by the electtical clock pulse and abso ⁇ tion of optical energy supplied by the serial digital bit stream into the P-type modulation doped QW structure 20 of the device selectively produces channel charge above the critical switching charge or below the holding charge such that device operates in the conducting/ON state and non-conducting/OFF state, respectively.
  • FIG. 7A A second exemplary embodiment of the photonic digital-to analog converter 301 is shown in FIG. 7A.
  • the serial digital bit stream is an optical signal that sequentially encodes a plurality of bits of information which are logically arranged from a most-significant-bit (MSB) to a least- significant-bit (LSB) as shown in FIG. 7B(i). These bits form a digital word.
  • the serial digital bit stream sequentially encodes four (4) bits of information logically arranged from a most-significant-bit (MSB) to a least-significant-bit (MSB- 3 ).
  • a first heterojunction thyristor device 302 is formed in a resonant cavity on a substrate as shown in FIG. 7C.
  • the first heterojunction thyristor device is configured as an optically-controlled sampling device (e.g., optically-controlled switch) in a manner similar to the device described above with respect to FIGS. 5C, 5D, and 5E. More specifically, as shown in FIG. 7C, a first p- channel injector tenninal 304 (the electtical input terminal) and a second p-channel injector terminal 306 (the electrical output terminal) are operably coupled to opposite ends of the p-channel QW(s) of the device 302.
  • a bias current source is coupled to the n-channel injector terminal(s) 308 and draws charge from the n-type QW channel(s) to the positive supply voltage potential No.
  • the anode terminal 310 is forward biased (e.g. biased positively) with respect to the cathode terminal 312.
  • an optical clock signal that is supplied to the device for resonant abso ⁇ tion therein.
  • the optical clock signal includes optical clock pulses that define active sampling periods whose duration overlaps the bits of information encoded in the serial digital bit stream as shown in FIG. 7B(ii).
  • this configuration differs from that in FIGS. 5C, 5D, and 5E, in that the serial digital bit stream is supplied to the resonant cavity of device 302 for resonant abso ⁇ tion therein.
  • a voltage reference 316 is operably coupled to the electrical input terminal 304. The voltage reference 316 and the heterojunction thyristor-based sampling device
  • a summing circuit 318 which is operably coupled to the electrical output terminal 306, sequentially sums the voltage signal produced at the output terminal
  • the length and width of device 302 is sized such that it operates during a given sampling period defined by the optical clock as follows.
  • the light level of the serial digital bit stream corresponds to the ON logic level
  • channel current produced by abso ⁇ tion of optical energy supplied by the serial digital bit stteam and the optical clock exceeds the bias current I BIAS to produce the critical switching charge Q CR in the N-type modulation doped QW structure of device 302.
  • the heterojunction thyristor device 302 This causes the heterojunction thyristor device 302 to switch to its conducting/ON state where the current I through the device is substantially greater than zero but below the threshold for lasing I I -
  • the bias current I BIAS exceeds the channel current produced by abso ⁇ tion of the optical clock alone and thus draws on the injector terminal 308 to drain charge from the N-type modulation doped QW structure of device 302, which causes the channel charge to fall below the holding charge Q H .
  • the bias current I BI A S exceeds the channel current produced by abso ⁇ tion of optical energy supplied by the serial digital bit stream and the optical clock and thus draws on the injector terminal 308 to drain charge from the N-type modulation doped QW structure of device 302, which causes the channel charge to remain below the holding charge QH- This causes the device to remain in its non-conducting/OFF state where the current I through the device is substantially zero.
  • the electrical input terminal 304 (and the voltage reference 316 coupled thereto) is electtically isolated from the electtical output terminal 306.
  • the device 302 when the device 302 is operating in the conducting/ON state, the electtical input terminal 304 (and the voltage reference 316 coupled thereto) is electrically coupled to the electrical output terminal 306 (and there is a minimal potential voltage difference between the input terminal 304 and the output terminal 306).
  • the device 302 operates as a sampling device (e.g., switch) that is selectively activated and deactivated by the binary logic level of the optical bits encoded in the serial digital bit stream, and produces at the output terminal 306 a voltage signal that represents the contribution of each optical bit of the digital word.
  • the summing circuit 318 sequentially sums the voltage signal produced at the output terminal 306 over the sequence of bits in the serial digital bit stteam to produce an output analog electrical signal corresponding to the digital word.
  • the summing circuitry 206 includes an adder node 320, a sample and hold circuit 322, and a feedback amplifier 324 coupled between the sample and hold circuit 322 and the adder node 320.
  • the adder node has a first input port 326, a second input port 328, and an output port 330.
  • the sample and hold circuit 322 has an input 332 and an output 334, and is activated by a clock pulse (which may be optical or electtical in form).
  • the first input port 326 of the adder node 320 is operably coupled to the electtical output terminal 306 of the heterojunction thyristor device 302
  • the output port 330 of the adder node 320 is operably coupled to the input 332 of the sample and hold circuit 322
  • the feedback amplifier 324 is operably coupled between the output node 334 of the sample and hold circuit 322 and the second input port 328 of the adder node 320.
  • the analog value corresponding to the four (N) bit digital word is produced at output 334 of the sample and hold circuit 322.
  • the voltage reference 316 supplies a voltage level corresponding to maximum voltage level (V REF ) of the analog electtical signal divided by 2 (N"1) , where N is the number of bits in the digital word.
  • the feedback amplifier 324 amplifies the output 334 of the sample and hold circuitry by a factor of 2.
  • the sample and hold circuit 322 is preferably realized with an optically-controlled heterojunction-thyristor-based sampling device as described above with respect to FIGS. 5C, 5D, and 5E. In an alternate embodiment as shown in FIG.
  • the configuration of the device 302 as described above with respect to FIG. 7A through 7C can be modified such that the first and second n-channel injector terminals are used as electrical input and output terminals, and the bias current draws charge from the p-type QW channel(s) to ground potential as shown.
  • optical energy supplied by the serial digital bit stteam and by the optical clock and absorbed into the P-type modulation doped QW structure 20 of the device selectively produces channel charge above the critical switching charge (or below the holding charge) such that device operates in the conducting/ON state (or the non- conducting/OFF state).
  • the devices 302, 322, and 324 of FIG. 6A and 7A are preferably formed on a common substrate from the same multilayer structure, such as the multilayer structures described above with respect to FIGS. 2A and 3 A.
  • a plurality of ttansistors such as n-type heterojunction bipolar transistors, p-type heterojunction bipolar ttansistors, n-channel heterojunction FET ttansistors, and/or p-channel heterojunction FET transistors
  • ttansistors such as n-type heterojunction bipolar transistors, p-type heterojunction bipolar ttansistors, n-channel heterojunction FET ttansistors, and/or p-channel heterojunction FET transistors
  • FIG. 8A A pictorial illustration of an exemplary p-type quantum-well-base bipolar ttansistor 802 formed from the multilayer structure of FIG. 2A is shown in FIG. 8A.
  • the p- type quantum-well-base bipolar transistor 802 includes a base electrode (B) electrically coupled to the p-type QW structure 20 (preferably via spaced apart P-type implants as described above for the heterojunction thyristor device).
  • An emitter electtode (E) is contacted (preferably via etching down to the ohmic contact layer as described above for the heterojunction thyristor device) to the n-type ohmic contact layer 14.
  • a collector electrode (C) is electtically coupled to an n-type implant, which is electrically coupled to the n-type QW structure 24.
  • a plurality of such p-type quantum-well-base bipolar ttansistor devices 802 can be configured to form a differential amplifier stage with a gain factor of 2 as shown in FIG. 8B, which is suitable for use as the amplifier circuit 324 in the illustrative embodiment of FIG. 6A and FIG. 7A.
  • the differential amplifier stage of FIG. 8B includes an emitter-coupled pair of p-type quantum- well-base bipolar transistors whose emitter terminals are coupled to ground through a bias current source as shown.
  • the input nodes (labeled V A and V B ) are coupled to the base electrodes of this pair of p-type quantum-well-base bipolar ttansistor as shown.
  • Such a configuration provides a gam factor of 2 to produce a voltage signal at the - VB)
  • the heterojunction device configured for digital- optical- to-digital-electrical conversion as described above with respect to FIGS. 2 A through 2D4 can be used to realize an optical-to-digital converter as shown m FIGS. 9 A through and 9D(n).
  • the heterojunction thyristor device 901 is supplied a serial optical bit stream as shown m FIG. 9B( ⁇ )
  • the heterojunction thyristor device 902 converts the serial optical bit stteam (input digital optical signal) supplied thereto to a corresponding digital electrical bit stream (output digital electtical signal) as described above with respect to FIGS. 2A, 2B1, 2C, and 2D1.
  • a se ⁇ al-to-parallel converter 904 may be provided to convert the serial digital bit stteam into an n-bit digital word as shown.
  • the heterojunction thyristor device 901 is supplied with a serial optical bit stteam as shown m FIG 9D( ⁇ )
  • the heterojunction thyristor device 902 converts the serial optical bit stream (input digital optical signal) supplied thereto to a corresponding digital electrical bit stream (output digital electrical signal) as described above with respect to FIGS. 2 A, 2B2, 2C and 2D2.
  • a se ⁇ al-to-parallel converter 904 may be provided to convert the serial digital bit stream into an n-bit digital word as shown.
  • the heterojunction device configured for digital- optical-to-digital-electncal conversion as described above with respect to FIGS. 2A through 2D2 can be used to realize a receive module 122 in a parallel optical data link as shown in FIG. 9E.
  • a parallel optical data link consists of a transmit module 120 coupled to a receive module 122 with a multi-fiber connector 124 as shown in FIG. IB.
  • the transmit module typically employs an array
  • the receive module 122 includes an array of digital-optical-to-digital-electtical converters 901 as described above with respect to FIGS. 9 A through 9D(iii). These devices are adapted to receive the synchronous optical bit stteams and convert them into electrical form to produce a plurality of electtical bit streams corresponding thereto.
  • the plurality of electtical bit stteams are provided to one or more integrated circuits 134 that map parallel bits encoded in the plurality of electtical bit stteams into a predetermined data format (such as a SONET frame).
  • many of the components of the optoelecttonic circuits that perform signal conversion and signal sampling as described herein are capable of being formed from the same multilayer structure, which enables monolithic integration and significant cost improvements.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)

Abstract

L'invention concerne divers circuits optoélectroniques et convertisseurs numérique/analogique photoniques obtenus à l'aide d'un ou de plusieurs dispositifs de thyristors d'hétérojonction et de circuits de support. Lesdits circuits optoélectroniques comprennent des dispositifs d'échantillonnage/commutation commandés optiquement et électriquement ainsi que des récepteurs de données optiques. Lesdits convertisseurs numérique/analogique photoniques comprennent des convertisseurs qui traitent une pluralité de signaux optiques numériques qui codent de manière synchrone des informations numériques ainsi que des convertisseurs qui traitent un signal optique numérique qui code en série des informations numériques.
PCT/US2003/033813 2002-10-25 2003-10-23 Circuits optoelectroniques faisant appel a un ou plusieurs dispositifs de thyristors WO2004038812A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003284911A AU2003284911A1 (en) 2002-10-25 2003-10-23 Optoelectronic circuits employing one or more heterojunction thyristor devices

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US10/280,892 US6954473B2 (en) 2002-10-25 2002-10-25 Optoelectronic device employing at least one semiconductor heterojunction thyristor for producing variable electrical/optical delay
US10/280,892 2002-10-25
US10/323,413 2002-12-19
US10/323,388 US6873273B2 (en) 2002-10-25 2002-12-19 Photonic serial digital-to-analog converter employing a heterojunction thyristor device
US10/323,413 US6995407B2 (en) 2002-10-25 2002-12-19 Photonic digital-to-analog converter employing a plurality of heterojunction thyristor devices
US10/323,388 2002-12-19
US10/323,389 2002-12-19
US10/323,390 2002-12-19
US10/323,390 US6853014B2 (en) 2002-10-25 2002-12-19 Optoelectronic circuit employing a heterojunction thyristor device that performs high speed sampling
US10/323,389 US7332752B2 (en) 2002-10-25 2002-12-19 Optoelectronic circuit employing a heterojunction thyristor device to convert a digital optical signal to a digital electrical signal

Publications (1)

Publication Number Publication Date
WO2004038812A1 true WO2004038812A1 (fr) 2004-05-06

Family

ID=32180774

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/033813 WO2004038812A1 (fr) 2002-10-25 2003-10-23 Circuits optoelectroniques faisant appel a un ou plusieurs dispositifs de thyristors

Country Status (2)

Country Link
AU (1) AU2003284911A1 (fr)
WO (1) WO2004038812A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064697B2 (en) 2003-01-29 2006-06-20 The University Of Connecticut Photonic sigma delta analog-to-digital conversation employing dual heterojunction thyristors
EP1676298A2 (fr) * 2003-10-20 2006-07-05 University of Connecticut Reseau d'imagerie utilisant des elements de pixel a base de thyristor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4806997A (en) * 1985-06-14 1989-02-21 AT&T Laboratories American Telephone and Telegraph Company Double heterostructure optoelectronic switch
US5204871A (en) * 1990-03-29 1993-04-20 Larkins Eric C Bistable optical laser based on a heterostructure pnpn thyristor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4806997A (en) * 1985-06-14 1989-02-21 AT&T Laboratories American Telephone and Telegraph Company Double heterostructure optoelectronic switch
US5204871A (en) * 1990-03-29 1993-04-20 Larkins Eric C Bistable optical laser based on a heterostructure pnpn thyristor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064697B2 (en) 2003-01-29 2006-06-20 The University Of Connecticut Photonic sigma delta analog-to-digital conversation employing dual heterojunction thyristors
US7409120B2 (en) 2003-01-29 2008-08-05 The University Of Connecticut Integrated circuit for programmable optical delay
EP1676298A2 (fr) * 2003-10-20 2006-07-05 University of Connecticut Reseau d'imagerie utilisant des elements de pixel a base de thyristor
EP1676298A4 (fr) * 2003-10-20 2010-03-17 Univ Connecticut Reseau d'imagerie utilisant des elements de pixel a base de thyristor

Also Published As

Publication number Publication date
AU2003284911A8 (en) 2004-05-13
AU2003284911A1 (en) 2004-05-13

Similar Documents

Publication Publication Date Title
US7595516B2 (en) Optoelectronic circuit employing a heterojunction thyristor device to convert a digital optical signal to a digital electrical signal
US6853014B2 (en) Optoelectronic circuit employing a heterojunction thyristor device that performs high speed sampling
US6873273B2 (en) Photonic serial digital-to-analog converter employing a heterojunction thyristor device
US6995407B2 (en) Photonic digital-to-analog converter employing a plurality of heterojunction thyristor devices
US6954473B2 (en) Optoelectronic device employing at least one semiconductor heterojunction thyristor for producing variable electrical/optical delay
US6841795B2 (en) Semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation
US7012274B2 (en) Modulation doped thyristor and complementary transistors combination for a monolithic optoelectronic integrated circuit
US7556976B2 (en) Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation
US6849866B2 (en) High performance optoelectronic and electronic inversion channel quantum well devices suitable for monolithic integration
US6977954B2 (en) Semiconductor laser array device employing modulation doped quantum well structures
JP2004534380A5 (fr)
US6974969B2 (en) P-type quantum-well-base bipolar transistor device employing interdigitated base and emitter formed with a capping layer
US6841806B1 (en) Heterojunction thyristor-based amplifier
US7776753B2 (en) Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation
US7385230B1 (en) Modulation doped thyristor and complementary transistor combination for a monolithic optoelectronic integrated circuit
US7015120B2 (en) Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation
US7333733B2 (en) Optoelectronic clock generator producing high frequency optoelectronic pulse trains with variable frequency and variable duty cycle and low jitter
WO2004038812A1 (fr) Circuits optoelectroniques faisant appel a un ou plusieurs dispositifs de thyristors
Zhou et al. Monolithic optoelectronic switch based on the integration of a GaAs/AlGaAs heterojunction bipolar transistor and a GaAs vertical-cavity surface-emitting laser
WO2004038764A2 (fr) Dispositifs a semi-conducteurs utilisant au moins une structure a puits quantique a dopage module et une ou plusieurs couches d'arret d'attaque pour la formation precise de contacts et procede de fabrication de ces dispositifs

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP