WO2004036620A2 - Method for generating oxide layers on semiconductor substrates - Google Patents
Method for generating oxide layers on semiconductor substrates Download PDFInfo
- Publication number
- WO2004036620A2 WO2004036620A2 PCT/EP2003/011234 EP0311234W WO2004036620A2 WO 2004036620 A2 WO2004036620 A2 WO 2004036620A2 EP 0311234 W EP0311234 W EP 0311234W WO 2004036620 A2 WO2004036620 A2 WO 2004036620A2
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- WO
- WIPO (PCT)
- Prior art keywords
- solution
- ozone
- temperature
- oxide
- use temperature
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
- H01L2224/85375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01072—Hafnium [Hf]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the invention relates to a method for generating oxide layers on metal surfaces on semiconductor substrates.
- Metal surfaces can be selected from the group aluminum, copper, silicon and an alloy thereof.
- Oxide layers on metals might be generated on bonding pads, e.g. comprising aluminum (Al, AISi, AlSiCu). Such bonding pads are small areas on top of a semiconductor chip. These bonding pads are used in the production of integrated circuits for connection to wires (e.g. fine gold wires) which in turn are connected to the external circuit, other electronic or electrical components or are connected to a so called lead frame.
- wires e.g. fine gold wires
- Miyakawa [Improvement of Moisture Resistance by the New Surface Treatment of Aluminum Bonding Pads in LSI, T. Miyakawa et al., ISTFA '93, The 19 th International Symposium for Testing & Failure Analysis] proposed a method for forming a fine aluminum oxide film on aluminum bonding pads, in order to prevent corrosion due to moisture penetration. Miyakawa teaches immersion of a semiconductor wafer in an ozone solution in the last step of the wafer production process, to form an aluminum oxide film over the bonding pads.
- a method for forming a protective oxide film is proposed.
- the oxide layer is formed on bonding pads of a semiconductor chip, while the chip is in the form of wafer.
- the wafer is exposed to ozone and ultraviolet (UV) radiation, so that excited oxygen, which is generated from the ozone by UV radiation, oxidizes metal atoms, for example aluminum atom of the aluminum bonding pads, to form a fine oxide film over the bonding pads.
- UV radiation ultraviolet
- the method for generating oxide layers on metal surfaces on semiconductor substrates comprises:
- the liquid, in which ozone is dissolved is preferably an aqueous solution. Pure water is possible and deionized water is typically used. Depending on the selected temperature a desired oxide thickness can be achieved.
- An additional advantage of the method according to the invention is that the solution will remove eventually organic and/or halogen contamination.
- the point-of-use temperature is higher than 30°C. This leads to a good oxide layer giving sufficient protection to the metal layer underneath.
- the forming of the solution by dissolving ozone in a liquid is carried out. at a dissolving temperature, which is lower than said point-of-use temperature.
- a dissolving temperature which is lower than said point-of-use temperature.
- Yet another embodiment of the method includes a step wherein the metal surface is pretreated with an oxide-removing agent before it is treated with the solution.
- the pretreatment with oxide-removing agent is useful if the metal surface has been exposed to ambient atmosphere for a longer time and the metal (e.g. Al) tends to form native oxide together with oxygen coming from air.
- the metal e.g. Al
- the point-of-use temperature is achieved by heating the solution after dissolving the ozone or by applying heat energy to the backside of semiconductor substrate (e.g. through a heated fluid). Further details of the invention follow from the example below.
- a semiconductor wafer having aluminum bonding pads exposed is placed on a spin chuck as described in EP1170782A2.
- the wafer is pretreated with DHF at ambient temperature for about 5 seconds. While rotating the spin chuck and the wafer thereon the wafer is heated by supplying deionized water onto the backside of the wafer.
- the backside shall be defined as the side of the wafer not having bonding pads exposed to be treated.
- the selected temperature is 50°C.
- the spin speed is 50 to 3000 rpm, preferably 200 to 1000 rpm.
- Deionized water (ambient temperature) is fed into an ozone module where ozone is dissolved in the water through a membrane to achieve an aqueous solution with a concentration of about 50ppm ozone.
- the ozone is being generated from oxygen treated with electrical discharge. .
- the solution is heated to a temperature of 50°C in line immediately before dispensing the solution onto the wafer's front surface.
- the wafer is treated for 4,5 minutes. This results in an aluminum oxide layer of a thickness of 20 nm. It has been seen that a treatment time of even five minutes does not result in a significantly higher thickness. - - • -
- Fig. 1 shows a diagram of the aluminum oxide thickness d as a function of the treating time t at two different treating temperatures T (23°C and 50°C). This shows for instance that at 50°C with a treatment of only 60 seconds an oxide thickness of 12 nm can be achieved.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Oxygen, Ozone, And Oxides In General (AREA)
- Formation Of Insulating Films (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003276093A AU2003276093A1 (en) | 2002-10-14 | 2003-10-10 | Method for generating oxide layers on semiconductor substrates |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT15472002 | 2002-10-14 | ||
ATA1547/2002 | 2002-10-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004036620A2 true WO2004036620A2 (en) | 2004-04-29 |
WO2004036620A3 WO2004036620A3 (en) | 2007-12-21 |
Family
ID=32097255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2003/011234 WO2004036620A2 (en) | 2002-10-14 | 2003-10-10 | Method for generating oxide layers on semiconductor substrates |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU2003276093A1 (en) |
WO (1) | WO2004036620A2 (en) |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0701275A2 (en) * | 1994-08-26 | 1996-03-13 | MEMC Electronic Materials, Inc. | Pre-thermal treatment cleaning process |
US5565378A (en) * | 1992-02-17 | 1996-10-15 | Mitsubishi Denki Kabushiki Kaisha | Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution |
WO1999059193A1 (en) * | 1998-05-12 | 1999-11-18 | Semitool, Inc. | Process for etching thin-film layers of a workpiece used to form microelectronic circuits or components |
US6017827A (en) * | 1998-05-04 | 2000-01-25 | Micron Technology, Inc. | System and method for mixing a gas into a solvent used in semiconductor processing |
US6240933B1 (en) * | 1997-05-09 | 2001-06-05 | Semitool, Inc. | Methods for cleaning semiconductor surfaces |
US20020020436A1 (en) * | 1997-05-09 | 2002-02-21 | Bergman Eric J. | Process and apparatus for treating a workpiece with steam and ozone |
WO2003090792A2 (en) * | 2002-04-26 | 2003-11-06 | Phifer Smith Corporation | Method and apparatus for treating a substrate with an ozone-solvent solution iii |
US20040067639A1 (en) * | 2002-10-05 | 2004-04-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming low thermal budget sacrificial oxides |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04114431A (en) * | 1990-09-04 | 1992-04-15 | Seiko Epson Corp | Oxidization process |
JPH11111908A (en) * | 1997-10-03 | 1999-04-23 | Hitachi Cable Ltd | Lead-forming material and resin adhesion improved surface treatment |
-
2003
- 2003-10-10 WO PCT/EP2003/011234 patent/WO2004036620A2/en not_active Application Discontinuation
- 2003-10-10 AU AU2003276093A patent/AU2003276093A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5565378A (en) * | 1992-02-17 | 1996-10-15 | Mitsubishi Denki Kabushiki Kaisha | Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution |
EP0701275A2 (en) * | 1994-08-26 | 1996-03-13 | MEMC Electronic Materials, Inc. | Pre-thermal treatment cleaning process |
US6240933B1 (en) * | 1997-05-09 | 2001-06-05 | Semitool, Inc. | Methods for cleaning semiconductor surfaces |
US20020020436A1 (en) * | 1997-05-09 | 2002-02-21 | Bergman Eric J. | Process and apparatus for treating a workpiece with steam and ozone |
US6017827A (en) * | 1998-05-04 | 2000-01-25 | Micron Technology, Inc. | System and method for mixing a gas into a solvent used in semiconductor processing |
WO1999059193A1 (en) * | 1998-05-12 | 1999-11-18 | Semitool, Inc. | Process for etching thin-film layers of a workpiece used to form microelectronic circuits or components |
WO2003090792A2 (en) * | 2002-04-26 | 2003-11-06 | Phifer Smith Corporation | Method and apparatus for treating a substrate with an ozone-solvent solution iii |
US20040067639A1 (en) * | 2002-10-05 | 2004-04-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming low thermal budget sacrificial oxides |
Non-Patent Citations (3)
Title |
---|
DE SMEDT F ET AL.: "A detailed study on the growth of thin oxide layers on silicon using ozonated solutions" JOURNAL OF ELECTROCHEMICAL SOCIETY, vol. 147, no. 3, March 2000 (2000-03), pages 1124-1129, XP002280392 * |
PATENT ABSTRACTS OF JAPAN vol. 016, no. 360 (E-1243), 4 August 1992 (1992-08-04) -& JP 04 114431 A (SEIKO EPSON CORP), 15 April 1992 (1992-04-15) * |
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 09, 30 July 1999 (1999-07-30) -& JP 11 111908 A (HITACHI CABLE LTD), 23 April 1999 (1999-04-23) * |
Also Published As
Publication number | Publication date |
---|---|
AU2003276093A1 (en) | 2004-05-04 |
WO2004036620A3 (en) | 2007-12-21 |
AU2003276093A8 (en) | 2004-05-04 |
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