WO2004034578A1

WO2004034578A1 - Variable delay line

Info

Publication number: WO2004034578A1
Application number: PCT/JP2003/013060
Authority: WO
Inventors: Itsuaki Katsumata; Tokumi Kobayashi; Masahiko Yokoyama
Original assignee: Soshin Electric Co., Ltd.
Priority date: 2002-10-10
Filing date: 2003-10-10
Publication date: 2004-04-22
Also published as: US7336143B2; CN1703829A; US20060262475A1; KR100799953B1; CN100508379C; KR20050075353A

Abstract

First and second reactance parts (18, 20) are connected with the first and second output terminals (14, 16) of a hybrid coupler (12). The first and second reactance parts (18, 20) have a substantially identical reactance X.

Description

Variable delay line technology

The present invention relates to a variable delay line having a variable reactance element. Light

Background art

Field 1

In recent years, variable delay lines used in commercial wireless communication devices

This is a bandpass filter in which the transmission / reception frequency band included in is used as a signal pass band. The variable delay line changes an absolute value (hereinafter, referred to as an absolute delay time) of a delay time of the variable delay line by changing a coupling capacitance of the bandpass filter to change the pass band. It has the feature of.

As shown in Fig. 15, the conventional variable delay line 100 has a capacitor 106, 108 and a variable capacitor 110 between the input terminal 102 and the output terminal 104. Are connected in series, and the first and second resonance circuits 112, 114 are connected between one end and the other end of the variable capacitance capacitor 110 and the ground, respectively. (See Japanese Patent Application Laid-Open No. 2001-119206).

When a predetermined input signal is supplied from the input terminal 102 of the variable delay line 100, an output signal having a predetermined absolute delay time shown in FIG. 16 is output from the output terminal 104. You. In this case, when the coupling capacitance C of the variable capacitor 110 shown in FIG. 17 changes, the absolute delay time changes as shown in FIG. For example, changing the coupling capacitance C from C1 to C2 or C3 (C1> C2> C3) increases the absolute delay time. If the adjustment range of the coupling capacitance C is wide, the range of the variation of the absolute delay time in the variable delay line 100 (hereinafter, referred to as variable delay time) is also widened.

On the other hand, when the coupling capacitance C is reduced, the passband bandwidth of the variable delay line 100 becomes narrower, and the transmission characteristic of the variable delay line 100 shown in FIG. 17 is attenuated. The indicated mismatch attenuation increases. In this case, when the coupling capacitance C changes, the capacitor 106 on the input terminal 102 and the first resonance circuit 112 shown in FIG. 15 and the capacitor 108 on the output terminal 104 shown in FIG. The balance with the second resonance circuit 114 is lost, and the value of the input impedance and the value of the output impedance in the variable delay line 100 fluctuate. This makes it difficult to obtain impedance matching in the variable delay line 100. Therefore, the mismatch attenuation shown in Fig. 18 increases. In addition, the transmission characteristics shown in FIG. 17 are greatly attenuated, the transmission loss in the variable delay line 100 increases, and the deviation of the absolute delay time shown in FIG. 16 increases.

In this state, even if the variable delay line 100 shown in FIG. 15 and other electronic components are connected via the input terminal 102 and the output terminal 104, the variable delay line 100 It is difficult to match the impedance with the other electronic components. Therefore, the transmission loss of the variable delay line 100 and the wireless communication device further increases. Further, since the above-mentioned deviation is large, the pass band of the variable delay line 100 is reduced, and the distortion of the output signal output from the output terminal 104 becomes remarkable.

For example, when a variable delay line 100 is mounted on an actual wireless communication device, a variable delay time of at least about 0.5 ns is required. However, as shown in FIGS. 16 to 18, the variable delay time of about 0.4 ns causes a decrease in the transmission characteristics and an increase in the mismatch attenuation, so that the variable delay line 1 having the desired characteristics can be obtained. It is difficult to achieve 0. Disclosure of the invention

The present invention suppresses fluctuations in input impedance and output impedance by mounting a hybrid coverl and a variable reactance element on a variable delay line, and connecting the variable reactance elements to two output terminals of the eight hybrid coverr, respectively. In addition, the variable delay line of the present invention has an object to provide a variable delay line capable of reducing the deviation of the absolute delay time, increasing the variable delay time and widening the pass band. The input terminal to which the signal is supplied has a phase difference of 9 First and second output terminals for outputting first and second output signals at 0 °, and isolation for outputting a reflected signal based on the first and second output signals as a third output signal And a first and second reactance sections connected to the first and second output terminals and having substantially the same reactance. Is characterized in that it comprises first and second variable reactance elements having substantially the same reactance.

In this case, one ends of the first and second reactance portions having substantially the same reactance as each other are connected to the first and second output terminals, and the other ends of the first and second reactance portions are connected to the ground. Connected and grounded.

When an input signal is supplied to the input terminal, a first output signal having the same phase as the input signal is output to the first output terminal. On the other hand, a second output signal having a phase difference of 90 ° with respect to the input signal is output to the second output terminal. Therefore, the phase difference between the first and second output signals is 90 °.

At this time, since the first and second reactance units are connected to the first and second output terminals, the first and second output signals allow the first and second output signals to be connected. The first and second reflected signals are generated at the output terminal. In addition, a reflection signal that is a composite signal of the first and second reflection signals is output to the isolation terminal. This reflected signal has a 180 ° phase difference with respect to the input signal. Since the portion between the isolation terminal and the input terminal functions as an isolation terminal, the reflected wave due to the reflected signal is attenuated while propagating from the isolation terminal to the input terminal. There is no output.

Thus, the hybrid coupler and the first and second reactance units can suppress the fluctuation of the input impedance and the output impedance of the variable delay line. Therefore, the deviation of the absolute delay time can be reduced, and a variable delay line having low transmission loss, a wide passband, and a third output signal with little distortion can be realized. Therefore, the reliability of the wireless communication device equipped with the variable delay line can be improved.

Further, the first and second variable resistors included in the first and second reactance units are provided. By changing the reactances of the reactance elements by the same amount, the reactances of the first and second reactance units can be changed by the same amount. Thereby, the reflected signal changes by a desired value, and the absolute delay time of the variable delay line changes by a predetermined amount. Therefore, by changing the reactance of the first and second variable reactance elements by a predetermined amount, a variable delay line having a desired absolute delay time and a variable delay time can be realized.

Further, the first and second reactance units include first and second capacitors having substantially the same capacitance, and first and second variable capacitances as the first and second variable reactance elements. It is desirable to form a series circuit of the element and the first and second resonance circuits.

In this case, by changing the capacitance of the first and second variable capacitance elements, the admittance of the first and second variable capacitance elements changes. Thereby, the reactance and admittance of the first and second reactance sections change, so that the absolute delay time and the variable delay time can be adjusted to desired values. Further, since the first and second resonance circuits each have a resonance frequency, a center frequency in a pass band of the variable delay line is determined by the resonance frequency. Therefore, with the configuration of the series circuit, it is possible to obtain a variable delay line having a desired pass band, an absolute delay time, and a variable delay time.

In the above-described circuit configuration of the variable delay line, the phase of the variable delay line changes by changing the absolute delay time. Further, in the circuit configuration, even if the resonance frequencies of the first and second resonance circuits are changed, the absolute delay time hardly changes if the bandwidth of the variable delay line is wide, but the variable delay line Only the phase of changes.

Therefore, in order to suppress the phase change in the variable delay line, a series circuit of the third and fourth capacitors and the third and fourth variable capacitance elements as variable reactance elements includes It is desirable that the two resonance circuits be connected in parallel. Thus, even if the absolute delay time of the variable delay line and the resonance frequency of the first and second resonance circuits change, the capacitances of the third and fourth variable capacitance elements can be adjusted. Thus, the change in the phase of the third output signal due to the change in the absolute delay time and the resonance frequency can be compensated. Therefore, the absolute delay time and the resonance frequency can be changed without changing the phase.

Further, it is preferable that the first and second resonance circuits are LC resonance circuits, resonance circuits based on distributed constant circuits, or dielectric resonators. Further, the first to fourth variable capacitance elements are desirably circuit elements capable of changing the capacitance, and such circuit elements include a varactor diode, a trimmer capacitor and the like.

Further, in the variable delay line described above, a plurality of ceramic layers are stacked to form an integrated structure of ceramics, and the integrated structure of ceramics is a ceramic layer on which the hybrid cover is formed; It may have a ceramic layer on which a second resonance circuit is formed, and at least a ceramic layer on which the first and second capacitors are formed. Accordingly, most of the circuit elements constituting the variable delay line are formed inside the ceramics integrated structure, so that a more miniaturized variable delay line can be realized. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a circuit diagram showing a variable delay line according to the present embodiment.

FIG. 2 is a circuit diagram showing first and second reactance units constituting the variable delay line of FIG.

FIG. 3 is a circuit diagram showing a variable delay line of the first specific example.

FIG. 4 is a diagram showing a simulation result of an absolute delay time in the variable delay line of FIG.

FIG. 5 is a diagram showing a simulation result of transmission characteristics in the variable delay line of FIG.

FIG. 6 is a diagram showing a simulation result of mismatch attenuation in the variable delay line of FIG.

FIG. 7 is a circuit diagram showing a variable delay line of the second specific example.

Fig. 8 shows the simulation result of the absolute delay time in the variable delay line of Fig. 7. FIG.

FIG. 9 is a diagram showing a simulation result of the phase in the variable delay line of FIG.

FIG. 10 is a circuit diagram showing a variable delay line of the third specific example.

FIG. 11 is a perspective view showing the variable delay line of FIG.

FIG. 12 is a perspective view showing the variable delay line of FIG. 10 without a case.

FIG. 13 is an exploded perspective view showing the variable delay line of FIG.

FIG. 14 is a cross-sectional view showing the variable delay line of FIG.

FIG. 15 is a circuit diagram showing a conventional variable delay line.

FIG. 16 is a diagram showing a simulation result of an absolute delay time in the variable delay line of FIG.

FIG. 17 is a diagram showing a simulation result of transmission characteristics in the variable delay line of FIG.

FIG. 18 is a diagram showing a simulation result of mismatch attenuation in the variable delay line of FIG. BEST MODE FOR CARRYING OUT THE INVENTION

As shown in FIG. 1, the variable delay line 10 of the present embodiment includes a hybrid cover 12 and first and second output terminals 14 and 16 connected to the hybrid force bra 12. And second reactance sections 18 and 20.

The hybrid power bracket 12 includes, in addition to the first and second output terminals 14 and 16, an input terminal 22 to which an input signal is supplied, and first and second output terminals 14 and 16. And an isolation terminal 24 that outputs a reflected signal based on the first and second output signals output from the variable delay line 10 as an output signal (third output signal) of the variable delay line 10. In this case, the first output terminal 14 is a 0 ° output terminal from which the first output signal in phase with the input signal supplied to the input terminal 22 is output, and the second output terminal 16 outputs a second output signal having a phase difference of 90 ° with respect to the input signal. 90 ° output terminal.

The first and second reactance sections 18 and 20 have substantially the same reactance X, and one end thereof is connected to the first and second output terminals 14 and 16 and the other end is grounded. Grounded. As shown in FIG. 2, inside the first and second reactance sections 18 and 20 are first and second variable capacitance elements 26 and 28 as variable reactance elements, and first and second variable capacitance elements 26 and 28. It is composed of a series circuit with the second resonance circuits 30 and 32. The first and second variable capacitance elements 26 and 28 only need to be able to change the reactance X by changing the coupling capacitance C. Such circuit elements include a paraductor diode. , Trimmer capacitors, etc. Also, the first and second resonance circuits 30 and 32 are desirably a resonance circuit composed of an LC resonance circuit and a distributed constant circuit or a dielectric resonator.

Next, the operation of the variable delay line 10 of the present embodiment will be described.

First, when an input signal is supplied to the input terminal 34 of the variable delay line 10 shown in FIG. 1, the input signal is supplied to the hybrid coupler 12 via the input terminal 22. At this time, the first and second output signals are output to the first and second output terminals 14 and 16. In this case, the phase difference between the first and second output signals is 90 °. Since the first and second output terminals 14 and 16 are grounded via the first and second reactance sections 18 and 20, the first and second output terminals 14 and 16 Generates the first and second reflected signals. Then, a reflection signal that is a composite signal of the first and second reflection signals is output to the isolation terminal 24, and the reflection signal is output as an output signal of the variable delay line 10, that is, a third output signal. Output to terminals 36. The reflected signal has a phase difference of 180 ° with respect to the input signal.

Since the portion between the isolation terminal 24 and the input terminal 22 functions as an isolator, the reflected wave of the reflected signal propagates from the isolation terminal 24 to the input terminal 22 but is attenuated on the way. It is not output to input terminal 22. That is, the reflected wave does not affect the input impedance and the output impedance of the variable delay line 10. Therefore, the input impedance of the variable delay line 10 is controlled by the hybrid force brass 12 and the first and second reactance sections 18 and 20. Source and output impedance fluctuations. Thereby, impedance matching in the variable delay line 10 can be easily performed. Further, by changing the coupling capacitance C of the first and second variable capacitance elements 26 and 28 of the first and second reactance sections 18 and 20 by the same amount, the first and second The reactance X of the reactance sections 18 and 20 can be changed by the same amount. This makes it possible to change the third output signal by a desired value. Therefore, the absolute delay time of the third output signal of the variable delay line 10 can be changed by a predetermined amount, and the variable delay time can be set to a desired value. Therefore, by changing the coupling capacitance C of the first and second variable capacitance elements 26 and 28 by a predetermined amount, the variable delay line 10 having the desired absolute delay time and variable delay time can be realized. Becomes possible.

Further, the first and second resonance circuits 30 and 32 each have a resonance frequency. The center frequency in the pass band of the variable delay line 10 is determined by the resonance frequency. That is, by setting the resonance frequency to a desired value, it becomes possible to obtain a variable delay line 10 having a desired pass band.

Although the configuration and operation of the variable delay line 10 of the present embodiment are as described above, the variable delay lines 10 A to 10 C of the first to third specific examples as the configuration examples will be described with reference to FIG. This will be described below with reference to FIGS.

The variable delay line 10A of the first specific example shown in FIG. 3 has substantially the same configuration as the variable delay line 10 of the present embodiment shown in FIGS. 1 and 2, but has the following points. different.

As shown in FIG. 3, the first and second reactance sections 18 and 20 are composed of first and second capacitors 38 and 40 and first and second variable capacitance elements 26 and 28, respectively. The first and second paramagnetic diodes 42, 44 replaced by the first and second λ Ζ 4 dielectrics replaced by the first and second resonant circuits 30, 32 This is a series circuit having resonators 46 and 48. .

In this case, one ends of the first and second capacitors 38 and 40 are connected to the first and second output terminals 14 and 16, and the other ends are the first and second Barak diode 42, 4 4 Sword terminal Kl, connected to 接続 2. In addition, the first and second roses The anode terminals Al and A2 of the collector diodes 42 and 44 are connected to the first and second λΖ4 dielectric resonators 46 and 48, respectively. Further, first and second voltage control terminals 50 and 52 are connected to the force source terminals Kl and Κ2 so that a DC voltage can be supplied.

In the variable delay line 10 # of the first specific example, the first and second voltage control terminals 50 and 52 are connected to the first and second varactor diodes 42 and 44 by a resistor or a resistor (not shown). When a DC voltage having substantially the same value is supplied through each of the varactor diodes, the coupling capacitance C of the first and second varactor diodes 42, 44 changes by the same amount corresponding to the DC voltage value. I do. Specifically, as the DC voltage increases, the coupling capacitance C of the first and second varactor diodes 42, 44 decreases.

When the coupling capacitance C changes from C = C1 to C = C2 or C = C3 (C1> C2> C3), the admittance in the first and second reactance sections 18, 20 changes. Thus, as shown in FIG. 4, the absolute delay time of the variable delay line 1OA increases. In this case, if the first and second varactor diodes 42, 44 capable of varying the coupling capacitance C in a wide range are mounted on the variable delay line 10A shown in FIG. 3, a wider variable delay time can be obtained. The variable delay line 1 OA can be obtained.

For example, for the third output signal output to the output terminal 36, the first and second reactance sections 18 and 20 are configured so that the minimum value of the absolute delay time is about 1 ns. By appropriately adjusting the values of the circuit elements, as shown in FIG. 4, the deviation of the absolute delay time for the frequency band of 100 MHz or more can be suppressed to 0.1 Ins or less, and the variable delay time can be reduced. It can be increased to 1 ns.

Also, in the variable delay line 10A of the first specific example, even if the absolute delay time changes to about 2 ns, the transmission characteristics shown in FIG. 5 and the mismatch attenuation shown in FIG. 6 hardly change. Therefore, the pass band of the variable delay line 1OA can be set to a wide bandwidth of 60 MHz or more.

By the way, in the variable delay line 1OA of the first specific example, when the absolute delay time is changed by changing the coupling capacitance C, the phase of the third output signal of the variable delay line 10A changes. Also, the resonance frequencies of the first and second λ / 4 dielectric resonators 46 and 48 are changed. Even if the center frequency in the pass band of the variable delay line 1OA is changed, the absolute delay of the third output signal hardly changes if the bandwidth of the variable delay line 1OA is wide, but the variable delay Only the phase of the third output signal of line 1 OA changes.

The variable delay line 10B of the second specific example shown in FIG. 7 has substantially the same configuration as the variable delay line 1OA of the first specific example shown in FIG. The first and second λ Ζ Ζ are the capacitors 54, 56 of the first and second and the third and fourth parameter diodes 58, 60, which are the third and fourth variable capacitance elements as variable reactance elements. The four dielectric resonators 46 and 48 are connected in parallel.

In this case, one end of the third and fourth capacitors 54, 56 is connected to the anode terminals Al, Α2 of the first and second varactor diodes 42, 44, and the other end is connected to the third and fourth capacitors 54, 56. Connected to the cathode terminals 1 and 2 of the fourth varactor diodes 58 and 60. Further, the anode terminals A 3, Α 4 of the third and fourth varactor diodes 58, 60 are connected to ground and are grounded. Furthermore, the third and fourth voltage control terminals 62 are connected to the power source terminals Κ3 and Κ4 of the third and fourth varactor diodes 58 and 60 so that a DC voltage can be supplied. , 6 4 are connected. In the variable delay line 10 # of the second specific example, the third and fourth varactor diodes 58, 60 are connected to the third and fourth varactor diodes 58, 60 from the third and fourth voltage control terminals 62, 64, respectively. When a DC voltage having substantially the same value is supplied via the first and second varactor diodes 58 and 60, the coupling capacitance of the third and fourth varactor diodes 58 and 60 corresponds to the value of the DC voltage. Change by the same amount. As a result, the change in the absolute delay time due to the change in the coupling capacitance C of the first and second varactor diodes 42, 44, and the change in the first and second λΖ4 dielectric resonators 46, 4 8, the phase change in the third output signal of the variable delay line 10 # based on the change in the center frequency due to the change in the resonance frequency can be compensated for. Specifically, the third and fourth varactor diodes By changing the coupling capacitance の of 58, 60 from C v = C 4 to C v = C 5 or C v = C 6 (C 4> C 5> C 6), FIG. 8 and FIG. As shown, it is possible to change the phase of the third output signal without affecting the absolute delay time of the variable delay line 10B. With this, the absolute delay time can be changed while maintaining the phase of the third output signal in the variable delay line 10B at a predetermined value, and the desired delay time and the variable delay time are provided. The variable delay line 10B can be realized.

The variable delay line 10C of the third specific example shown in FIGS. 10 to 14 has substantially the same circuit configuration as the variable delay line 1OA of the first specific example shown in FIG. First, as shown in FIG. 10, first and second voltage control terminals 50 and 52 are connected to first and second parasitic diodes via resistors 74 and 76, respectively. 4 2 and 4 4 are connected to the terminal Kl, Κ2. As shown in FIGS. 11 to 15, the variable delay line 10 C is formed by laminating a plurality of ceramic layers S 1 to S 11, and then firing and sintering the ceramic substrate ( (Integral structure) 7 8.

Specifically, as shown in FIGS. 11 and 12, the variable delay line 10 C of the third specific example has a plurality of wiring patterns formed on the surface of a ceramic substrate 78. The first and second varactor diodes 42, 44 and the resistors 74, 76 are mounted on the pattern, and the circuit elements other than the circuit elements described above are formed in the ceramic substrate 78. '

Almost the entire upper surface 78 e of the ceramic substrate 78 is covered by a metal case 80 serving as an upper lid for the ceramic substrate 78. In the lower part of the four side surfaces of the case 80, legs 80a to 80d are formed at the center thereof. Therefore, when the ceramic substrate 78 and the case 80 are overlapped so that the legs 80a to 80d are in contact with the upper surface 78e, as described above, almost the entire upper surface 78e is formed. Is covered with case 80, but of the four side surfaces of case 80, there are four corners where legs 80a to 80d are not formed, and four corners of top surface 78e. A gap 81 is formed between them.

Of the first to fourth side surfaces 78 a to 78 d which are the surface of the ceramic substrate 78,

At the center of the first and fourth side surfaces 78 a and 78 d, as shown in FIGS. 11 and 12, surface earth electrodes 82 a and 82 d are provided on the upper surface of the ceramic substrate 78. It is formed from 7 8 e to the bottom 7 8 f. In the first side surface 78a, near the second side surface 78b, an input terminal 34 is formed from the top surface 78e to the bottom surface 78f of the ceramic substrate 78. . On the other hand, among the first side surface 78 a, the portion near the third side surface 78 c facing the second side surface 78 b is connected to the output terminal 36 from the upper surface 78 e of the ceramic substrate 78. It is formed over the bottom surface 7 8 f.

The first voltage control terminal 50 is located at a position near the second side 78 b of the fourth side 78 d facing the first side 78 a, and the upper surface 7 It is formed from 8 e to the bottom surface 7 8 f. On the other hand, of the fourth side surface 78 d, at a position near the third side surface 78 c, the second voltage control terminal 52 extends from the upper surface 78 e to the bottom surface 78 f of the ceramic substrate 78. Is formed.

The input terminal 34, the output terminal 36, the first and second voltage control terminals 50 and 52, and the surface ground electrodes 8 2a and 8 2d are shown in FIG. 12 and FIG. As shown in FIG. 3, the first to fourth side surfaces 78 a to 78 d extend to the top surface 78 e and the bottom surface 78 f, respectively.

In the center of the top surface 78 e near the second side surface 78 b, a surface ground electrode 82 b is provided with an input terminal 34, an output terminal 36, and first and second voltage control terminals. It is formed so that it does not directly contact 50, 52. Further, of the upper surface 78 e, a center ground electrode 82 c near the third side surface 78 c is provided with an input terminal 34, an output terminal 36, and first and second voltages. The control terminals 50 and 52 are formed so as not to come into direct contact with the control terminals.

Thus, when the case 80 and the upper surface 78 e of the ceramic substrate 78 are overlapped, as shown in FIGS. 11 and 14, the surface earth electrodes 82 a to 82 d and the case 80 are overlapped. The legs 80a to 80d of the variable delay line 10C are in direct contact, and all the circuit elements of the variable delay line 10C are shielded from the outside. The gap 81 formed when the case 80 and the ceramic substrate 78 are overlapped is formed by the input terminal 34, the output terminal 36, and the first and second voltage control terminals 50 to the case 80. Acts as an escape part for the 52.

As shown in Figs. 11 and 13, the bottom surface 78 f The electrode 82 e is formed. The input terminal 34, the output terminal 36, and the first and second voltage control terminals 50, 52 are separated from each other by a predetermined distance without directly contacting the surface ground electrodes 82a to 82e. It is arranged in.

In addition, as shown in FIGS. 12 and 13, terminals 84 a to 84 h are provided at the center of the upper surface 78 e at the input terminal 34, the output terminal 36, and the first and second terminals. The voltage control terminals 50 and 52 and the surface earth electrodes 82 a to 82 d are formed in parallel at a predetermined interval without directly contacting each other. The first and second varactor diodes 42 and 44 and the resistors 74 and 76 are mounted on the upper surface 78 e having the terminals 84 a to 84 h as described above.

In this case, the power source terminals K 1, K 2 (see FIG. 10) of the first and second Barak diode 42, 44 are connected to the terminals 84a, 84d, and the anode terminals Al, A 2 (see Figure 11) is connected to terminals 84e and 84h. Resistors 74 and 76 are connected to terminals 84b, 84c, 84f and 84g. Note that the resistors 74 and 76 are composed of, for example, chip resistors.

As shown in FIGS. 13 and 14, the variable delay line 10 C of the third specific example is formed by stacking and firing and integrating the above-described plurality of ceramic layers (S 1 to S 11). The ceramic substrate 78 is constituted.

The ceramic substrate 78 is formed by stacking a first ceramic layer S1 to a first ceramic layer S11 in order from the top. These first to eleventh ceramic layers S1 to S11 are composed of one or a plurality of layers.

A capacitor electrode 86a is formed on one main surface of the second ceramic layer S2 in the ceramic substrate 78 so as to face the terminals 84a and 84b. The capacitor electrode 86a has a substantially convex shape in which a portion facing the terminal 84a is formed with a large area and a portion facing the terminal 84b is formed with a small area.

Further, on one principal surface of the second ceramic layer S2, a straight line bisecting line m () connecting the second and third side surfaces 78b and 78c with respect to the capacitor electrode 86a is provided. A vertical line connecting the first and fourth side surfaces 78a and 78d: representatively described on one main surface of the third ceramic layer S3) at a location axially symmetrical with the terminal 84c therebetween. , At the point opposite 8 4 d, A capacitor electrode 86 b is formed. In other words, the capacitor electrodes 86a and 86b are formed so that portions having a small area face each other across the bisector m.

Further, on one main surface of the second ceramic layer S2, the connection electrode 88 faces the terminals 84f and 84g so as not to come into direct contact with the capacitor electrodes 86a and 86b. It is formed.

On one main surface of the third ceramic layer S3, a capacitor electrode 86c having substantially the same shape as the capacitor electrode 86a is formed to face the capacitor electrode 86a, and A capacitor electrode 86 d having substantially the same shape as the capacitor electrode 86 b is formed to face the capacitor electrode 86 b. Therefore, the first capacitor 38 is constituted by the capacitor electrodes 86a and 86c opposed to each other with the second ceramic layer S2 interposed therebetween, and is opposed to the second ceramic layer S2 with the second ceramic layer S2 interposed therebetween. A second capacitor 40 is constituted by the formed capacitor electrodes 86 b and 86 d.A central portion of one main surface of the fifth ceramic layer S5 includes first and second capacitors. The first and second resonance electrodes 90a, 90b as the dielectric resonators 46, 48 are formed from the fourth side surface 78d toward the first side surface 78a, respectively. Have been. The first and second resonance electrodes 90a and 90b are formed axially symmetric with respect to the bisector m.

In this case, one end of the first resonance electrode 90a is a short-circuit end 92a connected to the fourth side surface 78d, and the other end of the first resonance electrode 90a is a surface earth electrode. The open end 94a is formed so as not to come into direct contact with 82a and 82d. The first resonance electrode 90a is formed in a substantially J-shaped wiring pattern on one main surface of the fifth ceramic layer S5. That is, this wiring pattern extends from the fourth side surface 78 d to which the short-circuit end 92 a is connected to the first side surface 78 a, and is formed at the center of the fifth ceramic layer S 5. The portion bends and extends toward the second side surface 78d, and further bends and extends toward the fourth side surface 78d. Then, the end of the portion bent toward the fourth side surface 78d faces the fourth side surface 78d. Open end 94a.

On the other hand, as described above, the second resonance electrode 9 Ob is a substantially J-shaped wiring pattern formed axially symmetric with the first resonance electrode 90a with respect to the bisector m. That is, one end of the second resonance electrode 90 b is a short-circuit end 92 b connected to the fourth side surface 78 d, and the other end of the second resonance electrode 90 b is a surface ground electrode 8. An open end 94b that is formed so as not to directly contact 2a and 82d, and faces the fourth side surface 78d.

One main surface of the eighth ceramic layer S8 has a starting point at a position closer to the second side surface 78b of the first side surface 78a, and the third to seventh ceramic layers S3 to S A substantially J-shaped first wiring pattern 96a ending at a location facing the capacitor electrode 86d with the 7 interposed therebetween is formed. In this case, the start point is connected to the input terminal 34, and the end point is formed so as not to directly contact the surface ground electrodes 82a and 82d.

On the other hand, one main surface of the seventh ceramic layer S7 has a starting point at a position closer to the third side surface 78c of the first side surface 78a, and the third to seventh ceramic layers S3 A substantially abbreviated second wiring pattern 96b is formed ending at a point facing the capacitor electrode 86c with respect to S7. In this case, the start point is connected to the output terminal 36, and the end is formed so as not to directly contact the surface ground electrodes 82a and 82d.

The first and second wiring patterns 96 a and 96 b constitute a hybrid coupler 12. In this case, the start point of the first wiring pattern 96 a is the input terminal 22 of the hybrid camera 12, and the end point corresponds to the second output terminal 16. In addition, the starting point of the second wiring pattern 96 b is the isolation terminal 24 of the hybrid coupler 12, and the ending point corresponds to the first output terminal 14.

A DC voltage supply electrode (D) is provided on almost the entire main surface of the 10th ceramic layer S10.

The C electrode 98 is formed so as not to directly contact the surface ground electrodes 82a and 82d. The DC electrode 98 is connected to the first and second pressure control terminals 50 and 52 formed on the fourth side surface 78d. 13060

1 6

On one main surface of the fourth, sixth, and ninth ceramic layers S4, S6, and S9, inner-layer ground electrodes 82f to 82h are formed over substantially the entire surface, respectively.

The second and third ceramic layers S2, S3 (capacitor layer 70) constituting the first and second capacitors 38, 40 and the first and second The fourth and fifth ceramic layers S 4 and S 5 (resonant circuit layer 68) constituting the λΖ4 dielectric resonators 46 and 48 are electrically separated. In the inner-layer ground electrode 82 f, there are no electrodes formed at locations facing the terminals 84 e and 84 h, the capacitor electrodes 86 c and 86 d, and the connection electrode 88. Insulated areas (insulated areas) are provided respectively.

Also, the fourth and fifth ceramic layers S 4, S 5 (resonant circuit layer 6 8) constituting the first and second λ / 4 dielectric resonators 46, 48 are formed by the inner layer earth electrode 82 g. ) And the sixth to eighth ceramic layers S 6 to S 8 (hybrid cover layer 66) constituting the hybrid power brass 12 are electrically separated from each other. And the inner layer ground electrode

Insulation regions are provided in the portion of 82 g opposite to the connection electrode 88, the end of the first wiring pattern 96 a and the end of the second wiring pattern 96 b, respectively.

Furthermore, the sixth to eighth ceramic layers S 6 to S 8 (hybrid force plastic layer 66) constituting the hybrid force bra 12 by the inner layer earth electrode 82 h and the DC electrode

9 and 8 are electrically separated. And, in the inner layer ground electrode 82 h, an insulating region is provided at a position facing the connection electrode 88.

Furthermore, the first ceramic layer S1 functions as a varactor diode layer 72 on which the varactor diodes 42 and 44 are mounted on the upper surface 78e.

The connection electrode 88 and the DC electrode 98 are connected via a via hole 99a formed through an insulating region in the inner-layer ground electrodes 82f to 82h. Further, the connection electrode 88 and the terminal 84 are connected via a via hole 99b. Furthermore, the terminal 84 f and the capacitor electrode 86 a are connected via a via hole 99 c. Furthermore, the terminal 84a and the capacitor electrode 86a are connected via a via hole 99d. Thus, when a DC voltage is supplied to the DC electrode 98 via the first voltage control terminal 50, the DC voltage is supplied to the power source terminal K1 of the first diode 42.

The terminal 84 e and the open end 94 a of the first resonance electrode 90 a are connected via a via hole 99 e formed through an insulating region in the inner-layer ground electrode 82 f. . Furthermore, the capacitor electrode 86 c and the end of the second wiring pattern 96 b are connected via a via hole 99 を通して formed through the insulating region in the inner-layer ground electrodes 82 f and 82 g. Have been. Thus, a series circuit including the first capacitor 38, the first varactor diode 42, and the first λΖ4 dielectric resonator 46 is formed.

On the other hand, the connection electrode 88 and the terminal 84 g are connected via a via hole 99 g. Further, the terminal 84c and the capacitor electrode 86b are connected via a via hole 99h. Furthermore, the capacitor electrode 86b and the terminal 84d are connected via a via hole 99i.

Thus, when a DC voltage is supplied to the DC electrode 98 via the second voltage control terminal 52, the DC voltage is supplied to the cathode terminal K2 of the second varactor diode 44. .

The terminal 84 h and the open end 94 b of the second resonance electrode 90 b are connected via a via hole 99 j formed through an insulating region in the inner-layer ground electrode 82 f. . Further, the capacitor electrode 86 d and the end of the first wiring pattern 96 a are connected to each other through a via hole 99 k formed through an insulating region in the inner-layer ground electrodes 82 f and 82 g. I have. Thus, a series circuit including the second capacitor 40, the second diode 44, and the second λΖ4 dielectric resonator 48 is formed.

Further, the surface earth electrode 82b and the inner layer earth electrode 82f to 82h are connected via two via holes 99 to 99m formed through the first to eighth ceramic layers S1 to S8. Connected. In this case, the via hole 991 is formed so as to extend from the portion near the first side surface 78a of the surface earth electrode 82b to the bottom surface 78f. Have been. The via hole 99 m is formed so as to extend from the portion of the surface ground electrode 82 b closer to the fourth side surface 78 d to the bottom surface 78 f.

Furthermore, the surface ground electrode 82c and the inner layer ground electrode 82f to 82h are formed by two via holes 99n, 990 formed through the first to eighth ceramic layers S1 to S8. Connected through. In this case, the via hole 9.9 η is formed so as to extend from the portion of the surface ground electrode 82 c closer to the first side surface 78 a to the bottom surface 78 f. The via hole 99 o is formed so as to extend from the portion of the surface ground electrode 82 c closer to the fourth side surface 78 d to the bottom surface 78 f.

In the variable delay line 10 C of the third specific example, each circuit element except the first and second varactor diodes 42, 44 and the resistors 74, 76 is connected to the above-described ceramic substrate 78 internal part. Thus, the variable delay line 10 C can be reduced in size.

On the other hand, also in the variable delay lines 10A and 10B (see FIGS. 3 and 7) of the first and second specific examples, similarly to the variable delay line 10C described above, Forming the first and second λ / 4 dielectric resonators 46, 48 and the first to fourth capacitors 38, 40, 54, 56 inside the ceramic substrate 78, It goes without saying that the first to fourth varactor diodes 42, 44, 58, and 60 can be mounted on the ceramic substrate 78 from outside.

Note that the variable delay line of the present invention is not limited to the above-described embodiment, but may adopt various configurations without departing from the gist of the present invention. Industrial applicability

As described above, according to the variable delay line of the present invention, the hybrid delay and the variable reactance element are mounted on the variable delay line, and the variable reactance elements are connected to the two output terminals of the hybrid coupler, respectively. Therefore, it is possible to suppress the fluctuation of the input impedance and the output impedance in the variable delay line, and it is possible to set the absolute delay time and the variable delay time to desired values, thereby increasing the passband. .

Claims

The scope of the claims

1. an input terminal (22) to which an input signal is supplied; first and second output terminals (14, 16) for outputting first and second output signals having a phase difference of 90 ° from each other; A hybrid power brass (12) having an isolation terminal (24) for outputting a reflected signal based on the first and second output signals as a third output signal; and the first and second output terminals ( First and second reactance sections (18, 20) connected to each other and having substantially the same reactance,

Has,

The first and second reactance units (18, 20) include first and second variable reactance elements having substantially the same reactance.

A variable delay line, characterized in that:

2. In the variable delay line according to claim 1,

The first and second reactance sections (18, 20) are composed of first and second capacitors (38, 40) having substantially the same capacitance, and the first and second variable reactance elements. And a series circuit of the first and second variable capacitance elements (26, 42), the first resonance circuit (30, 46), and the second resonance circuit (32, 48). Variable delay line.

3. In the variable delay line according to claim 2,

The series circuit of the third and fourth capacitors (54, 56) and the third and fourth variable capacitance elements (58, 60) as variable reactance elements is connected to the first resonance circuit (30, 46). ) And the second resonance circuit (32, 48) are connected in parallel with each other.

4. In the variable delay line according to claim 2 or 3,

Multiple ceramic layers are stacked to form a ceramic monolithic structure (78). And

The ceramic integrated structure (78) includes a ceramic layer (66) on which the hybrid force bra (12) is formed, the first resonance circuit (30, 46), and the second resonance circuit (32, 48). ), And a ceramic layer (70) on which at least the first and second capacitors (38, 40) are formed.

A variable delay line, characterized in that: