WO2004031944A1

WO2004031944A1 - Processor and instruction control method

Info

Publication number: WO2004031944A1
Application number: PCT/JP2002/010370
Authority: WO
Inventors: Takaharu Ishizuka
Original assignee: Fujitsu Limited
Priority date: 2002-10-04
Filing date: 2002-10-04
Publication date: 2004-04-15
Also published as: JPWO2004031944A1; JP3807740B2

Abstract

A processor issues an instruction including a branching instruction having a first identifier (ID=0), and executes speculation by the branching estimation. When a branching mistake is detected, an instruction in the correct direction is issued with a second identifier (ID=1) after the mistakenly issued instruction. After all the instructions issued prior to the branching are completed the instruction which has been mistakenly issued by the branching estimation is canceled, and issuing of the instruction in the correct direction is resumed. Since the processor updates the identifier (ID) attached to the instruction after the branching mistake has occurred, it is possible to issue the instruction in the correct direction without waiting for completion of all the instructions issued before the branching instruction which has caused a mistake, there by improving the processing performance. At least two identifiers are sufficient to be attached to the instruction, which reduces the quantity of the hardware.

Description

Description Processor and instruction control method

The present invention relates to a processor and an instruction control method for executing an instruction at speculation by branch prediction, and more particularly to a processor and an instruction control method for efficiently canceling a subsequent instruction when branch prediction fails. Background art

Conventionally, in processors with both branch prediction and dynamic pipeline processing, an in-order instruction issuing unit that depends on the program order, an out-of-order instruction execution unit that does not depend on the program order, and a program order It has an instruction decision section (commit) of the dependent inorder, and executes instructions speculatively based on branch prediction. That is, the instruction issuing unit fetches and decodes a plurality of instructions in order, and causes the instruction storage queue of the instruction storage unit to hold instruction operations (opcodes) and operands. The instruction execution unit speculatively executes instructions in out-of-order order and obtains a result as soon as all operands are prepared in the instruction storage unit and the arithmetic unit becomes available. The instruction determinator holds the incomplete instruction in the reorder buffer, and if the branch prediction is correct, the result of the instruction following the branch is valid, and is written from the reorder buffer to the register or memory. . If the branch prediction is missed and a branch miss occurs, all instructions following the branch are invalidated and removed from the instruction storage unit and the reorder buffer. Here, the reorder buffer is managed by a reorder map assigned by the instruction issuing unit as a substitute for the actual register used in the instruction, and the result of the instruction executed in the order of the order is written to the actual register. It is held only while the instruction determination unit waits for the insertion. Therefore, when the branch prediction is incorrect, the valid bit on the map of the reorder buffer assigned to the instruction following the branch is turned off.

Figure 1 shows the processing when a branch error occurs in a conventional processor. In the speculative execution of the instruction by the branch prediction in FIG. 1A, the branch prediction for the branch instruction B4 is If a branch miss 200 is detected due to a failure, as shown in Fig. 1 (B), if all instructions before branch instruction B4 are completed, after the resources including the reorder buffer have been updated, Cancel processing 202 is performed to cancel instructions 5 to 8 that have been executed by mistake, and then, as shown in Fig. 1 (C), the issuance of instructions that become instructions 50 and 51 in the correct direction is started, and the instruction sequence is changed. I want to run.

However, such an instruction control has a problem in that, unless the instruction before the branch instruction B4, which resulted in a branch error, is not completed, the issue of a correct instruction sequence cannot be resumed, and the processing performance of instruction execution is low. is there. Therefore, in order to improve the processing performance of the processor, instruction control for occurrence of a branch error as shown in Fig. 2 is performed. In this instruction control, as shown in Fig. 2 (A), the instruction sequence is provided with IDs as identifiers, such as ID = 0, ID = 1, and ID = 2, at the boundary of the branch instructions B4 and B8. If the branch error 204 of the branch instruction B 4 is detected in FIG. 2B, the instructions 5 to 11 having ID = 1 and ID = 2 newer than ID = 0 of the branch instruction B 4 are canceled. The process 206 is performed, and then, as shown in FIG. 2 (C), the issuance of the instructions 50 and 51 in the correct direction is started, and the instruction sequence is executed. Therefore, even if all instructions before the branch instruction B4 in which the branch miss 204 is detected are not completed, execution of a correct instruction sequence can be resumed, and the processing performance of the instruction can be improved. However, in the instruction control of Fig. 2, if a large number of branch instructions are to be operated simultaneously, it is necessary to have IDs corresponding to the number of the branch instructions, resulting in an increase in hardware amount and complexity, resulting in a processor. There is a problem that it is not suitable for speeding up. Also, in the case of a processor that is renaming, it is necessary to take a snapshot of the rename information for each branch instruction, which similarly increases the amount of hardware and makes it more unsuitable for accelerating the processor. There's a problem. This problem is described in detail as follows.

FIG. 3 is an explanatory diagram of a rename map used in a conventional processor. Renameable registers REG0, REG1, REG2, REG3, and reorder buffers ROB0, ROB1, ROB2 used for the rename are shown. , ROB 3 will be described as an example. The rename map 210 is a table for indexing the register number REG—AD212 as entry numbers 0 to 3. If the effective bit field AV field 216 is “1”, the register is reordered buffer. Dress HOB—Renamed in the reorder buffer HOB indicated by field 218 of AD. For example, when register REG1 is renamed using reorder buffer ROB3 when an instruction is issued, write "1" in the valid flag AV field 2 16 of the rename map entry "1", and also write the reorder buffer address ROB_AD field. Write “3” in 2 1 4. When the instruction is completed and the rename is completed, the valid flag AV field 216 is rewritten to “0” to release the Rio buffer ROB3. Further, if it is desired to rename the same register REG 1 with another Rioder buffer ROB 0 before releasing the reorder buffer ROB 3, only the fields 2 14 of the rename buffer address HOB—AD in the rename map 210 are read, for example. Rewrite to “0” and set the valid flag AV field 2 16 to “0” when the instruction that last renamed the register REG 1 is completed. For this reason, as shown in the instruction control of Fig. 2, when an ID, which is an identifier, is assigned to each instruction sequence at the boundary of a branch instruction, the rename map 210 shown in Fig. Buffer address: OB—there is a need to have an AD field 211 and an intermediate state valid flag AV field, which increases the amount of hardware. The problem is that it is complicated and is not suitable for high-speed processors. In the speculative execution of such an instruction, even if an exception occurs during the execution of the instruction, the speculatively executed instruction that has been issued without exception becomes invalid, and the same problem as that of a branch error occurs. is there.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a processor and an instruction control method capable of promptly resuming instruction issuance when a speculative execution is erroneous with a small amount of hardware. Disclosure of the invention

(Processor controlling branch prediction)

In the first embodiment of the processor according to the present invention, a first instruction control unit for issuing an instruction including a branch instruction with a first identifier (ID = 0) attached thereto and performing speculative execution by branch prediction, and When detected, the second instruction control unit issues an instruction in the correct direction following the instruction issued incorrectly, and incorrectly issues a branch prediction after all instructions before the branch are completed. Cancel the command that has been done and issue the command in the correct direction A third instruction control unit for starting a line. As described above, the processor of the present invention updates the identifier (ID) assigned to an instruction after the occurrence of a branch error, and thus corrects the instruction without waiting for completion of all instructions before the branch instruction in which the branch error occurred. By being able to issue instructions in different directions, the processing performance of the instructions is improved, and at least two identifiers need to be attached to the instructions, so that both the improvement in processing performance and the reduction in the amount of hardware can be achieved.

In a second embodiment of the processor of the present invention, a first instruction control unit for issuing an instruction including a branch instruction with a first identifier (ID = 0) attached thereto and performing speculative execution by branch prediction, A second instruction control unit is provided that, when a branch error is detected, attaches a second identifier (ID = 1) to the instruction in the correct direction following the instruction issued in error and issues it. Same as the first mode, except that after the first branch miss is detected and the instruction in the correct direction is issued, the second branch miss is detected for the old branch instruction before that. A third instruction control unit that waits for all instructions before the old branch instruction to complete, cancels all subsequent instructions, and then starts issuing instructions in the correct direction. I do. After starting instruction issuance in the right direction for the first branch error in this way, if a branch error occurs for the old branch instruction before that, it waits for completion of all instructions before the old branch instruction and is not completed Can be issued after canceling all instructions, and in this case also, at least two identifiers need to be attached to the instructions, and the amount of hardware can be reduced.

According to a third embodiment of the processor of the present invention, a first instruction control unit for issuing an instruction including a branch instruction with a first identifier (ID = 0) attached thereto and performing speculative execution by branch prediction, A second instruction control unit that issues an instruction in the correct direction with a second identifier (ID = 1) attached after an instruction that has been issued incorrectly when a branch miss is detected. Is the same as the first form, except that after the first branch miss is detected and an instruction in the correct direction is issued, a second branch miss is detected in an older branch instruction before that. In this case, the third instruction control unit that determines that the instruction is in the correct direction by detecting the first branch error, cancels the issued instruction, and then starts issuing instructions in the correct direction determined by detecting the second branch error. The second branch miss is detected and the correct direction instruction is issued. After completion, all instructions before the old branch instruction A fourth instruction control unit that waits, cancels the instruction on the second branch miss side, and then resumes issuing instructions in the correct direction. After starting instruction issuance in the correct direction for the first branch miss in this way, if a branch miss occurs for the old branch instruction before that, wait for completion of all instructions before the old branch instruction. All the uncompleted instructions that were erroneously issued in the first branch prediction can be canceled to issue an instruction in the correct direction, then wait for the completion of the instruction before the old branch instruction, and then erroneously issued uncompleted After canceling this instruction, the processing performance can be improved by issuing an instruction in the correct direction, and the amount of hardware can be reduced because at least two identifiers need to be attached to the instruction.

A fourth embodiment of the processor according to the present invention includes a first instruction control unit that issues an instruction including a branch instruction with a first identifier (ID = 0) attached thereto and performs speculative execution by branch prediction, and a first branch error. The point that the second instruction control unit that issues an instruction in the correct direction following the instruction issued in error and attaches the second identifier (ID = 1) to the instruction Same as the first mode, except that after the first branch miss is detected and the instruction is issued in the correct direction, the second branch is executed with a new branch instruction in the instruction issued as the correct direction. When a miss is detected, a third instruction control unit is provided that waits for all instructions before the new branch instruction to complete, cancels all subsequent instructions, and then starts issuing instructions in the correct direction. It is characterized by. In this way, after the instruction is issued in the correct direction for the first branch error, if a branch error occurs for a new branch instruction in the correct instruction sequence, the completion of all instructions before the new branch instruction is completed. It is possible to wait and cancel all unfinished instructions and issue instructions in the correct direction. In this case as well, only two identifiers need to be attached to the instructions, and the amount of hardware can be reduced.

A fifth embodiment of the processor according to the present invention includes a first instruction control unit that issues an instruction including a branch instruction with a first identifier (ID = 0) attached thereto and performs speculative execution by branch prediction, and a first branch error. And a second instruction control unit that issues an instruction in the correct direction following the instruction issued erroneously with the second identifier '(ID = 1) attached when detecting This is the same as in the first mode, but in addition to this, after the first branch error is detected and the instruction in the correct direction is started, the new If the second branch miss is detected with a new branch instruction, wait for all instructions before the old branch instruction where the first branch miss is detected to complete, while the instruction issue in the correct direction is suppressed. The third instruction control unit that cancels the instruction that was issued by mistake due to the old branch instruction, cancels the suppression, and starts issuing the instruction in the correct direction, and the correct direction by detecting the second branch error Wait for all instructions before the new branch instruction to complete after the instruction issuance of the first branch instruction has been completed, cancel the instruction on the second branch miss side, and then move in the correct direction due to the second branch miss. A fourth instruction control unit for resuming instruction issuance. After starting instruction issuance in the correct direction for the first branch error in this way, if a branch error occurs for a new branch instruction in the instruction sequence in the correct direction, all instructions before the new branch instruction are completed. Without waiting for the first branch, all uncompleted instructions that were erroneously issued due to the first branch error can be canceled and the instruction in the correct direction can be issued. By canceling unfinished instructions and issuing instructions in the correct direction, processing performance can be improved, and the amount of hardware can be reduced because at least two identifiers are required for instructions.

The processor according to the first to fifth embodiments further includes, in an entry referred to by a register number used by an instruction, an address storage area of a reorder buffer used for renaming, and instruction control. A rename map having a plurality of valid flag areas corresponding to a plurality of attached identifiers, and a rename map referred to by a register number when a register used by an instruction is renamed using a reorder buffer. The instruction that stores the address of the reorder buffer used for renaming in the entry, turns on the valid flag corresponding to the identifier attached to the instruction, and is issued erroneously when a branch error is detected. Turn off the valid flag of the rename map corresponding to the identifier attached to the instruction, and correspond to another identifier attached to the instruction issued in the correct direction. A renaming processing unit for turning on the valid flag of the rename map is provided so that an instruction in the correct direction issued upon detection of a branch error uses the rename information of an instruction issued erroneously. It is characterized by preventing.

(Instruction control method of branch prediction)

A first form of the instruction control method of the processor according to the present invention is as follows. A first step of issuing an instruction including a branch instruction with a first identifier attached thereto and performing speculative execution by branch prediction;

A second step of, when a branch miss is detected, issuing an instruction in the correct direction following the instruction issued in error with a second identifier attached thereto;

After all instructions before the branch are completed, a third step of canceling an instruction issued erroneously by branch prediction and starting instruction issuance in the correct direction is provided.

A second form of the instruction control method for a processor according to the present invention is as follows.

A first step of issuing an instruction including a branch instruction with a first identifier attached thereto and performing speculative execution by branch prediction;

A second step of, after detecting the first branch miss, issuing an instruction in the correct direction following the instruction issued in error with a second identifier attached thereto;

After the first branch miss is detected and an instruction in the correct direction is issued, if the old branch instruction detects a second branch miss, wait until all instructions before the old branch instruction have completed. , A third step of canceling all subsequent instructions and then starting to issue instructions in the correct direction;

It is characterized by having.

A third mode of the processor instruction control method according to the present invention is as follows.

After the first branch miss is detected and an instruction in the correct direction is issued, if a second branch miss is detected in an older branch instruction before that, the correct direction is determined by detecting the first branch miss. A third step of starting to issue an instruction in the correct direction determined by detecting the second branch error after canceling the issued instruction.

After the second branch miss is detected and the instruction in the correct direction is issued, wait for all instructions before the old branch instruction to complete, and then execute the instruction that was erroneously issued by the second branch prediction. Cancels and then resumes issuing instructions in the correct direction. And

It is characterized by having.

A fourth mode of the instruction control method for a processor according to the present invention is as follows.

A second step of, after detecting the first branch error, issuing an instruction in the correct direction attached to the second identifier after the erroneously issued instruction;

After the first branch miss is detected and the instruction in the correct direction is started, if the second branch miss is detected in a new branch instruction in the instruction issued as the correct direction, the instruction before the new branch instruction is A third step of waiting for all to complete, canceling all subsequent instructions, and then starting to issue instructions in the correct direction;

It is characterized by having.

Four modes of the instruction control method of the processor according to the present invention are as follows.

After the first branch miss is detected and instruction is issued in the correct direction, if the second branch miss is detected in a new branch instruction in the instruction issued as the correct direction, instruction issuance in the correct direction is suppressed. Waits for all instructions before the old branch instruction where the first branch miss is detected to be completed, cancels the instruction that was issued incorrectly by the old branch instruction, and releases the suppression. 3rd step to start issuing instructions in the correct direction

After the issuance of instructions in the correct direction due to the detection of the second branch error, wait for all instructions before the new branch instruction to complete, and then cancel the instruction issued by the detection of the first branch prediction. A fourth step of resuming instruction issuing in the correct direction due to the second branch error;

It is characterized by having.

Further, in the instruction control method of the processor according to the first to fifth embodiments, the instruction A rename map that has an address storage area for the Rioda buffer used for renaming and multiple valid flag areas corresponding to multiple identifiers attached by instruction control in the entry referenced by the register number used. If you set

When renaming a register used by an instruction using a reorder buffer, store the address of the reorder buffer used for renaming in the entry of the rename map referenced by the register number and attach it to the instruction. Turn on the valid flag corresponding to the identifier

When a branch mistake is detected, the valid flag of the rename map corresponding to the identifier attached to the instruction issued erroneously is turned off, and the identifier corresponding to another identifier attached to the instruction issued in the correct direction is turned off. By turning on the valid flag of the rename map,

It is characterized in that an instruction in the correct direction issued by detection of a branch miss is prevented from using rename information by an instruction issued incorrectly.

(Processor that handles exceptions)

The processor of the present invention can be applied similarly to the case of a branch miss, in addition to the speculative execution of an instruction by branch prediction, and also in the case of canceling an instruction speculatively executed without an exception by the occurrence of an exception. The following first to fifth modes are also taken for the occurrence of an exception in response to the detection of

A first mode of a processor for processing an exception occurrence according to the present invention includes: a first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached thereto and executes the instruction speculatively without exception occurrence; A second instruction control unit that issues an exception handling routine instruction with a second identifier attached after an instruction that is erroneously issued as no exception when an exception is detected, and an exception generating instruction And a third instruction control unit for canceling an instruction in which an exception has occurred and an instruction which has been issued as having no exception and starting to issue an instruction in an exception generation routine after all the previous instructions have been completed. I do. A second mode of processing the exception occurrence of the processor according to the present invention includes: a first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached thereto and executes the instruction speculatively without occurrence of the exception; When the first exception is detected, the instruction of the exception handling routine is added with the second identifier following the instruction that was erroneously issued as no exception. The second instruction control unit, which issues a second exception, detects the occurrence of the first exception, and issues an exception processing routine instruction that is in the correct direction after the first exception has been issued In this case, the instruction that caused the exception and all subsequent instructions are canceled after all instructions before the old branch instruction are completed, and then the instruction issuance of the exception handling routine due to the second exception is started. And three instruction control units.

A third mode for processing an exception occurrence of the processor of the present invention includes: a first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached thereto and executes the instruction speculatively without occurrence of an exception; A second instruction control unit for issuing an instruction of an exception handling routine with a second identifier added immediately after the instruction which is erroneously issued as no exception when the first exception is detected; After the first exception is detected and the instruction in the correct direction is issued and the second exception is detected in an earlier instruction, the first exception is detected. After canceling the issued instruction of the exception handling routine, a third instruction control unit that starts issuing the instruction of the exception handling routine that is oriented in the right direction by detecting the occurrence of the second exception, and that the second exception is detected Exception handling rules After the instruction of the previous instruction has been issued, wait for all instructions before the old branch instruction to complete, and then the instruction that caused the first exception and the instruction that was erroneously issued as having no exception due to this instruction And a fourth instruction control unit that resumes issuing an instruction of an exception handling routine upon occurrence of the second exception after canceling the second exception.

A fourth mode for processing an exception occurrence of the processor according to the present invention includes: a first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached thereto and executes the instruction speculatively without exception occurrence; A second instruction control unit for issuing an instruction of an exception handling routine with a second identifier added immediately after the instruction which is erroneously issued as no exception when the first exception is detected; After the first exception has been detected and the instruction of the exception handling routine in the correct direction has started, the second exception occurrence is detected with a new instruction in the instruction issued by the exception handling routine. In this case, wait for all instructions before the new exception generation instruction to complete, cancel the exception generation instruction and all subsequent instructions, and then start issuing the exception handling routine for the first exception. A third command control unit.

According to a fifth aspect of the present invention for processing a processor exception occurrence, a first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached thereto and executes the instruction speculatively without exception occurrence; A second instruction control unit that issues an exception handling routine instruction with a second identifier attached after an instruction that is erroneously issued as having no exception when the first exception is detected; If the first exception occurrence is detected and the direction is correct, after the issuance of an instruction in the exception handling routine is started, if the second exception occurrence is detected in a new instruction in the instruction issued by the exception handling routine, the exception handling routine In the state where the issue of the first exception has been detected, wait until all instructions before the one that caused the first exception have been completed, and then erroneously determine that the old exception occurred and that no exception occurred due to this instruction. Cancels the issued instruction, cancels the suppression, and starts issuing an exception handling routine instruction in the correct direction when the second exception occurs.The third instruction control unit, and the exception occurs when the second exception occurs After the instruction in the processing routine is issued, wait for all instructions before the new exception generation instruction to complete, and then cancel the second exception occurrence instruction and the instruction issued in the first exception generation exception handling routine. And a fourth instruction control unit that resumes issuing an instruction of an exception handling routine upon occurrence of a second exception.

(Instruction control method for handling exceptions)

The first mode of handling the exception occurrence of the instruction control method of the processor according to the present invention can be applied similarly to the case of a branch miss when canceling an instruction speculatively executed due to an exception. The following first to fifth modes are also applied to the occurrence of an exception in response to the detection.

A first mode of an instruction control method for a processor according to the present invention for processing an exception occurrence includes issuing an instruction including an exception occurrence instruction with a first identifier attached thereto, and speculatively executing the instruction as no exception occurrence. When,

A second step in which, when an exception is detected, an instruction of an exception handling routine is attached with a second identifier, followed by an instruction that has been erroneously issued as no exception has occurred, and

After all instructions before the exception generation instruction have completed, no exception generation instruction and no exception generation And a third step of canceling the issued instruction and starting instruction issuing of the exception generating routine. '' The second mode of the instruction control method for processing an exception occurrence of a processor according to the present invention is to issue an instruction including an exception occurrence instruction with a first identifier attached thereto, and to execute the instruction speculatively without exception occurrence. Steps and

After the first exception occurrence is detected and the instruction of the exception handling routine in the correct direction is issued, if an older instruction before that detects the second exception occurrence, all instructions before the old branch instruction are completed. A third step of canceling the exception generating instruction and all subsequent instructions after waiting for the execution of the second instruction, and then starting to issue the instruction of the exception handling routine due to the second exception generation; and

It is characterized by having.

A third form of the instruction control method for processing an exception occurrence in a processor according to the present invention includes the first step of issuing an instruction including an exception occurrence instruction with a first identifier attached thereto and executing the instruction speculatively without exception occurrence. When,

A second step of, when an exception is detected, issuing an instruction of an exception handling routine with a second identifier attached after an instruction which is erroneously issued as no exception is generated,

After the first exception has been detected and the instruction of the exception handling routine in the correct direction has been issued, if an earlier instruction detects a second exception occurrence, it is issued by detecting the first exception occurrence. A third step of, after canceling the exception processing routine instruction, starting to issue an exception processing routine instruction that is oriented in a correct direction by detecting the occurrence of the second exception;

After the second exception has been detected and the instruction of the exception handling routine has been issued, after waiting for all instructions before the old branch instruction to complete, the instruction that caused the first exception and the exception caused by this instruction Cancels the instruction that was erroneously issued as no occurrence, and then resumes issuing instructions in the exception handling routine due to the second exception The fourth step,

It is characterized by having.

A fourth mode of an instruction control method for processing an exception occurrence of a processor according to the present invention includes the steps of: issuing an instruction including an exception occurrence instruction with a first identifier attached thereto; and speculatively executing the instruction with no exception occurrence. When, '

When the first exception is detected, the first exception that issues the instruction of the exception handling routine with the second identifier attached after the instruction that was erroneously issued as no exception After the issuance of an instruction in the exception handling routine that has been detected and the direction is correct, if the second exception occurrence is detected in a new instruction among the instructions issued by the exception handling routine, all instructions before the new exception occurrence instruction A third step of waiting for completion, canceling the exception generating instruction and all subsequent instructions, and then starting issuing an instruction in an exception handling routine due to the first exception;

It is characterized by having.

According to a fifth aspect of the present invention, there is provided an instruction control method for processing an exception occurrence of a processor, comprising the steps of: issuing an instruction including an exception occurrence instruction with a first identifier attached thereto; and speculatively executing the instruction without exception. When,

If the first exception occurrence is detected and the instruction of the exception handling routine in the correct direction is started, and if the second exception occurrence is detected in a new instruction among the instructions issued by the exception handling routine, the exception handling routine is executed. Waiting for all instructions before the old exception generating instruction in which the first exception has been detected to be completed in the state where the instruction issue of A third step of canceling the issued instruction, releasing the suppression, and starting to issue an instruction of an exception handling routine that is oriented in a correct direction due to the occurrence of the second exception;

After the instruction of the exception handling routine has been issued due to the second exception, the instruction of the second exception and the first And a fourth step of canceling the instruction issued in the exception generating routine due to the exception and then restarting the instruction issuing of the second exception handling routine due to the occurrence of the exception. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is an explanatory diagram of an instruction control operation for a branch miss in a conventional processor; FIG. 2 is an explanatory diagram of an instruction control operation for a branch miss in a conventional processor in which a different ID is assigned to each branch instruction;

Figure 3 is an illustration of the rename map used in the conventional processor;

FIG. 4 is a block diagram of a functional configuration of a processor to which the present invention is applied;

FIG. 5 is an explanatory diagram of a rename map used in the processor of the present invention;

FIG. 6 is a circuit diagram comparing the hardware scale according to the number of IDs attached to an instruction with the present invention and the conventional example;

FIG. 7 is a block diagram of the first mode branch prediction instruction control unit according to the present invention;

FIG. 8 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 7;

FIG. 9 is a timing chart of the instruction control operation according to the embodiment of FIG. 7;

FIG. 10 is a flowchart of instruction control according to the embodiment of FIG. 7;

FIG. 11 is a block diagram of the second mode branch prediction instruction control unit according to the present invention; FIG. 12 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 11;

FIG. 13 is a timing chart of the instruction control operation according to the embodiment of FIG. 11; FIG. 14 is a flowchart of instruction control according to the embodiment of FIG. 11;

FIG. 15 is a block diagram of a third mode branch prediction instruction control unit according to the present invention; FIG. 16 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 15;

FIG. 17 is a timing chart of the instruction control operation according to the embodiment of FIG. 15; FIG. 18 is a flowchart of the instruction control according to the embodiment of FIG. 15;

FIG. 19 is a block diagram of a fourth mode branch prediction instruction control unit according to the present invention; FIG. 20 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 19;

Fig. 21 is a timing chart of the instruction control operation according to the embodiment of Fig. 19; Fig. 22 is a flowchart of instruction control according to the embodiment of Fig. 19; FIG. 23 is a block diagram of a fourth mode branch prediction instruction control unit according to the present invention; FIG. 24 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 23;

FIG. 25 is a timing chart of the instruction control operation according to the embodiment of FIG. 23; FIG. 26 is a flowchart of instruction control according to the embodiment of FIG. 24;

FIG. 27 is a flowchart of instruction control integrating the branch prediction instruction control of the first to fifth modes according to the present invention;

FIG. 28 is a block diagram of the first mode exception occurrence instruction control unit according to the present invention; FIG. 29 is an explanatory diagram of the instruction control operation according to the embodiment of FIG. 27;

FIG. 30 is a flowchart of instruction control according to the embodiment of FIG. 27;

FIG. 31 is a block diagram of a second mode exception occurrence instruction control unit according to the present invention; FIG. 32 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 31;

FIG. 33 is a flowchart of instruction control according to the embodiment of FIG. 31;

FIG. 34 is a block diagram of a third mode exception occurrence instruction control unit according to the present invention; FIG. 35 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 34;

FIG. 36 is a flowchart of instruction control according to the embodiment of FIG. 34;

FIG. 37 is a block diagram of a fourth mode exception occurrence instruction control unit according to the present invention; FIG. 38 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 37;

FIG. 39 is a flowchart of instruction control according to the embodiment of FIG. 37;

FIG. 40 is a block diagram of a fifth mode exception generating instruction control unit according to the present invention;

FIG. 41 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 40;

FIG. 42 is a flowchart of instruction control according to the embodiment of FIG. 41;

FIG. 43 is a flowchart of an instruction control in which the exception occurrence instruction control of the first to fifth modes according to the present invention is integrated;

FIG. 4 is a block diagram of a functional configuration of a processor to which the instruction control of the present invention is applied. In FIG. 4, a processor 10 includes a branch prediction unit 12, an instruction issuing unit 14, an instruction storage unit 16, an instruction execution unit 18, an instruction determination unit 20, a register 22, and a renaming processing unit 24. Is provided. The instruction storage 16 contains a reservation station. There are provided instruction storage queues 2'6-1 to 26-4. The instruction execution unit 18 includes a function processing unit such as a branch processing unit 28, an integer arithmetic unit 30, a floating point arithmetic unit 32, and a load Z store processing unit 34. Further, the renaming processing section 24 is provided with a reorder buffer 36 and a rename map 38. Each processing unit of the processor 10 operates under the control of the instruction control unit 40. In the present invention, the instruction control unit 40 includes a branch prediction instruction control unit 42 and an exception generation instruction control unit 44 which are unique to the present invention, in addition to the normal instruction control. The processor 10 in the embodiment of FIG. 4 performs speculative execution of instructions by using so-called dynamic scheduling and branch prediction together. First, the instruction issuing unit 14 fetches and decodes, for example, four instructions from the instruction cache. The branch prediction unit 12 includes a branch history table for branch prediction, and performs speculative execution in the predicted branch direction. The instruction issued from the instruction issuing unit 14 in order sends each instruction and its operand to the instruction storage unit 16 corresponding to the function processing unit in the instruction execution unit 18. At the same time, the instruction issuing unit 14 registers the instruction in the reorder buffer 36. The instructions sent to the instruction storage unit 16 are executed out-of-order as soon as the corresponding processing unit provided in the instruction execution unit 18 becomes available, and the Rio buffer assigned to the instruction is executed. The result is stored in The instruction deciding unit 20 holds all uncompleted instructions in the reorder buffer 36, and upon receiving the result of the determination as to whether or not the branch is taken by the branch processing unit 28 of the instruction executing unit 18, it receives the result. The instruction determination unit 20 determines the processing of the incomplete instruction based on the instruction. That is, if the branch prediction is correct, the result of the instruction following the branch instruction is valid, and is written to the register 22 or a memory (not shown) in in-order according to the order of the program. If the branch prediction is missed and a branch miss occurs, the results of all subsequent instructions to the branch instruction are invalidated, and are canceled from the instruction storage unit 16 and the Rioder buffer 36. As described above, when a branch error is detected for an instruction speculatively executed by branch prediction, the branch prediction instruction control unit 42 according to the present invention provided in the instruction control unit 40 is erroneous due to the branch error. It efficiently processes instructions in the correct direction based on cancellation of instructions issued in the direction and detection of branch mistakes.

FIG. 5 is a diagram showing a rename machine provided in the renaming processing section 24 of the processor 10 of FIG. FIG. In the branch prediction instruction control of the present invention, at least two IDs, ID = 0 and 1, may be used as IDs which are identifiers attached to instructions. Corresponding to the two IDs assigned to this instruction, the rename map 38 contains the reorder buffer address field (ROB—AD) 46 for each of the entries 0, 1, 2, and 3 shown on the right side specified by the register number 50 of the instruction. In addition, the valid flag field (AV0) 48-0 for storing the valid flag A V0 corresponding to ID = 0 and the valid flag field (A VI) 48-1 for storing the valid flag AV1 corresponding to ID = 1 Provided. In the rename map 38, the address of the Rio buffer to be renamed, for example, "00" is written in the entry specified by the register number 50, for example, in the reorder buffer address field 46 of the entry "0" for the register number RG1. . At this time, if the ID assigned to the instruction is ID == 0, the flag of the corresponding field of the valid flag field 48-0 is set to “1”. To release the reorder buffer upon completion of an instruction or to invalidate an instruction by detecting a branch error, for example, set the valid flag field 48-0 of ID = 0, which is set to "1", to "0". Good.

FIG. 6 is a circuit diagram as hardware that generates a cancel signal for canceling the valid flag field to “0” according to the ID attached to the instruction for the rename map 38 in FIG. FIG. 6A is a circuit corresponding to two IDs = 0 and 1 in the rename map 38 of the present invention in FIG. On the other hand, FIG. 6 (B) shows a hardware circuit in the case where eight ID = 0 to 7 are used in the conventional instruction control shown in FIG. In the circuit used in the present invention in FIG. 6A, when a cancel signal is generated, the 1-bit ID data provided in the ID field of the instruction is set in the latch 52, If ID = 0, the output of the receiver 54 becomes 1 and the output 1 is generated at the timing of the completion or invalid input of the instruction with ID = 0 for AND gate 56-0, which is the cancel signal from OR gate 58. Is output as When ID = 1 of the ID field of the instruction is held in the latch 52, the output of the buffer 55 becomes 1, which is accompanied by the completion or invalidation of the instruction with ID = 1 for AND gate 56-1. A cancel signal is output via the OR gate 58 when the signal is received. On the other hand, in the circuit used in the conventional instruction control shown in FIG. 6 (B), corresponding to eight IDs 0 to 7, the output line from the latch 60 is a 3-bit line, and the latch 60 A decoder 62 is provided to divide the 3-bit information in the ID field of the instruction stored in the decoder into eight types of IDs, and the output from the decoder 62 becomes eight signal lines. Further, following the decoder 62, AND gates 64-0 to 64-7 are provided corresponding to the eight ID == 0 to 7, and these outputs are combined by the OR gate 66 to extract the cancel signal. ing. As is clear from the comparison between the case of using two IDs of the present invention in FIG. 6 (A) and the conventional case of using eight IDs of FIG. 6 (B), the number of IDs added to the instruction increases. It can be seen that the circuit size for outputting the cancel signal becomes larger as the number of signals increases. On the other hand, in the present invention, as shown in Fig. 6 (A), basically, only two IDs need to be used, so it is necessary to complete the instruction or invalidate the instruction due to a branch mistake. It can be seen that the hardware amount of the cancel signal can be sufficiently reduced.

FIG. 7 is a block diagram of a functional configuration of a first mode branch prediction instruction control unit 42-1 which is a first embodiment of the branch prediction instruction control unit 42 provided in the processor 10 of FIG. The first mode branch prediction instruction control unit 42-1 includes a first instruction control unit 68, a second instruction control unit 70, and a third instruction control unit 72-1.

FIG. 8 shows an instruction control operation by the first mode branch prediction instruction control unit 421-1 of FIG. 7. The control operation of FIG. 7 will be described below with reference to this. First, the first instruction control unit 68 issues instructions 1 to 11 including branch instructions B4 and B8 with ID = 0 as the first identifier as shown in FIG. 8 (A). As for the branch instruction sequence B4, instructions 5 to 11 are issued in the direction determined by the branch prediction and executed speculatively. When a branch miss 80 is detected for the branch instruction B4 by speculative execution of an instruction based on such a branch prediction, the second instruction control unit 70 in FIG. 7 detects the branch miss 80. At that point, as shown in Fig. 8 (B), following instructions 5 to 11 issued by mistake, instructions 5 0 and 51 in the correct direction are another ID that serves as the second identifier. Issued with = 1. Next, as shown in FIG. 8 (C), the third instruction control unit 72-1 in FIG. 7 recognizes that all the instructions 1 to B4 before the branch are completed, and then branches the branch instruction B4. Life issued accidentally by prediction Execute cancel processing 84 for instructions 5 to 11 and then start issuing instructions following instructions 50 and 51 in the correct direction. At the time of cancel processing of the instruction 5 to instruction 11 issued by mistake 84 to instruction 11, ID = 0 and the resource of the instruction attached to the instruction to be canceled are canceled. Specifically, the ID field of the instruction canceled by the circuit of FIG. 6A is set in the latch 52 to generate a cancel signal, and the cancel signal is used by the instruction storage unit 16 of the processor 10 of FIG. In addition to canceling the instruction 5 to instruction 11 that was issued by mistake and stored in the valid flag field corresponding to ID = 0 in the rename map 38 in Fig. 5, all entries in the field 4 8-0 are deleted. By setting this bit to "0", the Rioda buffer 36 used as an instruction resource is released. As described above, in the control operation of the first mode branch prediction instruction control unit of the present invention, since a new ID is added to the instruction in the correct direction issued after the detection of a branch mistake, the branch is performed. It is only necessary to use two types of IDs for the instruction cancel for mistakes and for issuing instructions in the correct direction, and the amount of hardware involved in using IDs can be minimized. FIG. 9 is a timing chart corresponding to the instruction control operation of FIG. 8, in which instructions issued in the vertical direction are arranged, and the elapsed time is indicated in the horizontal direction. In FIG. 9, if a branch miss 80 is detected at time t1 for branch instruction B4, the branch instruction B4 has been issued and execution ends at time t2 after execution has ended. As shown in FIG. 8 (B), ID = 1 is assigned and instructions 50 and 51 in the correct direction are started to be issued. Thereafter, at time t3, after all instructions up to branch instruction B4 are completed at time t3, the erroneously issued instructions 5 to 11 are canceled.

FIG. 10 is a flow chart of the instruction control by the first mode branch prediction instruction control unit 421-1 in FIG. First, an instruction is issued with the same ID in step s1, and if a branch error occurs in the branch instruction that has been issued and executed in step S2, another ID is issued in step S3. And issue an instruction in the correct direction. Then, in step S4, it is monitored whether all instructions before the branch error have been completed.If all instructions have been completed, in step S5, a speculative failure instruction and a reorder buffer that are erroneously issued due to a branch error are included. After canceling the resource, instruction issuance in the correct direction is resumed in step S6. FIG. 11 is a block diagram of a second mode branch prediction instruction control unit 42-2 as a second embodiment of the branch prediction instruction control unit provided in the processor 10 of FIG. 4, and a first instruction control unit. 68, a second command control unit 70 and a third command control unit 72-2. Among them, the first instruction control unit 68 and the second instruction control unit 70 are the same as the first mode branch prediction instruction control unit 42--1 in FIG. In such a case, while an instruction in the correct direction is issued due to a branch miss, instruction control is performed when an older branch instruction causes a branch miss.

FIG. 12 is an explanatory diagram of the control operation by the second mode branch prediction instruction control unit 42-2 in FIG. First, as shown in FIG. 12A, the first instruction control unit 68 issues instructions including branch instructions B 2, B 4, and B 8 with ID = 0, and issues the branch instruction B 2 , B4, and B8 execute instructions speculatively by branch prediction. In this state, it is assumed that a branch miss 80 is detected along with the execution of the branch instruction B4 by the auto-order. In response to the detection of the branch miss 80, the second instruction control unit 70, following the instructions 5 to 11 issued in error, continues the instruction in the correct direction as shown in FIG. Issue 50, 51 with another ID = 1. The control operations by the first command control unit 68 and the second command control unit 70 are the same as those already described in FIGS. 8 (A) and 8 (B). Next, as shown in FIG. 12 (C), if a branch miss 82 is detected along with the execution of the branch instruction B2 older than the branch instruction B4 in which the branch miss 80 is detected in the art order, After the branch miss 8 2 is detected, the third instruction control unit 7 2-2 waits until all instructions 1 and B 2 before the old branch instruction B 2 are completed as shown in FIG. Cancel all subsequent instructions 3 to 51. Perform cancel processing 86. In this cancellation process 86, ID = 0 and resources are also canceled. Then, as shown in Fig. 12 (E), after the cancellation process 86 of the instruction issued erroneously, the instruction 60 0, 61, 62,. Resumes issuing. In the control operation of the second mode branch prediction instruction control unit 42-2, there is no need to assign an ID to each branch instruction as in the conventional example of FIG. However, since it is only necessary to attach another ID to the instruction generated in the correct direction, only two IDs are required, and the amount of hardware that generates the cancel signal is minimized as shown in Fig. 6 (A). With Monkey

FIG. 13 is a timing chart of the instruction control corresponding to FIG. In FIG. 13, when a branch miss 80 is detected at time t 1 along with execution of the branch instruction B 4, instructions 50 and 51 in the correct direction are assigned another ID = 1 from time t 2. Issue with After that, at time t3, if a branch miss 82 caused by the execution of the branch instruction B2 older than the branch instruction B4 is detected, the timing after the completion of the branch instruction B2 at the time t4 becomes incorrect. , All of the issued instructions 3 to 51 have been cancelled, and at time t5, the issuance of instructions 60, 61,...

FIG. 14 is a flowchart of instruction control by the second mode branch prediction instruction control unit 42-2 in FIG. First, in step S1, an instruction is issued with the same ID, and in step S2, if a branch error occurs along with the execution of the branch instruction for which branch prediction is performed, another ID is assigned in step S3. And issue an instruction in the correct direction. Thereafter, if a branch miss occurs in the branch instruction that is older than the branch instruction that caused the first branch miss in step S4, it is checked in step S5 whether all of the branch instructions before the old branch miss have been completed. When all instructions before the old branch instruction of the branch error have been completed, in step S6, after canceling all speculative failure instructions issued by mistake due to the branch error and their resources including the Rioder buffer, step S7 Press to start issuing instructions in the correct direction.

FIG. 15 is a block diagram of the third mode branch prediction instruction control unit 42-3 in the branch prediction instruction control unit 42 of FIG. 4. In this embodiment, the first instruction control unit 68 , A second command control unit 70, a third command control unit 72-3, and a fourth command control unit 74-3. Among them, the first instruction control unit 68 and the second instruction control unit 70 are the same as the first mode branch prediction instruction control unit 42-1 in FIG. Also, the third instruction control unit 723 and the fourth instruction control unit 744-3 are the same as the third instruction control unit 722 of the second mode branch prediction instruction control unit 422 of FIG. It is characterized by performing instruction control when a branch miss is detected for an old branch instruction after the first branch miss is detected. FIG. 1'6 is an explanatory diagram of the control operation of the third mode branch prediction instruction control unit 42-3 of FIG. FIGS. 16 (A), (B) and (C) are the same as those of the second mode branch prediction instruction control unit 42-2 in FIG. That is, as shown in Figure 16 (A), When a branch error 80 is detected, as shown in Figure 16 (B), instructions 50 and 51 in the correct direction follow instructions 5 to 11 issued incorrectly. Issue with a different ID-1. Then, as shown in Fig. 16 (C), if a branch miss 82 is detected along with the execution of a branch instruction B2 older than the branch instruction B4 that detected the branch miss 80, The third instruction control unit 7 2-3 cancels the instructions 50 and 51 issued by judging that the direction is correct by detecting the first branching error 80 as shown in Fig. 16 (D). After the processing 88, as shown in FIG. 16 (E), the issuance of instructions 60 and 61 in the correct direction determined by detecting the branch miss 82 is started. Subsequently, the fourth instruction control unit 74-3 in FIG. 15 waits until all the instruction sequences 1 and B2 before the old branch instruction sequence B2 are completed as shown in FIG. Cancel processing 90 for canceling instructions 3 to 11 issued erroneously due to branch prediction of instruction B 2, and then reissue instructions issued following instructions 60 and 61 issued in the correct direction. Open. Of course, in the cancellation process 90, ID = 0 and assets are canceled at the same time as the cancellation of the instruction. The control operation of the third mode branch prediction instruction control unit 42-3 in FIG. 16 is compared with the control operation of the second mode branch prediction instruction control unit 42-2 in FIG. In the same situation, the first branch miss 80 is detected following the old branch instruction's branch miss 82, but in the case of Fig. 16, the second branch miss as shown in Fig. 16 (D). When 8 2 is detected, cancel processing 8 8 of instructions 50 and 51 issued in the correct direction due to the first detected branch error 80 is performed, and then, as shown in Figure 16 (E). The instructions 60 and 61 in the correct direction are issued for the branch error 82, and the timing of issuing the instruction in the correct direction due to the second branch error 82 is faster than in Figure 12. The performance of instruction processing can be improved by a corresponding amount.

FIG. 17 is a timing chart corresponding to the instruction control of FIG. In FIG. 17, at time t1, if a branch miss 80 is detected along with execution of branch instruction B4, then at time t2, instructions 50, 51 in the correct direction are assigned different IDs. Issued with = 1. Subsequently, at time t3, when a branch miss 82 is detected along with the execution of the branch instruction B2 older than the branch instruction B4, at the subsequent time t4, the instructions 50, 5 After canceling 1, 1 Start issuing instructions 60 and 61 in the new direction. Comparing the timing chart in Figure 17 with the same two branch misses 80 and 82 in Figure 13 detected, the issuance of instructions 60 and 61 in the correct direction to be finally issued The timing is faster in Figure 17 and the instruction processing performance is correspondingly higher.

FIG. 18 is a flowchart of the instruction control of the third mode branch prediction instruction control unit 42-3 in FIG. In FIG. 18, first, an instruction is issued with the same ID in step S1. If it is determined in step S2 that a branch error has occurred along with execution of a branch instruction among the instructions issued in step S2, step S3 is executed. Issue a command in the correct direction with a different ID. Subsequently, in step S4, it is checked whether a branch miss occurs by executing a branch instruction that is older than the branch instruction that caused the first branch miss, and if an old branch miss occurs, the first step in step S5 is performed. The resource including the speculative failure instruction and reorder buffer issued in the correct direction for the branch error of the above is canceled. Subsequently, in step S6, an instruction in the correct direction for the branch miss that occurred for the old branch instruction is issued with the same ID as in step S3. Subsequently, in step S7, it is determined whether or not all the instructions before the old branch miss have been completed.When all the instructions have been completed, in step S8, the speculatively failed instruction issued erroneously due to the branch miss and its You have to cancel resources.

FIG. 19 is a block diagram of a fourth mode branch prediction instruction control unit 42-4 which is the fourth embodiment of the branch prediction instruction control unit 42 provided in the processor 10 of FIG. In this embodiment, a first command control unit 68, a second command control unit 70, and a third command control unit 72-4 are provided, and a first command control unit 68 and a second command control unit 72 are provided. The control unit 70 is the same as in the first embodiment in FIG. On the other hand, the third instruction control unit 72-4 performs a new instruction in the instruction sequence issued in the correct direction for the branch error after the branch error is first detected in the speculative instruction execution by the branch prediction. It is characterized by performing instruction control when a second branch error is detected for a branch instruction.

FIG. 20 is an explanatory diagram of the control operation of the fourth mode branch prediction instruction control unit 42-4 in FIG. In FIG. 20 (A), the first instruction control unit 68 issues an instruction including a branch instruction B2, B4, and B8, and the branch instruction is executed speculatively by branch prediction. Out-of-order execution of branch instruction B4 detects branch miss 80 Then, as shown in FIG. 20 (B), instructions 5 to 5 which are erroneously issued by the second instruction control unit 70 are followed by instructions 5 to 5 after instructions 11 to 11. With another ID = l. Next, as shown in Fig. 20 (C), the branch miss 92 is detected along with the execution of the branch instruction B52 included in the instructions 50 to 53 issued in the correct direction with ID = 1. Then, as shown in FIG. 20 (D), the third instruction control unit 72-4 waits until all the instructions before the branch instruction B52 where the branch miss 92 has been detected are completed, and then proceeds. Cancel processing 94 is performed to cancel all instructions 5 2 and 5 3, and then instructions 60 0, 61 1 and 62 2 in the correct direction due to branch mistake 90 as shown in Figure 20 (E). Start issuing.

FIG. 21 is a timing chart corresponding to the instruction control of FIG. In FIG. 21, when a branch miss 80 is detected along with the execution of the branch instruction B4 at time t1, an ID = 1 is added at time t2, and instructions 50 to 53 in the correct direction are added. Start issuing. After that, when a branch miss 90 is detected along with the issuance of the branch instruction 52B in the instruction issued in the correct direction at the time t3, the branch instruction 92 where the branch miss 92 is detected at the time t4. Wait for all instructions before B52 to complete, and at time t5 after completion, start issuing instructions 60, 61, and 62 in the correct direction due to branch miss 92.

FIG. 22 is a flowchart of the instruction control of the fourth mode branch prediction instruction control unit 42-4 in FIG. In FIG. 22, first, an instruction is issued with the same ID in step S 1, and if a branch error is detected in step S 2 along with execution of a branch instruction among the issued instructions, step S 3 A different ID is assigned to the instruction in the right direction, and the instruction in the correct direction is issued after the instruction issued incorrectly. Subsequently, in step S4, in response to the execution of a branch instruction in the instruction issued in the correct direction with respect to the branch error detected in step S2, if the occurrence of a branch error is determined, a new branch is determined in step S5. It is checked whether all instructions before the branch instruction for the miss have been completed. When it is determined that the instruction has been completed, all speculative failure instructions and resources that were erroneously issued due to the second branch error in step S6 are cancelled, and then instruction issuance in the correct direction is started in step S7.

FIG. 23 is a block diagram of a fifth mode branch prediction instruction control unit 42-5 serving as the fifth embodiment of the branch instruction prediction control unit 42 provided in the processor 10 of FIG. This W

In the twenty-fifth embodiment, a first instruction control unit 68, a second instruction control unit 70, a third instruction control unit 72-5, and a fourth instruction control unit 74-5 are provided. The second command control unit 70 is the same as that of the first embodiment shown in FIG. On the other hand, the third instruction control unit 72-5 and the fourth instruction control unit 74-5 detect the correct branch after first detecting the branch prediction as in the case of the third mode branch prediction instruction control unit 42-3 in FIG. It is characterized by performing instruction control when the second branch error is detected in the instruction issued in the direction. FIG. 24 shows the control operation of the fifth mode branch prediction instruction control unit 42-5 in FIG. FIG. 24 (A) shows a case where an instruction including the branch instructions B2, B4, and B8 issued by the first instruction control unit 68 detects a branch miss 80 along with the execution of the branch instruction B4. When 80 is detected, instructions 50 and 51 in the correct direction are issued with another ID = 1, following instructions 5 to 11 that were issued incorrectly as shown in FIG. 24 (B). Next, as shown in FIG. 24 (C), if a branch miss 92 is detected upon execution of the branch instruction B52 in the instructions 50 to 53 issued in the correct direction, the third instruction control unit in FIG. 72-5 is based on detection of branch miss 92, and in the state where the issuance of instructions (instructions 60, 61, 62, ...) in the correct direction for branch miss 92 is suppressed, and the older branch where branch miss 80 is detected After canceling all the instructions 1 to B4 before the instruction 1 to B4 are completed, cancel processing 96 is performed, and then instructions 60, 61, and 62 in the correct direction due to a branch error 92 as shown in FIG. · · Start issuing '. Subsequently, the fourth instruction control unit 74-5 in FIG. 23 waits until all instructions before the new branch instruction B 52 have completed as shown in FIG. 24 (F), and is issued upon detection of a branch miss 92. After cancel processing 97 for canceling instructions 52 and 53 is performed, instruction issuance following instructions 60, 61 and 62 in the correct direction due to branch mistake 92 is resumed. A comparison between the instruction control in the fifth embodiment shown in FIG. 24 and the instruction control performed when the same branch mistakes 80 and 92 are detected in the fourth embodiment shown in FIG. 20 shows that the fifth embodiment shown in FIG. In Figure 24 (D), when the old branch miss 80 is detected in the branch instruction B4, all the instructions before the branch instruction B4 have been completed. After executing the cancel process 96 to delete the instruction 11, the instructions 60, 61, and 62 in the correct direction for the branch mistake 92 are issued as shown in FIG. 24 (E), and the instructions 60, 61, and 62 in the correct direction are issued. Issuance timing is Figure 20 Therefore, the fifth embodiment of FIG. 24 can improve the instruction processing performance. In the instruction control of Fig. 24, the case where two IDs are used is taken as an example, but if three IDs are made available, there is no need to wait until the IDs expire. It is also possible to issue an instruction and wait for ID release when the ID expires. That is, in FIG. 24 (D), the issuing of instructions in the correct direction due to the branch mistake 92 is not suppressed, and the issuing of instructions 60 and 61 in the correct direction is started at the stage with ID == 2.

FIG. 25 is a timing chart corresponding to the instruction control of FIG. In FIG. 25, when a branch miss 80 is detected at the time t1 due to the execution of the branch instruction B4 according to the fault order, the instructions 50 to 53 in the correct direction are issued at the time t2. Start with another ID == 1. After that, when a branch miss 92 is detected along with the execution of the branch instruction B52 in the instructions 50 to 53 issued in the correct direction, the branch instruction B4 before the first branch miss 80 is detected. At time t4 after all of these instructions have been completed, instructions 5 to 11 that were issued by mistake in the branch prediction of branch instruction B4 are cancelled. Next, at time t5, the issuance of instructions 60, 61, and 62 in the correct direction for the branch miss 92 is started with the already released ID = 0. After that, at time t6, when all the instructions before the branch instruction B52 corresponding to the branch miss 92 are completed, the instructions 52, 53 that were erroneously issued in the branch prediction of the branch instruction B52 are canceled. I do. Referring to the timing chart of the fifth embodiment in FIG. 25 as the timing chart of the fourth embodiment in FIG. 21, instructions 60, 61, and The issue timing of 62 is earlier in the fifth embodiment of FIG. 25, and the processing performance of the instruction can be improved accordingly.

FIG. 26 is a flowchart of instruction control of the fifth branch prediction instruction control unit 42-5 in FIG. In FIG. 26, in step S1, an instruction is issued with the same ID, and in step S2, if it is determined that a branch error has occurred due to execution of a branch instruction, another ID is assigned in step S3. The instruction in the right direction is issued after the instruction that was issued by mistake. The processing of steps S1 to S3 is the processing of the first command control unit 68 and the second command control unit 70 in FIG. Next, with the execution of the branch instruction in the instruction issued in the correct direction in step S4 by the third instruction control unit 72-5, the second instruction When it is determined that a branch error has occurred, the process proceeds to step S5, where it is determined in step S5 that all instructions before the old branch instruction are completed in a state where the issuance of instructions in the correct direction is suppressed. Proceeding to step S6, cancel the instruction erroneously issued by the old branch instruction, release the inhibition, and start issuing the instruction in the correct direction for the new branch miss. Subsequently, the fourth instruction control section 7 4-5 determines in step S7 whether or not the previous instruction of the new branch miss has been completed. In step S8, the instruction issued by mistake in step S8 is canceled, and then in step S9, the instruction is issued in the correct direction.

FIG. 27 is a flowchart of the branch prediction instruction control unit 42 of the processor 10 of FIG. 4, and the first to fifth mode branch prediction instruction controls described in FIGS. 7 to 25 are all integrated. It is a flowchart of branch prediction instruction control. In FIG. 27, steps S1 to S3 are the processing of the first instruction control unit 68 and the second instruction control unit 70, and are executed while issuing the instruction with the same ID in step S1. If it is determined in step S2 that a branch error has occurred during execution of the branch instruction, an instruction in the correct direction is issued by attaching another ID to the instruction issued in error in step S3. Subsequently, it is checked in step S4 whether all instructions before the branch miss have been completed. When all the instructions before the branch miss have been completed, the process proceeds to step S7 to execute the first mode branch prediction instruction control. The processing contents of the first mode branch prediction instruction control in step S7 are the processing in steps S5 and S6 in FIG. If all instructions before the branch miss have not been completed in step S4, the occurrence of the second branch miss is checked in step S5. In step 6, it is determined whether the second branch miss is older than the first branch miss. If there is an old branch miss, the flow advances to step S8 to perform the second mode or third mode branch prediction instruction control. The second mode branch predictive instruction control performed in step S8 is the processing of steps S5 to S7 in FIG. The branch prediction instruction control in the third mode in step S8 is the processing in steps S5 to S8 in FIG. On the other hand, if there is no branch miss older than the first branch miss in step S6, a new branch miss due to execution of a branch instruction among instructions issued in the correct direction due to a branch miss in step S2. Because Proceeding to step S9, the control of the fourth or fifth mode branch prediction instruction is performed. The branch prediction instruction control of the fourth mode in step S9 is the processing of steps S5 to S7 in FIG. The control of the branch prediction instruction in the fifth mode in step S9 in FIG. 27 is the processing in steps S5 to S9 in FIG.

As described above, the present invention may perform the branch prediction instruction control in any one of the first to fifth modes, and may perform either the second mode or the third mode with respect to the first mode. The control may be a combination of any one of the fourth mode and the fifth mode.

Next, the exception occurrence instruction control unit 44 provided in the processor 10 of FIG. 4 will be described. As an embodiment of the exception generation instruction control unit 44, the first mode exception generation instruction control unit 44_1 in FIG. 28, the second mode exception generation control unit 44-2 in FIG. 31, and FIG. 3 4 3rd mode exception generation instruction control unit 4 4 3 13, 4 th mode exception generation instruction control unit 4 4 in FIG. 7 4 and 5th mode exception generation instruction control unit 4 4 in FIG. There are five. Each of the first mode, second mode, third mode, fourth mode, and fifth mode exception occurrence instruction control unit 441-1 to 44-4-5 is a specific example of the branch prediction instruction control unit 42 already described. Of the branch miss in the processing of each of the first mode, the second mode, the third mode, the fourth mode, and the fifth mode branch prediction instruction control unit 42_1 to 42-5 which are typical embodiments. This is equivalent to replacing the detection with the occurrence of an exception.In the case of a branch miss, the speculative failure instruction following the branch instruction in which the branch miss was detected is cancelled. The difference is that the speculation failure instruction is canceled. The following briefly describes the occurrence of an exception. The first mode exception occurrence instruction control unit 4411 in FIG. 28 includes a first instruction control unit 98, a second instruction control unit 100, and a third instruction control unit 102-1.

FIG. 29 shows the instruction control operation of the first mode exception occurrence control unit 44-1 of FIG. 28, and the instructions 1 to 10 issued with ID = 0 in FIG. 29 (A). When the exception 105 occurs in the instruction 4, if the instruction 5 to the instruction 11 issued as no exception occurs and another ID = 1 is added after the instruction 50, the instruction 50, 5 Issue 1. Next, as shown in Fig. 29 (C), when all of the steps 1 to 3 before the exception generation instruction 4 are completed, the cancellation processing 1 08 for canceling the speculation failure instruction 5 to the instruction 11 is executed. After that, issue of the exception handling routine is resumed.

FIG. 30 is a flowchart of the first mode exception occurrence instruction control. The instruction is issued with the same ID in step S1, and if the execution of the instruction in step S2 determines that an exception has occurred, another instruction follows the speculative failure instruction in step S3. Issue an exception handling routine instruction with the ID of Next, if it is determined in step S4 that all the instructions before the occurrence of the exception have been completed, the speculative failure instruction and the resources issued in step S5 that have been issued as having no exception have been canceled. The instruction issuance of the exception handling routine is restarted.

FIG. 31 is a block diagram of the second mode exception occurrence instruction control unit 44, and includes a first instruction control unit 98, a second instruction control unit 100, and a third instruction control unit 102. — Equipped with 2. FIG. 32 shows the control operation of the second mode exception generating instruction control unit 44-2. First, assuming that exception 1 106 is generated by execution of instruction 4 of instructions 1 to 11 issued with ID = 0 in Fig. 32 (A), Speculatively failed instructions 5 to 11 issued without exception as described above are followed by another ID = 1, followed by instructions 50 and 51 of the exception handling routine. Next, assuming that the execution of instruction 2 that is older than instruction 4 that caused exception 106 in Figure 32 (C) causes exception 110 to occur with the execution of instruction 2, and the exception for instruction 2 that is older than instruction 4 as shown in Figure 32 (D) When instruction 1 before 1 1 0 is completed, cancel processing 1 1 2 is performed to cancel all subsequent instructions 2 to 51 including instruction 2 where exception 1 1 0 occurred. As shown in (E), issuance of instructions 60, 61, 62,... Of the exception handling routine is started.

FIG. 33 is a flowchart of the second mode exception generation instruction control. In Fig. 33, in step S1, an instruction is issued with the same ID, and if an exception occurs during execution of the instruction in step S2, it is erroneously issued as no exception in step S3. Issue an exception handling routine instruction with a different ID after the instruction that has been executed. Next, in step S4, it is checked whether an exception has occurred for an instruction older than the first exception occurrence.If an exception occurs for the old instruction, step S5 has completed all instructions before the old exception occurrence instruction. Then, if completed, cancel all speculative failure instructions including the old instruction that caused an exception and its resources in step S6, and then execute the exception handling routine in step S7. Start issuing I do.

FIG. 34 is a block diagram of the third mode exception occurrence instruction control unit 44-13. The first instruction control unit 98, the second instruction control unit 100, and the third instruction control unit 102-3 And the fourth instruction control unit 104-3.

FIG. 35 is an explanatory diagram of the instruction control of the third mode exception occurrence instruction control unit 44-13 in FIG. As shown in Fig. 35 (B), when exception 1 06 occurs with execution of instruction 4 among instructions 1 to 11 issued with ID = 0 as shown in Fig. 35 (A), Speculatively failed instructions 5 to 11 issued as no exception to instruction 4 are followed by instructions 50 and 51 of the exception handling routine with another ID = 1. Then, as shown in Figure 35 (C), if exception 1 110 occurs with the execution of instruction 2 that is older than instruction 4 where exception 106 occurs, as shown in Figure 35 (D), exception 1 After performing cancel processing 1 1 4 to cancel instructions 50 and 51 issued in the instruction processing routine for the occurrence of 06, the exception processing routine of exception 1 1 0 is shown in Figure 35 (E). Issue instructions 60 and 61. And in Figure 35 (F), after the instruction 1 before the instruction 1 of the old exception 1 1 0 is completed, the speculative failure instruction 3 to the instruction 11 including the instruction 2 that generated the exception 1 1 0 are canceled. After the processing 1 16 has been performed, the issuance of the instruction following the instructions 60 and 61 by the exception handling routine of the exception 110 is restarted.

FIG. 36 is a flowchart of the third mode exception generation instruction control. In FIG. 36, an instruction is issued with the same ID in step S1, and if an exception occurs in step S2 'in this instruction, an exception follows the instruction in step S3 in step S3. Issue an exception handling routine with an ID attached after the speculatively failed instruction erroneously issued as no occurrence. Next, in step S4, it is determined whether an exception has occurred in an instruction older than the first exception occurrence, and if an old exception has occurred, in step S5, the speculation issued in the exception handling routine for the first exception occurrence is performed. After canceling the failed instruction and its resources, the instruction of the exception handling routine for the occurrence of the old exception is issued in step S6 with the same ID as in step S3. Subsequently, when it is determined in step S7 that all instructions before the old exception have occurred are completed, in step S8, the speculatively failed instructions and resources issued as no exceptions, including the instruction with the old exception, are deleted. After canceling, issue of the exception handling routine is resumed. FIG. 37 is a block diagram of the fourth mode exception occurrence instruction control unit 44 14, and includes a first instruction control unit 98, a second instruction control unit 100, and a third instruction control unit 102 4. Is provided. FIG. 38 is an explanatory diagram of instruction control of the fourth mode exception occurrence instruction control unit 44-4. In Fig. 38, first, after issuing instructions 1 to 11 as shown in Fig. 38 (A), if an exception 106 occurs with execution of instruction 4, the exception as shown in Fig. 38 (B) Issue the speculatively failed instructions 5 to 11 issued without occurrence, and issue instructions 50 and 51 of the exception handling routine of exception exception 106 with a different ID = 1. Next, as shown in Figure 38 (C), of instructions 50, 51, 52, and 53 issued in the exception handling routine for exception 106, the second exception 1 Assuming that 16 has occurred, as shown in Fig. 38 (D), the speculatively failed instructions 52, 5 that issued the instruction 50 and instruction 51 in which exception 1 16 occurred without exceptions Cancel 3 Cancel processing 1 18 is performed, and then the issuance of instructions 60, 61, 62, ... of the exception handling routine due to exception 1 16 as shown in Fig. 38 (E) is resumed.

FIG. 39 is a flowchart of the fourth mode exception generation instruction control. In FIG. 39, an instruction is issued with the same ID in step S_1, and if it is determined that an exception occurs due to execution of the instruction in step S2, an exception occurs in step S3. An instruction for the exception handling routine is issued with a different ID after the speculatively failed instruction that was erroneously issued as no exception occurred. Subsequently, in step S4, if it is determined that the second instruction is to be generated in accordance with the execution of one of the instructions issued by the exception handling routine, the process proceeds to step S5. If it is determined that all the instructions have been completed, the process proceeds to step S6, and all subsequent speculative failure instructions including the instruction that caused the new exception and its resources are canceled, and then a new exception is generated in step S7. Resumes the issuance of an instruction in the exception handling routine when the error occurs.

FIG. 40 is a block diagram of the fifth mode exception occurrence instruction control unit 44-5. A first instruction control unit 98, a second instruction control unit 100, a third instruction control unit 102-5, and a fourth instruction control unit 104-5 are provided.

FIG. 41 is an explanatory diagram of the instruction control of the fifth mode exception occurrence instruction control unit 44-5. Instructions 1 to 11 issued with ID == 0 as shown in Figure 41 (A) As shown in Figure 41 (B), when an exception 106 occurs due to the execution of the instruction, the speculative failure instructions 5 to 11 issued after the occurrence of the exception 106 following the instruction 4 as having no exception have occurred. Subsequently, instructions 50 and 51 of the exception handling routine are issued with another ID = 1. Next, as shown in FIG. 41 (C), if the second exception 116 occurs with the execution of the instruction 52 in the instructions 50 to 54 issued in the exception handling routine, as shown in FIG. 41 (D) ), And waits for the completion of all executions of instructions 1 to 3 before instruction 4 in which the older exception 106 occurred, and then cancels the speculative failure instructions 5 to 11 following the exception generation instruction 4. . Next, as shown in Fig. 41 (E), following the instructions 53 and 54 that became speculative failure instructions due to the second new exception 116, the exception 116 with ID = 0 released in the cancel processing 120 is added. Start issuing the instructions 60, 61, 62 · · · of the exception handling routine. Eventually, as shown in Figure 41 (F), after waiting for the completion of all instructions 50 and 51 before the instruction 52 where the new exception 1 16 has occurred, the instruction 52 where the exception 116 has occurred and the speculative failure following it After executing the cancel process 122 for canceling the instructions 53 and 54, the instruction issuance is resumed following the instructions 60, 61, 62 · · · which become the exception routine. In the instruction control shown in Fig. 41, the case where two IDs are used is taken as an example, but if three IDs are made available, there is no need to wait until the IDs expire. It is also possible to issue an instruction and wait for ID release when the ID expires. That is, in FIG. 41 (D), the issuance of instructions in the correct direction due to the occurrence of the exception 116 is not suppressed, and the issuance of instructions 60, 61, and 62 in the correct direction is started at this stage with ID = 2. FIG. 42 is a flowchart of the fifth mode exception generation instruction control. In FIG. 42, in step S1, an instruction is issued with the same ID, and in step S2, if an exception occurs due to execution of an instruction in the instruction, a speculative operation following the exception instruction is performed in step S3. An exception handling routine instruction is issued with a different ID after the failed instruction. Next, in step S4, if an exception occurs due to the execution of an instruction in the instruction issued by the exception handling routine, in step S5 an old exception is generated with instruction issuance suppressed by the exception handling routine. Judge whether all instructions before the completed instruction have been completed. When the completion of this instruction is determined, the exception generating instruction and the speculative failure instruction and its resources are canceled in step S6, and the exception handling accompanying the occurrence of the new exception is performed. Of the logical routine is started. Subsequently, it is checked in step S7 whether all instructions preceding the instruction that caused the new exception have been completed.If it is determined that the instruction has been completed, the instruction including the instruction that caused the new exception in step S8 follows. After canceling the speculative failure instruction and its resources, in step S9, the instruction issuing of the exception handling routine accompanying the occurrence of a new exception is restarted.

FIG. 43 shows the first mode, second mode, third mode, fourth mode, and fifth mode of the exception occurrence instruction control section 44 provided in the processor 10 of FIG. This is a flowchart of the exception generation instruction control in which all the exception generation instruction controls are integrated. In the flowchart of FIG. 43, in step S1, an instruction is issued with the same ID, and when the occurrence of an exception is determined by executing the instruction in step S2, another ID is determined in step S3. The instruction of the exception handling routine is issued following the speculative failure instruction. Subsequently, in step S4, it is checked whether or not all the instructions before the occurrence of the exception have been completed. When it is determined that the instruction has been completed, in step S7, control of the first mode exception occurrence instruction is executed. The exception generating instruction control in the first mode is the processing of steps S5 and S6 in FIG. If all instructions before the occurrence of the exception are not completed in step S4, the occurrence of the second exception is checked in step S5. If the second exception has occurred, the process proceeds to step S6, and it is checked whether the exception is older than the first exception. If an old exception has occurred, the process proceeds to step S8, and the second or third mode exception occurrence instruction control is performed. In this case, the exception generation instruction control in the second mode is the processing of steps S5 to S7 in FIG. The exception generation instruction control in the third mode is the processing of steps S5 to S8 in FIG. Further, if it is determined in step S6 that an exception is newer than the first exception, the flow advances to step S9 to control the fourth or fifth mode of the exception occurrence instruction. The exception generation instruction control in the fourth mode is the processing of steps S5 to S7 in FIG. The exception generation instruction control in the fifth mode is the processing of steps S5 to S9 in FIG.

In the above embodiment, the branch instruction is executed as a speculatively executed instruction, and the exception occurrence accompanying the instruction execution is taken as an example. However, the present invention can be applied to other appropriate speculative instructions. it can.

Further, the present invention is not limited to the above embodiment, and does not impair its object and advantages. Including any appropriate modifications. Further, the present invention is not limited by the numerical values shown in the above embodiments. Industrial applicability

As described above, according to the present invention, at the time of speculative instruction execution based on branch prediction, if a branch miss is detected, the speculatively failed instruction that has been erroneously issued is canceled and correct. The process of resuming instruction issue in the direction can be realized at high speed and with a small amount of hardware resources, and can greatly contribute to performance improvement particularly when the operating frequency of the processor is increased.

Similarly, when an instruction exception occurs, the speculatively failed instruction that was issued as having no exception can be canceled, and the instruction can be issued by the exception handling routine with a high speed and a small amount of hardware. In this case as well, it can greatly contribute to performance improvement in a processor whose operating frequency is increased.

Claims

The scope of the claims

1. A first instruction control unit that issues an instruction including a branch instruction with a first identifier attached thereto and executes speculation by branch prediction,

A second instruction control unit that, when a branch miss is detected, issues an instruction in the correct direction following the instruction issued in error with a second identifier attached thereto;

And a third instruction control unit configured to cancel instructions erroneously issued by branch prediction and start issuing instructions in a correct direction after all instructions before the branch are completed. .

2. A first instruction control unit that issues an instruction including a branch instruction with a first identifier attached thereto and executes speculation by branch prediction,

A second instruction control unit that, when the first branch error is detected, issues an instruction in the correct direction following the instruction issued in error with a second identifier attached thereto;

After the first branch miss is detected and an instruction in the correct direction is issued, if a second branch miss is detected in an earlier old branch instruction, all instructions before the old branch instruction are completed. A third instruction control unit that cancels all subsequent instructions, and then starts issuing instructions in the correct direction;

A processor comprising:

3. A first instruction control unit that issues an instruction including a branch instruction with a first identifier attached thereto and executes speculation by branch prediction,

After the first branch miss is detected and an instruction in the correct direction is issued, if a second branch miss is detected in an earlier older branch instruction, the correct direction is determined by the detection of the first branch miss. A third instruction control unit that starts issuing instructions in the correct direction determined by the detection of the second branch error after canceling the issued instruction that has been determined; and a correct instruction direction that is detected when the second branch error is detected. After the order was issued, the old A fourth instruction control unit that waits until all instructions before the next branch instruction are completed, cancels an instruction that has been erroneously issued by the second branch prediction, and then resumes issuing instructions in the correct direction. ,

A processor comprising:

4. a first instruction control unit that issues an instruction including a branch instruction with a first identifier attached thereto and executes speculation by branch prediction;

After the first branch miss is detected and the instruction in the correct direction is started, if a second branch miss is detected in a new branch instruction in the instruction issued as the correct direction, A processor comprising: a third instruction control unit that waits until all instructions are completed, cancels all subsequent instructions, and then starts issuing instructions in a correct direction.

5. A first instruction control unit that issues an instruction including a branch instruction with a first identifier attached thereto and executes speculation by branch prediction,

After the first branch miss is detected and the instruction is issued in the correct direction, if the second branch miss is detected in a new branch instruction in the instruction issued as the correct direction, the instruction is issued in the correct direction. In the suppressed state, after waiting for all instructions before the old branch instruction in which the first branch miss is detected to complete, cancel the instruction erroneously issued by the old branch instruction, and then cancel the instruction. A third instruction control unit that releases the inhibition and starts issuing instructions in the correct direction;

After the issuance of the instruction in the correct direction due to the detection of the second branch miss, the instruction issued by the detection of the first branch prediction is waited until all instructions before the new branch instruction are completed. A fourth instruction control unit that cancels and then resumes issuing instructions in the correct direction due to the second branch error; A processor comprising:

6. The processor of claims 1 to 5, further comprising:

A rename map that has an address storage area for the reorder buffer used for renaming, and a plurality of valid flag areas corresponding to a plurality of identifiers attached by instruction control, in the entry referenced by the register number used by the instruction. When,

When a register used by an instruction is renamed using the reorder buffer, the address of the reorder buffer used for renaming is stored in the entry of the rename map referenced by the register number, and attached to the instruction. Turns on the valid flag corresponding to the identifier, and when a branch error is detected, turns off the valid flag of the rename map corresponding to the identifier attached to the instruction issued incorrectly, and attaches it to the instruction issued in the correct direction. A renaming processing unit for turning on a valid flag of a rename map corresponding to another identifier to be

A processor for preventing an instruction in a correct direction issued by detection of a branch error from using rename information by an instruction issued by mistake.

7. A first step of issuing an instruction including a branch instruction with a first identifier attached thereto and executing speculation by branch prediction,

A third step of canceling an erroneously issued instruction by branch prediction and starting instruction issue in a correct direction after all instructions before the branch are completed. Control method.

8. A first step of issuing an instruction including a branch instruction with a first identifier attached thereto and executing speculation by branch prediction;

When the first branch error is detected, the instruction in the correct direction follows the instruction issued in error and attaches the second identifier. After the first branch miss is detected and an instruction in the correct direction is issued, if a second branch miss is detected in an earlier old branch instruction, all instructions before the old branch instruction are completed. A third step to cancel all subsequent instructions, and then start issuing instructions in the correct direction;

An instruction control method for a processor, comprising:

9. A first step of issuing an instruction including a branch instruction with a first identifier attached thereto and executing speculation by branch prediction;

After the first branch miss is detected and an instruction in the correct direction is issued, if a second branch miss is detected in an earlier older branch instruction, the correct direction is determined by the detection of the first branch miss. A third step of starting the issuance of the instruction in the correct direction determined by the detection of the second branch error after canceling the instruction issued and determined, and an instruction in the correct direction when the second branch error is detected. After the instruction is issued, the instruction before the old instruction is completed, and the instruction issued in error by the second branch prediction is canceled, and then the instruction is issued in the correct direction. The fourth step to resume,

An instruction control method for a processor, comprising:

10. A first step of issuing an instruction including a branch instruction with a first identifier attached thereto and performing speculative execution by branch prediction;

A second step in which, when the first branch error is detected, an instruction in the correct direction is issued after the instruction issued in error with a second identifier attached thereto;

After the first branch miss is detected and the instruction in the correct direction is started, if a second branch miss is detected in a new branch instruction in the instruction issued as the correct direction, A third step of: waiting for all instructions to be completed, canceling all subsequent instructions, and then starting issuing instructions in the correct direction.

1 1. A first step of issuing an instruction including a branch instruction with a first identifier attached thereto and performing speculative execution by branch prediction;

After the first branch miss is detected and the instruction is issued in the correct direction, if the second branch miss is detected with a new branch instruction in the instruction issued as the correct direction, the instruction is issued in the correct direction. In the suppressed state, wait until all instructions before the old branch instruction in which the first branch miss is detected are completed, and then cancel the instruction erroneously issued by the old branch instruction. A third step of releasing the suppression and starting instruction issue in the correct direction;

After the issuance of the instruction in the correct direction due to the detection of the second branch miss, the instruction issued by the detection of the first branch prediction is waited until all instructions before the new branch instruction are completed. A fourth step of resuming instruction issue in the correct direction due to the second branch error after canceling;

An instruction control method for a processor, comprising:

1 2. In the instruction control method for a processor according to any one of claims 7 to 11,

A line which has an address storage area of a leader buffer used for renaming and a plurality of valid flag areas corresponding to a plurality of identifiers attached by instruction control in the entry referenced by the register number used by the instruction If you have a mumap,

When a register used by an instruction is renamed using a reorder buffer, an address of the reorder buffer used for renaming is stored in an entry of the rename map referred to by a register number, and is attached to the instruction. Turn on the valid flag corresponding to the identifier

When a branch mistake is detected, the valid flag of the rename map corresponding to the identifier attached to the instruction issued erroneously is turned off, and the identifier corresponding to another identifier attached to the instruction issued in the correct direction is turned off. By turning on the valid flag of the rename map, An instruction control method for a processor, comprising: preventing an instruction in a correct direction issued by detection of a branch miss from using rename information of an instruction issued by mistake.

1 3. A first instruction control unit that issues an instruction including an exception generating instruction with a first identifier attached thereto and executes the instruction speculatively without occurrence of an exception;

A second instruction control unit that, when an exception is detected, issues an instruction of an exception handling routine with a second identifier attached after an instruction that is erroneously issued as no exception is generated,

And a third instruction control unit for canceling the exception generation instruction and the instruction generated as no exception generation and starting the instruction generation of the exception generation routine after all instructions before the exception generation instruction are completed. Features processor.

1 4. A first instruction control unit which issues an instruction including an exception generating instruction with a first identifier attached thereto and executes the instruction speculatively without occurrence of an exception;

A second instruction control unit that issues an instruction of an exception handling routine with a second identifier attached after an instruction that is erroneously issued as having no exception when the first exception is detected, and

After the first exception occurrence is detected and the instruction of the exception handling routine in the correct direction is issued, if an earlier old instruction detects the second exception occurrence, the instruction before the old exception occurrence instruction is returned. A third instruction control unit that waits until all of the above are completed, cancels the exception generation instruction and all subsequent instructions, and then starts issuing an instruction in an exception handling routine due to the second exception generation.

A processor comprising:

15. A first instruction control unit that issues an instruction including an exception generating instruction with a first identifier attached thereto and executes the instruction speculatively without occurrence of an exception.

When the first exception is detected, the instruction of the exception handling routine is issued with the second identifier attached following the instruction that was erroneously issued as no exception occurred. 2 Command control unit,

After the first exception occurrence is detected and the instruction of the exception handling routine in the correct direction is issued, if the second exception occurrence is detected by an earlier instruction before that, the first exception occurrence is detected. After canceling the issued instruction of the exception handling routine, a third instruction control unit that starts issuing the instruction of the exception handling routine that is oriented in a correct direction by detecting the occurrence of the second exception,

After the second exception occurrence is detected and the instruction of the exception handling routine is issued, after waiting for all instructions before the old branch instruction to complete, the instruction causing the first exception occurrence and the instruction A fourth instruction control unit that cancels an instruction that is erroneously issued as no exception has occurred, and then resumes issuing instructions of the exception handling routine due to the second exception occurrence;

A processor comprising:

1. A first instruction control unit which issues an instruction including an exception generating instruction with a first identifier attached thereto and executes the instruction speculatively without occurrence of an exception;

A second instruction control unit that issues an instruction of an exception handling routine attached with a second identifier following the instruction that was erroneously issued as no exception when the first exception occurred, and

After starting the issuance of an exception handling routine in the correct direction by detecting the first exception occurrence, and detecting a second exception occurrence in a new instruction among the instructions issued by the exception handling routine, The third instruction that waits for all instructions before the new exception generation instruction to complete, cancels the exception generation instruction and all subsequent instructions, and then starts issuing the exception handling routine instruction when the first exception occurs. Control unit,

An instruction control method, comprising:

1. A first instruction control unit that issues an instruction including an exception generating instruction with a first identifier attached thereto and executes the instruction speculatively without occurrence of an exception;

When the first exception occurred, it was incorrectly issued as no exception A second instruction control unit that issues the instruction of the exception handling routine with the second identifier attached thereto following the instruction;

After starting the issuance of an exception handling routine in the correct direction by detecting the first exception occurrence, and detecting a second exception occurrence in a new instruction among the instructions issued by the exception handling routine, In a state in which the issuance of the instruction of the exception handling routine is suppressed, the system waits for completion of all the instructions before the older exception occurrence instruction in which the first exception occurrence is detected, and then executes the old exception occurrence instruction and the instruction. A third instruction control unit for canceling the instruction erroneously issued as no exception has occurred, releasing the inhibition, and starting to issue an instruction of an exception handling routine which is oriented in a correct direction by the second exception occurrence; and ,

After the instruction of the exception handling routine is issued due to the second exception occurrence, the instruction of the second exception occurrence and the first exception occurrence are waited until all instructions before the new exception occurrence instruction are completed. A fourth instruction control unit that cancels the instruction issued in the exception handling routine of the second instruction, and then resumes issuing the instruction of the exception handling routine due to the occurrence of the second exception;

A processor comprising:

18. A first step of issuing an instruction including an exception generating instruction with a first identifier attached thereto and executing the instruction speculatively without occurrence of an exception;

A third step of canceling the exception generating instruction and the instruction issued as no exception generation and starting the instruction generation of the exception generating routine after all instructions before the exception generating instruction are completed;

An instruction control method for a processor, comprising:

1 9. Attach the first identifier, issue the instruction including the instruction that caused the exception, and execute the instruction speculatively without exception. When detecting the occurrence of the first exception, the instruction of the exception handling routine is issued with the second identifier attached after the instruction that was erroneously issued as no exception occurred, and the first exception is generated. If the second exception is detected in the older instruction after the instruction of the exception handling routine in the correct direction has been issued and the previous instruction is issued, wait until all instructions before the old branch instruction have completed. A third step of canceling the exception generating instruction and all subsequent instructions, and then starting to issue an instruction in an exception handling routine based on the second exception generation;

An instruction control method for a processor, comprising:

20. A first step of issuing an instruction including an exception generating instruction with a first identifier attached thereto and executing the instruction speculatively without occurrence of an exception;

A second step of, after detecting the first exception occurrence, issuing an instruction of an exception handling routine with a second identifier attached thereto following the instruction that was erroneously issued as no exception occurrence;

After the first exception occurrence is detected and the instruction of the exception handling routine in the correct direction is issued, if a second exception occurrence is detected by an earlier fault instruction, the first exception occurrence is detected. A third step of, after canceling the issued instruction of the exception handling routine, starting to issue an instruction of the exception handling routine to be in a correct direction by detecting the occurrence of the second exception;

After the second exception occurrence is detected and the instruction of the exception handling routine is issued, after waiting for all instructions before the old branch instruction to complete, the instruction causing the first exception occurrence and the instruction A fourth step of canceling the instruction erroneously issued as no exception has occurred, and then restarting the issuance of the instruction of the exception handling routine due to the second exception occurrence;

An instruction control method for a processor, comprising:

2 1. Attach the first identifier, issue the instruction including the instruction that caused the exception, and execute the instruction speculatively without exception. A second step of, after detecting the first exception occurrence, issuing an instruction of an exception handling routine attached with a second identifier following the instruction erroneously issued as no exception occurrence,

After starting the issuance of an exception handling routine in the correct direction by detecting the first exception occurrence, and detecting a second exception occurrence in a new instruction among the instructions issued by the exception handling routine, Wait for all instructions before the new exception generation instruction to complete, cancel the exception generation instruction and all subsequent instructions, and then start issuing the exception handling routine for the first exception generation. An instruction control method for a processor, comprising: three steps:

2 2. A first step of issuing an instruction including an exception generating instruction with a first identifier attached thereto and executing the instruction speculatively without occurrence of an exception;

When detecting the occurrence of the first exception, the instruction of the exception handling routine is issued with the second identifier attached after the instruction that was erroneously issued as no exception occurred. When the second exception is detected in a new instruction among the instructions issued by the exception handling routine after the instruction issuance of the exception handling routine in the correct direction is detected and the instruction issuance of the exception handling routine is started. In a state where the first exception occurrence is detected, the instruction before the old exception occurrence instruction in which the first exception occurrence is detected is completed. A third step of canceling the issued instruction, releasing the inhibition, and starting to issue an instruction of an exception handling routine that is in a correct direction due to the occurrence of the second exception;

After the instruction of the exception handling routine is issued due to the occurrence of the second exception, the instruction of the second exception and the first exception are waited until all instructions before the new exception occurrence instruction are completed. A fourth step of canceling the instruction issued in the generated exception handling routine and then restarting the issuance of the instruction in the exception handling routine due to the occurrence of the second exception;

An instruction control method for a processor, comprising: