JP3807740B2 - Processor and instruction control method - Google Patents

Description

The present invention relates to a processor and an instruction control method for executing an instruction at the time of speculation by branch prediction, and more particularly to a processor and an instruction control method for efficiently canceling a subsequent instruction when branch prediction fails.

  Conventionally, in a processor that uses both branch prediction and dynamic pipeline processing, an in-order instruction issue unit that depends on the program order, an out-of-order instruction execution unit that does not depend on the program order, and the program order A dependent in-order instruction determination unit (commit) is provided, and instructions are speculatively executed based on branch prediction. That is, the instruction issuing unit fetches and decodes a plurality of instructions by in-order, and holds the instruction operation (opcode) and operand in the instruction storage queue of the instruction storage unit. The instruction execution unit executes the instruction speculatively out-of-order and obtains a result as soon as all operands are prepared in the instruction storage unit and the arithmetic unit becomes available. The instruction determination unit holds the incomplete instruction in the reorder buffer, and if the branch prediction is correct, the result of the subsequent instruction of the branch is validated and written from the reorder buffer to the register or memory.

  If the branch prediction is missed and a branch miss occurs, all subsequent instructions of the branch are invalidated and removed from the instruction storage unit and the reorder buffer. Here, the reorder buffer is managed by the reorder map assigned by the instruction issuing unit as a substitute for the actual register used in the instruction, and the result of the instruction executed out of order is written to the actual register. Is held only while the instruction determination unit waits. For this reason, when the branch prediction is lost, the valid bit on the map of the reorder buffer allocated to the instruction following the branch is turned off.

FIG. 1 shows processing when a branch miss occurs in a conventional processor. In the speculative execution of an instruction by branch prediction in FIG. 1A, when branch prediction for branch instruction B4 fails and branch miss 200 is detected, as shown in FIG. When all the instructions are completed, after the update of the resource including the reorder buffer is completed, a cancel process 202 is executed to cancel the instructions 5 to 8 that have been executed by mistake, and thereafter, FIG. In this way, the issuance of instructions that become instructions 50 and 51 in the correct direction is started, and the instruction sequence is executed.

  However, in such instruction control, there is a problem that if the instruction before the branch instruction B4 that caused a branch miss is not completed, issuance of a correct instruction sequence cannot be resumed and the processing performance of instruction execution is low. Therefore, in order to improve the processing performance of the processor, instruction control for occurrence of branch miss as shown in FIG. 2 is performed. In this instruction control, as shown in FIG. 2 (A), IDs as identifiers are given as ID = 0, ID = 1, ID = 2 on the boundary of branch instructions B4, B8, When the branch miss 204 of the branch instruction B4 is detected in FIG. 2B, a cancel process 206 for canceling instructions 5 to 11 having ID = 1 and ID = 2 newer than ID = 0 of the branch instruction B4 is performed. After that, as shown in FIG. 2C, the issuance of instructions 50 and 51 in the correct direction is started and the instruction sequence is executed.

  For this reason, even if all the instructions before the branch instruction B4 in which the branch miss 204 is detected are not completed, the execution of the correct instruction sequence can be resumed, and the instruction processing performance can be improved. However, in the instruction control of FIG. 2, if a large number of branch instructions are operated simultaneously, it is necessary to have IDs corresponding to the number of branch instructions, resulting in an increase in hardware amount and complexity. There is a problem that it is not suitable for high speed. In the case of a renamed processor, it is necessary to take a snapshot of the rename information for each branch instruction. Similarly, this increases the amount of hardware and complexity, and is not suitable for increasing the speed of the processor. There is. This problem is explained in detail as follows.

  FIG. 3 is an explanatory diagram of a rename map used in a conventional processor, where there are registers REG0, REG1, REG2, REG3 that can be renamed and reorder buffers ROB0, ROB1, ROB2, ROB3 used for the rename. Will be described as an example. The rename map 210 is a table that indexes the register number REG_AD 212 as entry numbers 0 to 3. If the field 216 of the valid bit field AV is “1”, the register is reorder indicated by the field 214 of the reorder buffer address ROB_AD. Indicates that the buffer ROB is being renamed.

  For example, when the register REG1 is renamed by using the reorder buffer ROB3 when the instruction is issued, “1” is written in the valid flag AV field 216 of the entry “1” of the rename map and the field of the reorder buffer address ROB_AD. Write “3” in 214. When the renaming is completed upon completion of the instruction, the field 216 of the valid flag AV is rewritten to “0” and the reorder buffer ROB3 is released. Further, when it is desired to rename the same register REG1 with another reorder buffer ROB0 before releasing the reorder buffer ROB3, only the field 214 of the rename buffer address ROB_AD in the rename map 210 is rewritten to “0”, for example, The AV field 216 is set to “0” when the instruction that last renamed the register REG1 is completed.

  Therefore, as in the case of instruction control in FIG. 2, when an ID, which is an identifier, is assigned to each instruction sequence with a branch instruction as a boundary, the rename map 210 shown in FIG. There is a problem that the field 214 of ROB_AD must be provided and the field of the valid flag AV in the intermediate state must also be generated. This increases the amount of hardware and makes it more complicated, and speeds up the processor. There is a problem that it is not suitable. The speculative execution of such an instruction has the same problem as the case of a branch miss because the speculatively executed instruction issued as no exception becomes invalid even when an exception occurs during instruction execution. .

An object of the present invention is to provide a processor and an instruction control method capable of promptly resuming instruction issue when speculative execution is erroneous with a small amount of hardware.

  FIG. 1 is a diagram illustrating the principle of the present invention.

(Processor that controls branch prediction)
In the first form of the processor of the present invention, a first instruction control unit that issues a command including a branch command with a first identifier (ID = 0) and speculatively executes it by branch prediction; When detected, the second instruction control unit that issues instructions in the correct direction following the instructions that were issued in error, and after all instructions before the branch are completed, A third instruction control unit that cancels the stored instruction and starts issuing a command in the correct direction following the instruction issued by the second command control unit with a second identifier attached thereto; As described above, the processor of the present invention updates the identifier (ID) attached to the instruction after the branch miss occurs, so that the correct direction can be obtained without waiting for the completion of all instructions before the branch instruction in which the branch miss has occurred. Can be issued, the processing performance of the instruction is improved, and at least two identifiers are required to be attached to the instruction. Thus, the improvement of the processing performance and the reduction of the hardware amount can be achieved at the same time.

In the second form of the processor of the present invention, a first instruction control unit that issues a command including a branch command with a first identifier (ID = 0) and speculatively executes by branch prediction; And a second instruction control unit that issues a second identifier (ID = 1) attached to an instruction in the correct direction after the instruction that has been issued in error when a branch miss is detected. Is the same as the first form, but after the first branch miss is detected and the instruction in the correct direction of the first branch miss is issued, the second branch miss is executed for the old branch instruction before that. A third instruction control unit that waits for all instructions before the old branch instruction to be completed, cancels all subsequent instructions, and starts issuing instructions in the correct direction of the second branch miss. It is provided with. In this way, after issuing an instruction in the correct direction for the first branch miss, if a branch miss occurs for the old branch instruction before that, the program waits for completion of all the instructions before the old branch instruction and is not completed. An instruction in the right direction can be issued after canceling all the instructions. In this case, it is sufficient that at least two identifiers are attached to the instruction, and the amount of hardware can be reduced.

In the third embodiment of the processor of the present invention, a first instruction control unit that issues a command including a branch command with a first identifier (ID = 0) and speculatively executes by branch prediction; A second instruction control unit that issues an instruction in the correct direction with a second identifier (ID = 1) after the instruction that has been issued in error when a branch miss is detected, In the same way as the first form, but in addition to this, after the first branch miss is detected and the instruction in the correct direction of the first branch miss is issued, the second branch in the previous old branch instruction is issued. If a miss is detected, an instruction issued in the correct direction determined by detecting the first branch miss is canceled, and then an instruction issued in the correct direction of the second branch miss determined by detecting the second branch miss is issued. Third instruction controller to start and second branch miss After the instruction in the correct direction is detected and issued, it waits for all instructions before the old branch instruction to complete, cancels the instruction on the second branch miss side, and resumes issuing the instruction in the correct direction And a fourth command control unit.

  Thus, after issuing an instruction in the correct direction for the first branch miss, if a branch miss occurs for an old branch instruction before that, the first branch miss is not waited for completion of all instructions before the old branch instruction. Cancel all uncompleted instructions that were issued in the wrong branch prediction and issue instructions in the correct direction, then wait for completion of instructions before the old branch instruction, and cancel uncompleted instructions that were issued incorrectly Then, it is possible to improve the processing performance by issuing an instruction in the correct direction, and the hardware amount can be reduced because at least two identifiers are attached to the instruction.

According to a fourth aspect of the processor of the present invention, there is provided a first instruction control unit that issues a command including a branch instruction with a first identifier (ID = 0), speculatively executes by branch prediction, and a first branch miss. A point is provided with a second instruction control unit that issues a command in the correct direction with a second identifier (ID = 1) attached after a command that has been issued in error after detection. In addition to this, after the first branch miss is detected and instruction issue in the correct direction of the first branch miss is started, the second branch instruction in the instruction issued as the correct direction When the third branch miss is detected, it waits for all the instructions before the new branch instruction to be completed, cancels all subsequent instructions, and starts issuing instructions in the right direction of the second branch miss . An instruction control unit is provided.

  In this way, after issuing an instruction in the correct direction for the first branch miss, if a branch miss occurs for a new branch instruction in the correct instruction sequence, wait for the completion of all instructions before the new branch instruction. All uncompleted instructions can be canceled and instructions in the correct direction can be issued. In this case as well, at least two identifiers need to be attached to the instructions, and the amount of hardware can be reduced.

According to a fifth aspect of the processor of the present invention, there is provided a first instruction control unit that issues a command including a branch instruction with a first identifier (ID = 0), speculatively executes by branch prediction, and a first branch miss. A first command control unit that issues a command in the right direction with a second identifier (ID = 1) attached after the command that has been erroneously issued when detected is the first point. In addition to this, after a first branch miss is detected and an instruction is issued in the correct direction of the first branch miss , a new branch instruction in the instruction issued as the correct direction is used. If a branch miss of 2 is detected, the instruction issued in the correct direction is suppressed, waits for all the instructions before the old branch instruction in which the first branch miss is detected, and then the old branch instruction Cancel an order that was issued by mistake Et al., A third instruction control unit for starting the right direction instruction issue of the second branch miss to release the suppression after the instruction issue of the right direction by the detection of the second branch miss has been started, a new branch instruction A fourth instruction control unit that waits for all previous instructions to be completed, cancels the instruction on the second branch miss side, and resumes issuing instructions in the correct direction due to the second branch miss It is characterized by that.

  In this way, after issuing instructions in the correct direction for the first branch miss, if a branch miss occurs for a new branch instruction in the instruction sequence in the correct direction, wait for the completion of all instructions before the new branch instruction. It is possible to cancel all unfinished instructions that were issued in error by the first branch mistake and issue instructions in the correct direction, and then wait for completion of instructions before the new branch instruction, Processing performance can be improved by canceling instructions and issuing instructions in the correct direction, and the amount of hardware can be reduced because at least two identifiers need to be attached to the instructions.

  In the processors of the first to fifth embodiments, the address storage area of the reorder buffer used for renaming, and a plurality of items attached by instruction control are added to the entry referenced by the register number used by the instruction. Rename map with multiple valid flag areas corresponding to identifiers, and when using a reorder buffer to rename a register used by an instruction, it is used for a rename map entry that is referenced by a register number Stores the address of the reorder buffer to be used, turns on the valid flag corresponding to the identifier attached to the instruction, and renames map corresponding to the identifier attached to the instruction that was issued erroneously when a branch miss was detected The renaming map corresponding to another identifier attached to the instruction issued in the correct direction is turned off. And a renaming processing unit that turns on the valid flag of the instruction, thereby preventing an instruction in the correct direction issued by detecting a branch miss from using renaming information by an instruction that has been issued in error. And

(Instruction control method for branch prediction)
The first form of the processor instruction control method according to the present invention includes a first step of issuing an instruction including a branch instruction with a first identifier attached, speculatively executing by branch prediction, and an error when a branch miss is detected. The second step of issuing an instruction in the correct direction with the second identifier attached after the instruction that has been issued in this way, and after all the instructions before the branch are completed, the instruction is erroneously issued by branch prediction. And a third step of starting the issuance of a command in the correct direction following the command issued in the second step with the second identifier .

In the second form of the processor instruction control method according to the present invention, a first step of issuing an instruction including a branch instruction with a first identifier and speculatively executing by branch prediction, and detecting a first branch miss And a second step of issuing an instruction in the correct direction with the second identifier attached after the instruction that has been issued in error, and the first branch miss is detected and the first branch error is correct. After a direction instruction is issued, if a second branch miss is detected with an older old branch instruction, wait for all instructions before the old branch instruction to complete and cancel all subsequent instructions. To start issuing instructions in the right direction of the second branch miss ,
It is provided with.

In the third form of the processor instruction control method according to the present invention, a first step of issuing an instruction including a branch instruction with a first identifier and speculatively executing by branch prediction, and detecting a first branch miss And a second step of issuing an instruction in the correct direction with the second identifier attached after the instruction that has been issued in error, and the first branch miss is detected and the first branch error is correct. When a second branch miss is detected in the old branch instruction before the direction instruction is issued, the second instruction is canceled after the issued instruction is canceled by determining the correct direction by detecting the first branch miss. A third step for starting the issuance of instructions in the correct direction of the second branch miss determined by the detection of the branch miss of the first branch instruction, and after the second branch miss is detected and the instruction in the correct direction is issued, before the old branch instruction All the orders Waiting Ryosuru of, after canceling the instruction had issued incorrectly by the second branch prediction, and the fourth step to resume the correct direction of the instruction issue,
It is provided with.

According to a fourth aspect of the processor instruction control method of the present invention, a first step of issuing an instruction including a branch instruction with a first identifier attached, speculatively executing by branch prediction, and detecting a first branch miss And a second step of issuing an instruction in the correct direction with the second identifier attached after the instruction that has been issued in error, and the first branch miss is detected and the first branch error is correct. If the second branch miss is detected with a new branch instruction in the instruction issued as the correct direction after starting the instruction issue in the direction, all subsequent instructions wait for the instructions before the new branch instruction to be completed. And a third step of starting the issuance of instructions in the correct direction of the second branch miss .

According to a fifth embodiment of the processor instruction control method of the present invention, a first step of issuing an instruction including a branch instruction with a first identifier and speculative execution by branch prediction, and detecting a first branch miss And a second step of issuing an instruction in the correct direction with the second identifier attached after the instruction that has been issued in error, and the first branch miss is detected and the first branch error is correct. When the second branch miss is detected with a new branch instruction in the instruction issued as the correct direction after starting the instruction issue in the direction, the first branch miss is detected with the instruction issue in the correct direction being suppressed. Wait for all instructions before the old branch instruction to complete, cancel the instruction that was issued by the old branch instruction by mistake, cancel the suppression, and the instruction in the correct direction for the second branch miss Start issuing Issued by detection of the first branch prediction after waiting for all instructions before the new branch instruction to be completed after the third step and instruction issue in the right direction by the detection of the second branch miss were started. And a fourth step of resuming instruction issuance in the correct direction due to the second branch miss after canceling the instruction.

  Further, in the processor instruction control method according to the first to fifth embodiments, an address storage area of a reorder buffer used for renaming and an instruction control are attached to an entry referred to by a register number used by the instruction. When a rename map having a plurality of valid flag areas corresponding to a plurality of identifiers is provided, when the register used by the instruction is renamed using the reorder buffer, the rename map referenced by the register number is used. In the entry, the address of the reorder buffer used for renaming is stored, and the valid flag corresponding to the identifier attached to the instruction is turned on. When a branch miss is detected, the instruction that has been issued erroneously is detected. Turn off the validity flag of the rename map corresponding to the attached identifier and attach it to the instruction issued in the correct direction. By turning on the validity flag of the rename map corresponding to another identifier, it is possible to prevent the use of rename information by an instruction in which a correct direction instruction issued by detecting a branch miss is erroneously issued It is characterized by.

(Processor that handles exception occurrence)
In addition to the speculative execution of instructions by branch prediction, the processor of the present invention can be applied in the same way as the case of a branch miss when canceling an instruction that has been speculatively executed without an exception occurrence by the occurrence of an exception. The following first to fifth forms are also adopted for occurrence of exceptions corresponding to the detection.

A first form of a processor for processing an exception occurrence according to the present invention is a first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached, and speculatively executes the instruction as no exception occurs; A second instruction control unit for issuing an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when an exception occurrence is detected, and an exception generation instruction After all previous instructions are completed, cancel the instruction that has been issued as an exception occurrence instruction and no exception occurrence, and attach the second identifier to the exception processing routine instruction issued following the instruction issued by the second instruction control unit And a third command control unit that starts in this manner.

A second form of processing exception occurrence of the processor of the present invention is a first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached, and speculatively executes the instruction as no exception occurs;
A second instruction control unit that issues an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
After the first exception occurrence is detected and the exception handling routine instruction in the correct direction is issued, when the second exception occurrence is detected in the old instruction before that, all the instructions before the old branch instruction are completed. And a third instruction control unit for canceling the exception generation instruction and all subsequent instructions after waiting for this and then starting issuing an instruction of the exception processing routine by the second exception generation.

A third form of processing exception occurrence of the processor of the present invention is a first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached, and executes the instruction speculatively without occurrence of an exception; A second instruction control unit that issues an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
After the first exception occurrence is detected and the exception handling routine instruction is issued in the correct direction, when the second exception occurrence is detected in the old instruction before it, it is issued due to the detection of the first exception occurrence. A third instruction control unit that starts issuing an instruction of the exception handling routine that is in the correct direction upon detection of the occurrence of the second exception after canceling the instruction of the exception handling routine; and the exception handling routine when the second exception occurrence is detected After the instruction is issued, wait until all instructions before the old branch instruction are completed, and cancel the instruction that caused the first exception and the instruction that was erroneously issued as no exception occurred by this instruction. And a fourth instruction control unit for restarting the issuance of an exception processing routine instruction upon occurrence of the second exception.

A fourth form of processing exception occurrence of the processor of the present invention is a first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached, and speculatively executes the instruction as no exception occurs; A second instruction control unit that issues an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
When the second exception occurrence is detected by a new instruction in the instruction issued by the exception processing routine after the first exception occurrence is detected and instruction issue of the exception handling routine in the correct direction is started, a new exception occurrence instruction is detected. A third instruction control unit that waits for completion of all previous instructions, cancels the exception generation instruction and all subsequent instructions, and then starts issuing an exception processing routine instruction upon occurrence of the first exception; It is characterized by that.

A fifth form of processing a processor exception occurrence according to the present invention is a first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached, and executes the instruction speculatively without occurrence of an exception;
A second instruction control unit that issues an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
If the second exception occurrence is detected by a new instruction in the instruction issued by the exception processing routine after the first exception occurrence is detected and the instruction issuing of the exception handling routine in the correct direction is started, the exception processing routine With the instruction issue suppressed, wait until all instructions before the old exception generation instruction where the first exception has been detected are completed, and then issue the old exception generation instruction and this instruction as no exception occurrence. A third instruction control unit that cancels the instruction that has been canceled and then releases the suppression and starts issuing an exception handling routine that is in the correct direction upon occurrence of the second exception; and an exception handling routine upon occurrence of the second exception After the first instruction is issued, the second exception generation instruction and the first exception generation exception processing routine wait for the completion of all instructions before the new exception generation instruction. After canceling the line instruction, characterized by comprising a fourth instruction control unit resumes the instruction issue of handling routine according to the second exception.

(Instruction control method to handle exception occurrence)
The first form of processing the exception occurrence of the instruction control method of the processor according to the present invention can be applied to the case of canceling the speculatively executed instruction due to the exception occurrence in the same manner as in the case of a branch miss. In response to the exception occurrence, the following first to fifth forms are also adopted.

A first form of an instruction control method for a processor according to the present invention for processing an exception occurrence is a first step of issuing an instruction including an exception occurrence instruction with a first identifier attached and executing the instruction speculatively with no exception occurrence A second step of issuing an exception processing routine instruction with a second identifier attached after the instruction that was erroneously issued as no exception occurrence when an exception occurrence is detected, and an exception occurrence instruction After completing all previous instructions, cancel the instruction issued as an exception occurrence instruction and no exception occurrence following the instruction issued in the second step, and attach the second identifier to issue the exception processing routine instruction And a third step of starting.

According to a second aspect of the instruction control method for processing an exception occurrence of a processor according to the present invention, a first step of issuing an instruction including an exception occurrence instruction with a first identifier and executing the instruction speculatively without occurrence of an exception. A second step of issuing an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception occurrence when an exception occurrence is detected; after the exception is issued instruction exception handling routines that right direction is detected, if at earlier older instruction detects a second exception, for completion old Aya Ordinance previous instruction are all A third step of waiting, canceling the exception generation instruction and all subsequent instructions, and starting issuing an instruction of the exception processing routine by the second exception generation.

  According to a third aspect of the instruction control method for processing an exception occurrence of a processor according to the present invention, a first step of issuing an instruction including an exception occurrence instruction with a first identifier and executing the instruction speculatively without occurrence of an exception. A second step of issuing an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception occurrence when an exception occurrence is detected; Exception processing routine issued by detecting the occurrence of the first exception when the second exception occurrence is detected by the old instruction before the exception processing routine instruction in the correct direction is issued after the occurrence of the exception is detected The third step of starting issue of an exception processing routine that is in the correct direction upon detection of the occurrence of the second exception, and the exception processing routine when the second exception occurrence is detected. After the chin instruction is issued, the instruction before the old branch instruction is completed and the instruction that caused the first exception and the instruction that was erroneously issued as no exception occurred by this instruction And a fourth step of restarting the issuance of an exception processing routine instruction due to the occurrence of the second exception.

  According to a fourth aspect of the instruction control method for processing an exception occurrence of a processor according to the present invention, a first step of issuing an instruction including an exception occurrence instruction with a first identifier attached and executing the instruction speculatively without occurrence of an exception. And a second step of issuing an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as no exception occurrence when the first exception occurrence is detected; When the second exception occurrence is detected by a new instruction in the instruction issued by the exception processing routine after the first exception occurrence is detected and instruction issue of the exception handling routine in the correct direction is started, a new exception occurrence instruction is detected. Wait until all previous instructions are completed, cancel the exception generation instruction and all subsequent instructions, and then start issuing the exception processing routine instruction when the first exception occurs Tsu and-flops, and further comprising a.

According to a fifth aspect of the instruction control method for processing the occurrence of an exception of a processor according to the present invention, a first step of issuing an instruction including an exception occurrence instruction with a first identifier attached and executing the instruction speculatively without occurrence of an exception. A second step of issuing an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception occurrence when an exception occurrence is detected; If the second exception occurrence is detected by a new instruction in the instruction issued by the exception processing routine after the exception occurrence is detected and the instruction is issued in the correct direction, the exception processing routine is issued. In the suppressed state, wait for the completion of all instructions before the older exception generation instruction where the first exception occurrence is detected. The third step of canceling the instruction that has been issued in this way, releasing the suppression, and starting issuing instructions of the exception handling routine that takes the correct direction when the second exception occurs, and the exception due to the second exception occurring After the instruction of the processing routine is issued, the second exception generating instruction and the instruction issued by the exception generating routine due to the first exception generation are canceled after all instructions before the new exception generating instruction are completed. And a fourth step of resuming the issuance of an exception processing routine instruction upon occurrence of a second exception.

  As described above, according to the present invention, as described above, according to the present invention, a speculative error is issued when a branch miss is detected during speculative instruction execution based on branch prediction. The processing that cancels the failure instruction and restarts the issuance of the instruction in the right direction can be realized on high-speed and few hardware resources, and greatly contributes to the performance improvement especially when the operating frequency of the processor is increased. Can do.

Similarly, when an instruction exception occurs, cancellation of a speculative failure instruction that has been issued as no exception has occurred and instruction issuance by an exception handling routine can be realized at high speed and with a small amount of hardware, Also in this case, it is possible to greatly contribute to the performance improvement in the processor whose operating frequency is increased.

  FIG. 4 is a block diagram of a functional configuration of a processor to which the instruction control of the present invention is applied. 4, the processor 10 includes a branch prediction unit 12, an instruction issue unit 14, an instruction storage unit 16, an instruction execution unit 18, an instruction determination unit 20, a register 22, and a renaming processing unit 24. The instruction storage unit 16 is provided with instruction storage queues 26-1 to 26-4 called reservation stations. The instruction execution unit 18 is provided with functional processing units such as a branch processing unit 28, an integer arithmetic unit 30, a floating point arithmetic unit 32, and a load / store processing unit 34. Further, the renaming processing unit 24 is provided with a reorder buffer 36 and a rename map 38.

  Each processing unit of the processor 10 operates under the control of the instruction control unit 40. In the present invention, the instruction control unit 40 includes a branch prediction instruction control unit 42 and an exception generation instruction control unit 44 unique to the present invention in addition to normal instruction control. The processor 10 in the embodiment of FIG. 4 performs speculative execution of instructions by using so-called dynamic scheduling and branch prediction together. First, the instruction issuing unit 14 fetches, for example, four instructions from the instruction cache and decodes them. The branch prediction unit 12 includes a branch history table for branch prediction, and performs speculative execution in the predicted branch direction.

  The instruction issued in-order from the instruction issuing unit 14 sends each instruction and its operand to the instruction storage unit 16 corresponding to the function processing unit in the instruction execution unit 18. At the same time, the instruction issuing unit 14 registers the instruction in the reorder buffer 36. The instruction sent to the instruction storage unit 16 is executed out-of-order as soon as the corresponding processing unit provided in the instruction execution unit 18 becomes available, and the result is stored in the reorder buffer assigned to the instruction. Stored. The instruction determination unit 20 holds all incomplete instructions in the reorder buffer 36, and upon receiving a determination result as to whether or not the branch processing unit 28 of the instruction execution unit 18 establishes a branch, the instruction determination unit 20 determines the instruction based on the determination result. The unit 20 determines processing of an incomplete instruction. That is, when the branch prediction is correct, the result of the subsequent instruction with respect to the branch instruction is validated, and is written in the register 22 or a memory (not shown) in order according to the order of the program.

  When the branch prediction is missed and a branch miss occurs, all the results of the subsequent instruction with respect to the branch instruction are invalidated and canceled from the instruction storage unit 16 and the reorder buffer 36. In this way, when a branch miss is detected for a speculatively executed instruction by branch prediction, the branch prediction instruction control unit 42 according to the present invention provided in the instruction control unit 40 issues in a wrong direction due to a branch miss. The instruction issuance process in the correct direction is efficiently performed based on the cancellation of the executed instruction and the detection of the branch miss.

  FIG. 5 is an explanatory diagram of the rename map 38 provided in the renaming processing unit 24 of the processor 10 of FIG. In the branch prediction instruction control of the present invention, at least two IDs of 0 and 1 may be used as IDs which are identifiers attached to instructions.

  Corresponding to the two IDs attached to this instruction, the rename map 38 adds to the reorder buffer address field (ROB_AD) 46 for each of the entries 0, 1, 2, 3 shown on the right side designated by the register number 50 of the instruction. , A valid flag field (AV0) 48-0 for storing a valid flag AV0 corresponding to ID = 0 and a valid flag field (AV1) 48-1 for storing a valid flag AV1 corresponding to ID = 1 are provided. In the rename map 38, the address of the reorder buffer to be renamed, for example, “00” is written in the entry designated by the register number 50, for example, in the case of the register number RG1, the reorder buffer address field 46 of the entry “0”. At this time, if the ID attached to the instruction is ID = 0, the flag of the corresponding field of the valid flag field 48-0 is set to “1”.

  When the reorder buffer is released upon completion of an instruction or when an instruction is invalidated due to detection of a branch miss, for example, the valid flag field 48-0 with ID = 0, which is “1”, may be set to “0”. .

  FIG. 6 is a circuit diagram as hardware for generating a cancel signal for canceling the valid flag field to “0” in accordance with the ID given to the instruction targeting the rename map 38 of FIG. FIG. 6A shows a circuit corresponding to two IDs = 0 and 1 in the rename map 38 of the present invention shown in FIG. On the other hand, FIG. 6B shows a hardware circuit in the case of using eight ID = 0 to 7 in the conventional instruction control shown in FIG. In the circuit used in the present invention of FIG. 6A, when a cancel signal is generated, 1-bit ID data provided in the ID field of the instruction is set in the latch 52, and ID = 0. For example, the output of the inverter 54 becomes 1, and an output 1 is generated at the input timing due to the completion or invalidation of the instruction with ID = 0 for the AND gate 56-0, which is output from the OR gate 58 as a cancel signal.

  Also, when ID = 1 in the ID field of the instruction is held in the latch 52, the output of the buffer 55 becomes 1, and a signal input accompanying the completion or invalidation of the instruction with ID = 1 for the AND gate 56-1. The cancel signal is output via the OR gate 58 at the timing of receiving the signal. On the other hand, in the circuit used in the conventional instruction control of FIG. 6 (B), 8 IDs = 0 to 7, the output line from the latch 60 is a 3-bit line, and the latch 60 holds the output line. A decoder 62 is provided for dividing the 3-bit information in the ID field of the issued instruction into 8 types of IDs, and the output from the decoder 62 is 8 signal lines.

  Further, following the decoder 62, AND gates 64-0 to 64-7 corresponding to eight ID = 0 to 7 are provided, and these outputs are combined by an OR gate 66 to extract a cancel signal. As apparent from the comparison between the case of using the two IDs of the present invention in FIG. 6 (A) and the case of using the conventional eight IDs of FIG. 6 (B), the number of IDs attached to the instruction is increased. It can be seen that the circuit scale for outputting the cancel signal increases as the number of times increases.

  On the other hand, in the present invention, as shown in FIG. 6A, basically, only two IDs need be used. Therefore, it is necessary for instruction completion or invalid instruction due to branch miss. It can be seen that the hardware amount of the cancel signal can be made sufficiently small.

  FIG. 7 is a block diagram of a functional configuration of the first mode branch prediction instruction control unit 42-1 serving as the first embodiment of the branch prediction instruction control unit 42 provided in the processor 10 of FIG. 4. The first mode branch prediction instruction control unit 42-1 includes a first instruction control unit 68, a second instruction control unit 70, and a third instruction control unit 72-1.

  FIG. 8 shows an instruction control operation by the first mode branch prediction instruction control unit 42-1 of FIG. 7, and the control operation of FIG. 7 will be described with reference to this. First, the first instruction control unit 68 issues instructions 1 to 11 including branch instructions B4 and B8 with ID = 0 as the first identifier as shown in FIG. For B4, instructions 5 to 11 are issued in the direction determined by the branch prediction and executed speculatively. When a branch miss 80 is detected for the branch instruction B4 by speculative execution of an instruction based on such branch prediction, the second instruction control unit 70 in FIG. As in 8 (B), the instructions 50 and 51 in the correct direction are issued with another ID = 1 as the second identifier following the instructions 5 to 11 that have been issued by mistake.

  Subsequently, after the third instruction control unit 72-1 in FIG. 7 recognizes that all the instructions 1 to B4 before the branch are completed as shown in FIG. 8C, the third instruction control unit 72-1 makes an error by branch prediction of the branch instruction B4. The cancel process 84 is executed for the instructions 5 to 11 that have been issued in this manner, and then the instruction issue following the instructions 50 and 51 in the correct direction is started. In the case of the cancel processing 84 of the instruction 5 to the instruction 11 that have been issued by mistake, the ID = 0 and the instruction resource attached to the instruction to be canceled are cancelled. Specifically, the ID field of the instruction canceled by the circuit of FIG. 6A is set in the latch 52 to generate a cancel signal, and the cancel signal is held in the instruction storage unit 16 of the processor 10 of FIG. And canceling the erroneously issued instructions 5 to 11 and setting all entries in the valid flag field 48-0 corresponding to ID = 0 in the rename map 38 of FIG. The reorder buffer 36 used as the instruction resource is released.

  As described above, in the control operation by the first mode branch prediction instruction control unit of the present invention, a new ID is assigned to the instruction in the correct direction issued after the branch miss is detected. It is only necessary to use two types of IDs for instruction cancellation and instruction issuance in the correct direction, and the amount of hardware associated with the use of IDs can be minimized.

  FIG. 9 is a timing chart corresponding to the instruction control operation of FIG. 8, in which the issued commands are arranged in the vertical direction, and the elapsed time is shown in the horizontal direction. In FIG. 9, when a branch miss 80 is detected at time t1 for the branch instruction B4, as shown in FIG. 8B, at the timing of time t2 after the branch instruction B4 has been issued and finished. With ID = 1, issuing instructions 50 and 51 in the correct direction is started. After that, at time t3 after all the instructions up to branch instruction B4 are completed at time t3, instructions 5 to 11 that have been issued in error are canceled.

  FIG. 10 is a flowchart of instruction control by the first mode branch prediction instruction control unit 42-1 of FIG. First, in step S1, an instruction is issued with the same ID, and when a branch error occurs for a branch instruction that has been issued and completed in step S2, a different direction is assigned in step S3 with the correct direction. Issue an order. Subsequently, in step S4, it is monitored whether or not all instructions before the branch miss are completed. When all the instructions are completed, the speculative failure instruction that has been erroneously issued due to the branch miss in step S5 and its resources including the reorder buffer. In step S6, issuance of instructions in the correct direction is resumed.

  FIG. 11 is a block diagram of a second mode branch prediction instruction control unit 42-2 which is a second embodiment of the branch prediction instruction control unit provided in the processor 10 of FIG. An instruction control unit 70 and a third instruction control unit 72-2 are provided. Among these, the first instruction control unit 68 and the second instruction control unit 70 are the same as the first mode branch prediction instruction control unit 42-1 of FIG. 7, but the third instruction control unit 72-2 has a branch. While issuing an instruction in the correct direction due to a miss, instruction control is processed when a branch miss occurs with an older branch instruction.

  FIG. 12 is an explanatory diagram of a control operation by the second mode branch prediction instruction control unit 42-2 of FIG. First, as shown in FIG. 12A, the first instruction control unit 68 issues an instruction including branch instructions B2, B4, and B8 with ID = 0, and the branch instructions B2, B4, and B8 are issued. , Each instruction is speculatively executed by branch prediction. In this state, it is assumed that a branch miss 80 is detected as the branch instruction B4 is executed out of order.

  In response to the detection of the branch miss 80, the second instruction control unit 70 sends instructions 50 and 51 in the correct direction following the instructions 5 to 11 which have been issued in error, as shown in FIG. Issue another ID = 1. Control operations by the first command control unit 68 and the second command control unit 70 are the same as those already described with reference to FIGS. Next, as shown in FIG. 12C, if a branch miss 82 is detected as a result of out-of-order execution of a branch instruction B2 older than the branch instruction B4 in which the branch miss 80 is detected, the third instruction control unit 72 is detected. -2 waits for the completion of all instructions 1 and B2 before the old branch instruction B2, as shown in FIG. 12D, after the branch miss 82 is detected, and cancels all subsequent instructions 3 to 51. Cancel processing 86 is performed.

  In this cancel process 86, ID = 0 and resources are also cancelled. Then, as shown in FIG. 12E, after the cancel processing 86 for the erroneously issued instruction is completed, the issuance of the instructions 60, 61, 62,. To do. In such a control operation of the second mode branch prediction instruction control unit 42-2, it is not necessary to attach an ID for each branch instruction as in the conventional example of FIG. 2, and it is correct when a branch miss is detected. Since it is only necessary to attach another ID to the instruction generated in the direction, only two IDs are necessary, and the amount of hardware that generates a cancel signal as shown in FIG. 6A can be minimized.

  FIG. 13 is a timing chart of instruction control corresponding to FIG. In FIG. 13, when a branch miss 80 is detected along with the execution of the branch instruction B4 at time t1, instructions 50 and 51 in the correct direction are issued with different ID = 1 from time t2. Thereafter, when a branch miss 82 associated with the execution of the branch instruction B2 older than the branch instruction B4 is detected at time t3, the erroneously issued instruction 3 to instruction 51 at the timing after the completion of the branch instruction B2 at time t4. .. Are cancelled, and at the subsequent time t5, issuance of instructions 60, 61,... In the correct direction is started.

  FIG. 14 is a flowchart of instruction control by the second mode branch prediction instruction control unit 42-2 of FIG. First, in step S1, an instruction is issued with the same ID, and if a branch miss occurs in accordance with the execution of the branch instruction for which branch prediction is performed in step S2, another ID is assigned in step S3 and the correct direction is set. Issue an instruction. Thereafter, when a branch miss occurs for a branch instruction older than the branch instruction that caused the first branch miss in step S4, it is checked in step S5 whether all previous branch instructions of the old branch miss have been completed.

  When all the instructions before the branch instruction of the old branch miss are completed, after canceling all the speculative failure instructions and the resources including the reorder buffer that were erroneously issued due to the branch miss in step S6, the correct direction is obtained in step S7. Start issuing instructions.

  FIG. 15 is a block diagram of a third mode branch prediction instruction control unit 42-3 in the branch prediction instruction control unit 42 of FIG. 4. In this embodiment, the first instruction control unit 68, the second instruction control, and the like. Unit 70, a third instruction control unit 72-3, and a fourth instruction control unit 74-3. Among these, the first instruction control unit 68 and the second instruction control unit 70 are the same as the first mode branch prediction instruction control unit 42-1 of FIG. Further, the third instruction control unit 72-3 and the fourth instruction control unit 74-3 are similar to the third instruction control unit 72-2 of the second mode branch prediction instruction control unit 42-2 of FIG. Instruction control is performed when a branch miss is detected for an old branch instruction after the detection of.

  FIG. 16 is an explanatory diagram of the control operation of the third mode branch prediction instruction control unit 42-3 of FIG. 16A, 16B, and 16C are the same as those of the second mode branch prediction instruction control unit 42-2 in FIG. That is, when a branch miss 80 is detected as a result of execution of the branch instruction B4 in FIG. 16A, as shown in FIG. Direction commands 50 and 51 are issued with another ID = 1.

  Thereafter, as shown in FIG. 16C, assuming that a branch miss 82 is detected along with the execution of a branch instruction B2 older than the branch instruction B4 that detected the branch miss 80, the third instruction control unit 72-3 in FIG. As shown in FIG. 16D, after cancel processing 88 for canceling the issued instructions 50 and 51 determined to be in the correct direction by detecting the first branch miss 80 as shown in FIG. 16D, the branch is executed as shown in FIG. Issue of instructions 60 and 61 in the correct direction determined by detection of the miss 82 is started. Subsequently, the fourth instruction control unit 74-3 in FIG. 15 waits for all of the instruction sequences 1 and B2 before the old branch instruction sequence B2 to be completed as shown in FIG. After executing the cancel process 90 for canceling the instructions 3 to 11 which have been issued by mistake, the instruction issue following the instructions 60 and 61 issued in the correct direction is resumed.

  Of course, in the cancellation process 90, ID = 0 and the asset are canceled simultaneously with the cancellation of the command. When the control operation by the third mode branch prediction instruction control unit 42-3 in FIG. 16 is compared with the control operation by the second mode branch prediction instruction control unit 42-2 in FIG. However, in the case of FIG. 16, when the second branch miss 82 is detected as shown in FIG. 1616 (D), it is detected first. The instruction 50, 51 issued in the correct direction is executed by the branch error 80, and then the instructions 60, 61 in the correct direction are issued to the branch error 82 as shown in FIG. Compared with FIG. 12, the timing of issuing instructions in the correct direction due to the second branch miss 82 is faster, and the performance of instruction processing can be improved accordingly.

  FIG. 17 is a timing chart corresponding to the command control of FIG. In FIG. 17, when a branch miss 80 is detected at the time t1 as the branch instruction B4 is executed, instructions 50 and 51 in the correct direction are issued with different ID = 1 at the subsequent time t2. To do. Subsequently, when a branch miss 82 is detected along with the execution of the branch instruction B2 older than the branch instruction B4 at time t3, the instructions 50 and 51 issued in the correct direction due to the branch miss 80 are canceled at the subsequent time t4. At t5, issue of instructions 60 and 61 in the correct direction for the branch miss 82 is started.

  When comparing the timing chart of FIG. 1717 with respect to the case where the two branch misses 80 and 82 in FIG. 13 are detected, the issue timing of the instructions 60 and 61 in the correct direction to be finally issued is as shown in FIG. Is faster, and the processing performance of instructions is higher.

  FIG. 18 is a flowchart of instruction control of the third mode branch prediction instruction control unit 42-3 of FIG. In FIG. 18, first, an instruction is issued with the same ID in step S1, and when the occurrence of a branch miss is determined along with the execution of the branch instruction in the instruction issued in step S2, another step is executed in step S3. Issue an instruction in the correct direction with an ID. Subsequently, in step S4, it is checked whether or not a branch miss occurs due to the execution of a branch instruction older than the branch instruction that caused the first branch miss. If an old branch miss occurs, the first branch miss is detected in step S5. Cancel resources including speculative failure instructions and reorder buffers issued in the correct direction. Subsequently, in step S6, an instruction in the correct direction for the branch miss that has occurred for the old branch instruction is issued with the same ID as in step S3.

  Subsequently, in step S7, it is determined whether or not all instructions before the old branch miss have been completed. When all the instructions are completed, the speculative failure instruction and its resources that have been erroneously issued due to the branch miss are canceled in step S8. It will be.

  FIG. 19 is a block diagram of a fourth mode branch prediction instruction control unit 42-4 serving as a fourth embodiment of the branch prediction instruction control unit 42 provided in the processor 10 of FIG. In this embodiment, a first instruction control unit 68, a second instruction control unit 70, and a third instruction control unit 72-4 are provided. The first instruction control unit 68 and the second instruction control unit 70 are shown in FIG. 7 is the same as the first embodiment. On the other hand, the third instruction control unit 72-4 detects a new branch instruction in the instruction sequence issued in the correct direction for the branch miss after the first branch miss is detected in the speculative instruction execution by the branch prediction. Instruction control is performed when a second branch miss is detected.

  FIG. 20 is an explanatory diagram of the control operation of the fourth mode branch prediction instruction control unit 42-4 of FIG. In FIG. 20A, an instruction including branch instructions B2, B4, and B8 is issued by the first instruction control unit 68, and the instruction is speculatively executed by branch prediction for the branch instruction. When a branch miss 80 is detected as a result of execution by an order, the instruction in the correct direction follows the instruction 5 to the instruction 11 that are erroneously issued by the second instruction control unit 70 as shown in FIG. Instructions 50 and 51 are issued with another ID = 1. Next, as shown in FIG. 20C, when a branch miss 92 is detected as a result of execution of the branch instruction B52 included in the instructions 50 to 53 issued with ID = 1 in the correct direction, the third instruction control is performed. As shown in FIG. 20D, the unit 72-4 waits for the completion of all instructions before the branch instruction B52 in which the branch miss 92 is detected, and cancels all subsequent instructions 52 and 53. After that, as shown in FIG. 20 (E), issuance of instructions 60, 61, 62.

  FIG. 21 is a timing chart corresponding to the command control of FIG. In FIG. 21, when a branch miss 80 is detected along with the execution of the branch instruction B4 at time t1, issue of instructions 50 to 53 in the correct direction is started with ID = 1 at time t2. Thereafter, when a branch miss 90 is detected with the issuance of the branch instruction 52B in the instructions issued in the correct direction at time t3, all the instructions before the branch instruction B52 in which the branch miss 92 is detected are completed at time t4. And at the time t5 after completion, issuance of instructions 60, 61, 62 in the correct direction is started by the branch miss 92.

  FIG. 22 is a flowchart of instruction control of the fourth mode branch prediction instruction control unit 42-4 of FIG. In FIG. 22, first, an instruction is issued with the same ID in step S1, and when a branch miss occurrence is detected in step S2 with execution of the branch instruction in the issued instruction, another ID is detected in step S3. The instruction in the correct direction is issued after the instruction that has been issued by mistake. Subsequently, when the occurrence of a branch miss is determined in response to the execution of the branch instruction in the instruction issued in the correct direction with respect to the branch miss detected in step S2 in step S4, a branch of a new branch miss is determined in step S5. It is checked whether all instructions before the instruction are completed.

  If it is determined that the instruction has been completed, all speculative failure instructions and resources that have been erroneously issued due to the second branch miss are canceled in step S6, and then instruction issue in the correct direction is started in step S7.

  FIG. 23 is a block diagram of a fifth mode branch prediction instruction control unit 42-5, which is a fifth embodiment of the branch instruction prediction control unit 42 provided in the processor 10 of FIG. In this embodiment, the first instruction control unit 68, the second instruction control unit 70, the third instruction control unit 72-5, and the fourth instruction control unit 74-5 are provided. The second command control unit 70 is the same as that of the first embodiment of FIG. On the other hand, the third instruction control unit 72-5 and the fourth instruction control unit 74-5, after detecting the branch prediction for the first time, as in the case of the third mode branch prediction instruction control unit 42-3 in FIG. Instruction control is performed when a second branch miss is detected in an instruction issued in the direction.

  FIG. 24 shows the control operation of the fifth mode branch prediction instruction control unit 42-5 of FIG. FIG. 24A shows a case where a branch miss 80 is detected in the instruction including the branch instructions B2, B4, B8 issued by the first instruction control unit 68 as the branch instruction B4 is executed. Then, as shown in FIG. 24B, the instructions 50 and 51 in the correct direction are issued with different ID = 1 following the instructions 5 to 11 which have been issued by mistake. Next, as shown in FIG. 24C, when the branch miss 92 is detected in accordance with the execution of the branch instruction B52 among the instructions 50 to 53 issued in the correct direction, the third instruction control unit 72-5 in FIG. Based on the detection of the branch miss 92, the issuance of instructions in the correct direction (instructions 60, 61, 62. After executing the cancel process 96 for canceling the wait for the completion of the instructions 1 to B4, the instructions 60, 61, 62... Are issued in the correct direction due to the branch error 92 as shown in FIG. Start.

  Subsequently, the fourth instruction control unit 74-5 in FIG. 23 waits for all instructions before the new branch instruction B52 to be completed as shown in FIG. , 53 is cancelled, then the instruction issue following the instructions 60, 61, 62 in the correct direction due to the branch miss 92 is resumed. When comparing the instruction control in the fifth embodiment of FIG. 24 and the instruction control when the same branch mistakes 80 and 92 in the fourth embodiment of FIG. 20 are detected, there is a comparison with the fifth embodiment of FIG. In FIG. 24D, when all instructions before branch instruction B4 in which old branch miss 80 is detected are completed, instructions 5 to 11 that were erroneously issued in branch prediction for branch instruction B4 are deleted. After executing the cancel process 96, the instructions 60, 61, 62 in the correct direction for the branch miss 92 are issued as shown in FIG. 24E, and the issue timing of the instructions 60, 61, 62 in the correct direction is shown. Therefore, the fifth embodiment of FIG. 24 can improve the instruction processing performance.

  In the command control of FIG. 24, the case where two IDs are used is taken as an example. However, when three IDs can be used, the command is issued without waiting until the IDs are exhausted. It is possible to wait for ID release when the ID is exhausted. That is, in FIG. 24D, issuance of instructions in the correct direction due to the branch miss 92 is not suppressed, and issuance of instructions 60 and 61 in the correct direction is started with ID = 2.

  FIG. 25 is a timing chart corresponding to the command control of FIG. In FIG. 25, when a branch miss 80 is detected along with execution of the branch instruction B4 by out-of-order at time t1, issuance of instructions 50 to 53 in the correct direction is started with another ID = 1 at time t2. . After that, when a branch miss 92 is detected as a result of execution of the branch instruction B52 in the instructions 50 to 53 issued in the correct direction, all the instructions before the branch instruction B4 in which the first branch miss 80 is detected are completed. At a later time t4, instructions 5 to 11 that have been erroneously issued in branch prediction of branch instruction B4 are canceled. Next, at time t5, issuance of instructions 60, 61, 62 in the correct direction for the branch miss 92 is started with ID = 0 already released. Thereafter, when all the instructions before the branch instruction B52 corresponding to the branch miss 92 are completed at time t6, the instructions 52 and 53 that have been erroneously issued in the branch prediction of the branch instruction B52 are canceled.

  When the timing chart of the fifth embodiment of FIG. 25 is referred to the timing chart of the fourth embodiment of FIG. 21, the issue timing of instructions 60, 61, 62 in the correct direction for the branch miss 92 is shown in FIG. In the fifth embodiment, the processing speed of the instruction can be improved correspondingly.

  FIG. 26 is a flowchart of instruction control of the fifth branch prediction instruction control unit 42-5 of FIG. In FIG. 26, an instruction is issued with the same ID in step S1, and when occurrence of a branch miss is determined along with execution of the branch instruction in step S2, another ID is assigned in step S3 and the correct direction is indicated. Issue following the instruction that has been issued by mistake. The processing of steps S1 to S3 is the processing of the first command control unit 68 and the second command control unit 70 in FIG. Next, when the third instruction control unit 72-5 determines that the second branch miss occurs in accordance with the execution of the branch instruction in the instruction issued in the correct direction in step S4, the process proceeds to step S5, and the correct instruction If it is determined in step S5 that all instructions before the older branch instruction are completed in a state in which issuance of instructions in the direction is suppressed, the process proceeds to step S6 to cancel the instruction that was erroneously issued by the old branch instruction After that, the suppression is released and instruction issue in the correct direction for the new branch miss is started.

  Subsequently, the fourth instruction control unit 74-5 determines whether or not the previous instruction of the new branch miss is completed in step S7, and if it is determined that the instruction is completed, it is erroneously issued before the detection of the new branch miss in step S8. After the canceled instruction is canceled in step S8, issue of the instruction in the correct direction is started in step S9.

  FIG. 27 is a flowchart of the branch prediction instruction control unit 42 of the processor 10 of FIG. 4. The branch prediction instruction control in which all of the first mode to fifth mode branch prediction instruction control described in FIGS. It is a flowchart. In FIG. 27, steps S1 to S3 are processes of the first instruction control unit 68 and the second instruction control unit 70. While issuing an instruction with the same ID in step S1, branching is executed in step S2 as a branch instruction is executed. If the occurrence of a mistake is determined, an instruction in the correct direction is issued with another ID added to the instruction that has been issued in error in step S3. Subsequently, in step S4, it is checked whether or not all instructions before the branch miss are completed. When all the instructions before the branch miss are completed, the process proceeds to step S7 to execute the branch prediction instruction control in the first mode. The processing content of the first mode branch prediction instruction control in step S7 is the processing in steps S5 and S6 in FIG.

  If all the instructions before the branch miss are not completed in step S4, the occurrence of the second branch miss is checked in step S5, and if the second branch miss is determined, the second time in step S6. It is determined whether or not the branch miss is older than the first branch miss. If it is an old branch miss, the process proceeds to step S8 where branch prediction instruction control in the second mode or the third mode is performed. The second mode branch prediction instruction control performed in step S8 is the process of steps S5 to S7 in FIG. Further, the branch prediction instruction control in the third mode in step S8 is the processing in steps S5 to S8 in FIG. On the other hand, if there is no branch miss older than the first branch miss in step S6, it is a new branch miss associated with the execution of the branch instruction in the instruction issued in the correct direction due to the branch miss in step S2. In step S9, the branch prediction instruction control in the fourth mode or the fifth mode is performed. This branch prediction instruction control in the fourth mode in step S9 is the processing in steps S5 to S7 in FIG. Further, the fifth mode branch prediction instruction control in step S9 in FIG. 27 is performed in steps S5 to S9 in FIG.

  As described above, the present invention may perform the branch prediction instruction control in any one of the first mode to the fifth mode, and in contrast to the first mode, either the second mode or the third mode, It is good also as control of the combination which added either 4 mode or 5th mode.

  Next, the exception generation instruction control unit 44 provided in the processor 10 of FIG. 4 will be described. Embodiments of the exception generation instruction control unit 44 include a first mode exception generation instruction control unit 44-1 in FIG. 28, a second mode exception generation control unit 44-2 in FIG. 31, and a third mode exception generation instruction in FIG. There is a control unit 44-3, a fourth mode exception generation instruction control unit 44-4 in FIG. 37, and a fifth mode exception generation instruction control unit 44-5 in FIG. The exception occurrence instruction control units 44-1 to 44-5 in the first mode, the second mode, the third mode, the fourth mode, and the fifth mode are concretely implemented by the branch prediction instruction control unit 42 described above. In the first mode, second mode, third mode, fourth mode, and fifth mode branch prediction instruction control units 42-1 to 42-5 that are forms, the detection of branch miss is replaced with exception occurrence In the case of a branch miss, the speculative failure instruction following the branch instruction in which the branch miss was detected is canceled, but in the case of an exception, the speculative failure instruction is canceled including the exception occurrence instruction itself. Is different.

  Therefore, the exception occurrence will be briefly described as follows. The first mode exception occurrence instruction control unit 44-1 in FIG. 28 includes a first instruction control unit 98, a second instruction control unit 100, and a third instruction control unit 102-1.

  FIG. 29 shows the instruction control operation of the first mode exception generation control unit 44-1 in FIG. 28. Instructions 1 to 10 issued with ID = 0 in FIG. When an exception 105 occurs, instructions 50 and 51 of the exception processing routine are issued with another ID = 1 following the instructions 5 to 11 which have been issued as no exceptions are generated. Next, as shown in FIG. 29C, when all of 1 to 3 before the exception generation instruction 4 are completed, the cancel processing 108 for canceling the speculative failure instruction 5 to the instruction 11 is performed, and then the exception processing routine instruction Resume publishing.

  FIG. 30 is a flowchart of first mode exception generation instruction control. In step S1, an instruction is issued with the same ID, and if an exception is detected by execution of the instruction in step S2, another ID is added after the speculative failure instruction in step S3. Then, an exception handling routine instruction is issued. Next, when it is determined in step S4 that all instructions prior to the occurrence of the exception have been completed, the speculative failure instruction and its resources that have been issued as no exception have been issued in step S5, and then the exception processing routine is executed in step S6. Restart issuing instructions.

  FIG. 31 is a block diagram of the second mode exception occurrence instruction control unit 44-2, which includes a first instruction control unit 98, a second instruction control unit 100, and a third instruction control unit 102-2.

  FIG. 32 shows the control operation of the second mode exception occurrence instruction control unit 44-2. First, if an exception 106 is generated by executing the instruction 4 among the instructions 1 to 11 issued with ID = 0 in FIG. 32A, it is assumed that no exception occurs as shown in FIG. Instructions 50 and 51 of the exception handling routine are issued with another ID = 1 following the speculative failure instructions 5 to 11 that have been issued. Next, in FIG. 32C, if an exception 110 is generated in accordance with the execution of the instruction 2 older than the instruction 4 in which the exception 106 has occurred, the instruction 1 before the exception 110 of the old instruction 2 as shown in FIG. Is completed, cancel processing 112 for canceling all subsequent instructions 2 to 51 including instruction 2 in which exception 110 has occurred is performed, and then instructions 60 and 61 of the exception handling routine are performed as shown in FIG. , 62...

  FIG. 33 is a flowchart of second mode exception generation instruction control. In FIG. 33, when an instruction is issued with the same ID in step S1 and an exception occurs in accordance with the execution of the instruction in step S2, behind the instruction that has been erroneously issued as no exception in step S3. Following this, an exception handling routine instruction is issued with a different ID. Next, in step S4, it is checked whether an exception has occurred for an instruction older than the first exception occurrence. If an exception has occurred for an old instruction, step S5 has all instructions before the old exception occurrence instruction completed. In step S6, all speculative failure instructions including the old instruction that caused an exception and its resources are canceled, and then in step S7, issue of an exception processing routine is started.

  FIG. 34 is a block diagram of the third mode exception occurrence instruction control unit 44-3. The first instruction control unit 98, the second instruction control unit 100, the third instruction control unit 102-3, and the fourth instruction control unit 104 are shown in FIG. -3.

  FIG. 35 is an explanatory diagram of instruction control of the third mode exception generation instruction control unit 44-3 of FIG. When an exception 106 occurs when the instruction 4 in the instruction 1 to the instruction 11 issued with ID = 0 as shown in FIG. 35 (A) is executed, an exception is given to the instruction 4 as shown in FIG. 35 (B). Following the speculative failure instructions 5 to 11 issued as no occurrence, the instructions 50 and 51 of the exception handling routine are issued with another ID = 1. Subsequently, as shown in FIG. 35 (C), if the exception 110 is generated in accordance with the execution of the instruction 2 older than the instruction 4 in which the exception 106 has occurred, an instruction processing routine for the occurrence of the exception 106 as shown in FIG. 35 (D). After executing the cancel process 114 for canceling the instructions 50 and 51 issued in step, the exception processing routine instructions 60 and 61 for the exception 110 are issued in FIG. Then, after the instruction 1 before the instruction 2 of the old exception 110 is completed in FIG. 35 (F), after performing the cancel processing 116 for canceling the speculative failure instruction 3 to the instruction 11 including the instruction 2 that has generated the exception 110. The instruction issue following the instructions 60 and 61 by the exception processing routine of the exception 110 is resumed.

  FIG. 36 is a flowchart of third mode exception generation instruction control. In FIG. 36, an instruction is issued with the same ID in step S1, and if an exception occurs in step S2 in this instruction, it is erroneously issued in step S3 as no exception following the exception occurrence instruction. An exception handling routine instruction is issued with an ID after the speculative failure instruction. Next, in step S4, it is determined whether or not an exception has occurred with an instruction older than the first exception occurrence. If an old exception has occurred, a speculative failure instruction issued in the exception processing routine for the first exception occurrence in step S5 and After canceling the resource, in step S6, an exception processing routine instruction for the occurrence of an old exception is issued with the same ID as in step S3. Subsequently, when it is determined in step S7 that all instructions prior to the occurrence of the old exception have been completed, the speculative failure instruction and resources that have been issued as no exception are canceled, including the old exception occurrence instruction, in step S8. , Resumes issuing an exception handling routine instruction.

  FIG. 37 is a block diagram of the fourth mode exception occurrence instruction control unit 44-4, which includes a first instruction control unit 98, a second instruction control unit 100, and a third instruction control unit 102-4.

  FIG. 38 is an explanatory diagram of instruction control of the fourth mode exception occurrence instruction control unit 44-4. In FIG. 38, first, after issuing the instruction 1 to the instruction 11 as shown in FIG. 38 (A), if an exception 106 occurs with the execution of the instruction 4, it is issued as no exception occurs as shown in FIG. 38 (B). Instructions 50 and 51 of the exception processing routine for exception 106 are issued with another ID = 1 after the speculative failure instructions 5 to 11 which have been lost. Subsequently, as shown in FIG. 38C, if the second exception 116 occurs when the instruction 51 is executed among the instructions 50, 51, 52, and 53 issued in the exception processing routine for the exception 106, FIG. As shown in FIG. 38D, after cancel processing 118 for canceling the speculative failure instructions 52 and 53 that have issued the instruction 50 and the instruction 51 in which the exception 116 has occurred as no exception has occurred, as shown in FIG. As described above, the issuing of the exception handling routine instructions 60, 61, 62.

  FIG. 39 is a flowchart of fourth mode exception generation instruction control. In FIG. 39, when an instruction is issued with the same ID in step S1 and an exception is identified as the instruction is executed in step S2, it is determined that no exception has occurred for the instruction in which the exception occurred in step S3. An exception handling routine instruction is issued with a different ID added to the speculative failure instruction that has been issued by mistake.

  Subsequently, when it is determined in step S4 that the second instruction is generated as a result of execution of a certain instruction among the instructions issued by the exception handling routine, in step S5, all instructions before the new exception are all displayed. If it is determined that the process has been completed, the process proceeds to step S6, cancels all subsequent speculative failure instructions including the instruction in which a new exception has occurred, and its resources, and then in step S7, executes an exception handling routine associated with the occurrence of a new exception. Restart issuing instructions.

  FIG. 40 is a block diagram of the fifth mode exception generating instruction control unit 44-5. A first command control unit 98, a second command control unit 100, a third command control unit 102-5, and a fourth command control unit 104-5 are provided.

  FIG. 41 is an explanatory diagram of instruction control of the fifth mode exception occurrence instruction control unit 44-5. When an exception 106 is generated as a result of execution of instruction 4 in instruction 1 to instruction 11 issued with ID = 0 as shown in FIG. 41A, the exception 106 is generated as shown in FIG. Thus, the instructions 50 and 51 of the exception handling routine are issued with another ID = 1 after the speculative failure instruction 5 to the instruction 11 which have been issued as an exception is not generated following the instruction 4. Subsequently, as shown in FIG. 41 (D), when the second exception 116 occurs in accordance with the execution of the instruction 52 among the instructions 50 to 54 issued in the exception processing routine as shown in FIG. 41 (C). A cancel process 120 is executed to wait for the completion of execution of all the instructions 1 to 3 prior to the instruction 4 in which the older exception 106 is generated, and to cancel the speculative failure instructions 5 to 11 following the exception occurrence instruction 4. Subsequently, as shown in FIG. 41 (E), following the instructions 53 and 54 that have become speculative failure instructions due to the second new exception 116, ID = 0 released by the cancel processing 120 is added and the exception 116 is added. Issuance of the exception handling routine instructions 60, 61, 62.

  Finally, as shown in FIG. 41 (F), after waiting for completion of all the instructions 50 and 51 before the instruction 52 in which the new exception 116 has occurred, the instruction 52 in which the exception 116 has occurred and the speculative failure instruction 53 that follows it. , 54 is cancelled, and then the issue of instructions following the instructions 60, 61, 62. In the command control of FIG. 41, the case where two IDs are used is taken as an example, but when three IDs can be used, the command issuance is performed without waiting until the IDs are exhausted. It is possible to wait for ID release when the ID is exhausted. That is, in FIG. 41D, issuance of instructions in the correct direction due to the occurrence of the exception 116 is not suppressed, and issuance of instructions 60, 61, 62 in the correct direction is started with ID = 2 at this stage.

  FIG. 42 is a flowchart of fifth mode exception generation instruction control. In FIG. 42, when an instruction is issued with the same ID in step S1 and an exception occurs in step S2 due to the execution of the instruction therein, in step S3, after the speculative failure instruction following the exception instruction. Subsequently, an exception handling routine command is issued with another ID. Next, when an exception occurs in response to the execution of an instruction in the instruction issued by the exception processing routine in step S4, the instruction before the instruction that caused the old exception in the state in which the instruction issuance by the exception processing routine is suppressed in step S5. It is determined whether or not all the instructions are completed. When the completion of the instruction is determined, in step S6, the exception generation instruction, the speculative failure instruction following the exception generation instruction, and its resources are canceled, and the instruction processing of the exception processing routine accompanying the generation of a new exception is started. Subsequently, in step S7, it is checked whether all instructions preceding the instruction that caused a new exception have been completed. If it is determined that the instruction has been completed, a subsequent speculative failure instruction including the instruction that caused the new exception occurrence in step S8. Then, after canceling the resource, in step S9, the issuance of an exception processing routine instruction associated with the occurrence of a new exception is resumed.

  FIG. 43 shows all the exception generation instruction control in the first mode, the second mode, the third mode, the fourth mode, and the fifth mode described above for the exception generation instruction control unit 44 provided in the processor 10 of FIG. It is a flowchart of integrated exception generation instruction control. In the flowchart of FIG. 43, when an instruction is issued with the same ID in step S1, and the occurrence of an exception is determined by executing the instruction in step S2, an exception is assigned with another ID in step S3. Issue processing routine instructions following speculative failure instructions. Subsequently, in step S4, it is checked whether or not all the instructions before the occurrence of the exception are completed. When the completion is determined, the exception generation instruction control in the first mode is executed in step S7.

  This exception mode instruction control in the first mode is the processing of steps S5 and S6 in FIG. If all the instructions before the exception occurrence are not completed in step S4, the second exception occurrence is checked in step S5. When the second exception occurs, the process proceeds to step S6, and it is checked whether an exception older than the first exception occurs. If an old exception has occurred, the process proceeds to step S8, and exception generation instruction control in the second or third mode is performed. The exception generation instruction control in the second mode in this case is the processing of steps S5 to S7 in FIG.

  Also, the exception generation instruction control in the third mode is the processing of steps S5 to S8 in FIG. If it is determined in step S6 that an exception has occurred that is newer than the first exception, the process proceeds to step S9, and exception generation instruction control in the fourth or fifth mode is performed. This exception mode instruction control in the fourth mode is the processing of steps S5 to S7 in FIG. Further, the exception generation instruction control in the fifth mode is the processing of steps S5 to S9 in FIG.

  In the above embodiment, a branch instruction and an exception occurrence accompanying instruction execution are taken as examples of speculatively executed instructions. However, the present invention can be applied to other appropriate speculative instructions. it can.

The present invention is not limited to the above-described embodiments, and includes appropriate modifications that do not impair the objects and advantages thereof. Further, the present invention is not limited by the numerical values shown in the above embodiments.

FIG. 1 is an explanatory diagram of an instruction control operation for a branch miss in a conventional processor;
FIG. 2 is an explanatory diagram of an instruction control operation for a branch miss in a conventional processor that assigns a different ID to each branch instruction;
FIG. 3 is an explanatory diagram of a rename map used in a conventional processor;
FIG. 4 is a block diagram of a functional configuration of a processor to which the present invention is applied;
FIG. 5 is an explanatory diagram of a rename map used in the processor of the present invention;
FIG. 6 is a circuit diagram in which the hardware scale according to the number of IDs attached to an instruction is compared between the present invention and a conventional example;
FIG. 7 is a block diagram of a first mode branch prediction instruction control unit according to the present invention;
FIG. 8 is an explanatory diagram of an instruction control operation according to the embodiment of FIG.
9 is a timing chart of an instruction control operation according to the embodiment of FIG.
FIG. 10 is a flowchart of command control according to the embodiment of FIG. 7;
FIG. 11 is a block diagram of a second mode branch prediction instruction control unit according to the present invention;
FIG. 12 is an explanatory diagram of an instruction control operation according to the embodiment of FIG.
FIG. 13 is a timing chart of an instruction control operation according to the embodiment of FIG. 11;
14 is a flowchart of command control according to the embodiment of FIG.
FIG. 15 is a block diagram of a third mode branch prediction instruction control unit according to the present invention;
FIG. 16 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 15;
FIG. 17 is a timing chart of an instruction control operation according to the embodiment of FIG. 15;
18 is a flowchart of command control according to the embodiment of FIG. 15;
19 is a block diagram of a fourth mode branch prediction instruction control unit according to the present invention;
20 is an explanatory diagram of an instruction control operation according to the embodiment of FIG.
FIG. 21 is a timing chart of an instruction control operation according to the embodiment of FIG.
22 is a flowchart of command control according to the embodiment of FIG. 19;
FIG. 23 is a block diagram of a fourth mode branch prediction instruction control unit according to the present invention;
FIG. 24 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 23;
25 is a timing chart of an instruction control operation according to the embodiment of FIG.
FIG. 26 is a flowchart of command control according to the embodiment of FIG. 24;
FIG. 27 is a flowchart of instruction control in which branch prediction instruction control in the first mode to the fifth mode is integrated according to the present invention;
FIG. 28 is a block diagram of a first mode exception generation instruction control unit according to the present invention;
FIG. 29 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 27;
30 is a flowchart of command control according to the embodiment of FIG. 27;
FIG. 31 is a block diagram of a second mode exception generation instruction control unit according to the present invention;
FIG. 32 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 31;
FIG. 33 is a flowchart of command control according to the embodiment of FIG. 31;
34 is a block diagram of a third mode exception generation instruction control unit according to the present invention;
35 is an explanatory diagram of the instruction control operation according to the embodiment of FIG. 34;
36 is a flowchart of command control according to the embodiment of FIG. 34;
FIG. 37 is a block diagram of a fourth mode exception generation instruction control unit according to the present invention;
FIG. 38 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 37;
39 is a flowchart of command control according to the embodiment of FIG. 37;
40 is a block diagram of a fifth mode exception generation instruction control unit according to the present invention;
41 is an explanatory diagram of an instruction control operation according to the embodiment of FIG. 40;
42 is a flowchart of command control according to the embodiment of FIG. 41;
FIG. 43 is a flowchart of instruction control in which exception generation instruction control from the first mode to the fifth mode is integrated according to the present invention;

Explanation of symbols

10: Processor 12: Branch prediction unit 16: Instruction storage unit 18: Instruction execution unit 18
20: Instruction determination unit 22: Register 24: Renaming processing unit 24
26-1 to 26-4 instruction storage queues 26-1 to 26-4
28: Branch processing unit 30: Integer arithmetic unit 32: Floating point arithmetic unit 34: Load / store processing unit 36: Reorder buffer 36
38: Rename map 38
40: Instruction control unit 42: Branch prediction instruction control unit 44: Exception occurrence instruction control unit 68: First instruction control unit 70: Second instruction control unit 72-5: Third instruction control unit 74-5: Fourth instruction control Part

Claims (22)

A first instruction control unit that issues an instruction including a branch instruction with a first identifier attached, and speculatively executes by branch prediction;
A second instruction control unit for issuing an instruction in the correct direction with a second identifier following the instruction that has been issued in error when a branch error is detected;
After all the instructions before the branch are completed, the instruction issued in error by the branch prediction is canceled, and the instruction issued in the correct direction following the instruction issued by the second instruction control unit is attached with the second identifier. A third command control unit starting with
A processor comprising:
A first instruction control unit that issues an instruction including a branch instruction with a first identifier attached, and speculatively executes by branch prediction;
A second instruction control unit that issues an instruction in the correct direction with a second identifier following the instruction that has been issued in error when the first branch miss is detected;
After the first branch miss is detected and an instruction in the correct direction of the first branch miss is issued, if a second branch miss is detected in the previous old branch instruction, the instruction before the old branch instruction A third instruction control unit that waits for all to complete, cancels all subsequent instructions, and then starts issuing instructions in the correct direction for the second branch miss ;
A processor comprising:
A first instruction control unit that issues an instruction including a branch instruction with a first identifier attached, and speculatively executes by branch prediction;
A second instruction control unit that issues an instruction in the correct direction with a second identifier following the instruction that has been issued in error when the first branch miss is detected;
After the first branch miss is detected and an instruction in the correct direction of the first branch miss is issued, if a second branch miss is detected in an old branch instruction before that, the first branch miss is detected. A third instruction control unit that starts issuing instructions in the correct direction of the second branch miss determined by detecting the second branch miss after canceling the issued instruction determined to be in the correct direction by detection;
After the second branch miss was detected and an instruction in the correct direction was issued, the instruction before the old branch instruction was completely completed, and was issued erroneously by the second branch prediction. A fourth instruction control unit that cancels the instruction and then resumes issuing instructions in the correct direction;
A processor comprising:
A first instruction control unit that issues an instruction including a branch instruction with a first identifier attached, and speculatively executes by branch prediction;
A second instruction control unit that issues an instruction in the correct direction with a second identifier following the instruction that has been issued in error when the first branch miss is detected;
After the first branch miss is detected and instruction issue in the correct direction of the first branch miss is started, if a second branch miss is detected with a new branch instruction in the instruction issued as the correct direction, the new branch miss is detected. A third instruction control unit that waits for all instructions before the branch instruction to complete and cancels all subsequent instructions, and then starts issuing instructions in the correct direction of the second branch miss ;
A processor comprising:
A first instruction control unit that issues an instruction including a branch instruction with a first identifier attached, and speculatively executes by branch prediction;
A second instruction control unit that issues an instruction in the correct direction with a second identifier following the instruction that has been issued in error when the first branch miss is detected;
After detecting the first branch miss and starting issuing instructions in the correct direction of the first branch miss, if the second branch miss is detected with a new branch instruction in the instruction issued as the correct direction, the correct direction The instruction issued before the older branch instruction in which the first branch miss is detected is completely canceled while the instruction issued by the old branch instruction is canceled. A third instruction control unit that cancels the inhibition and starts issuing an instruction in the correct direction of the second branch miss ;
After an instruction is issued in the correct direction due to the detection of the second branch miss, the instruction issued by the detection of the first branch prediction is canceled after all instructions before the new branch instruction are completed. And a fourth instruction control unit that resumes issuing instructions in the correct direction due to the second branch miss;
A processor comprising:
In the processor of claims 1 to 5, further:
In the entry referenced by the register number used by the instruction, the address storage area of the reorder buffer used for renaming, and the rename map having a plurality of valid flag areas corresponding to the plurality of identifiers attached in the instruction control ,
When the register used by the instruction is renamed using the reorder buffer, the address of the reorder buffer used for renaming is stored in the entry of the rename map referenced by the register number, and the identifier attached to the instruction When the valid flag corresponding to is turned on and a branch miss is detected, the rename flag valid flag corresponding to the identifier attached to the instruction that was issued by mistake is turned off and attached to the instruction issued in the correct direction. A renaming processing unit for turning on a valid flag of a rename map corresponding to another identifier;
And a processor for preventing use of renaming information by an instruction in which a correct direction instruction issued by detecting a branch miss is erroneously issued.
A first step of issuing an instruction including a branch instruction with a first identifier attached and executing speculatively by branch prediction;
A second step of issuing an instruction in the correct direction with a second identifier following the instruction that has been issued in error when a branch miss is detected;
After all the instructions before the branch are completed, the instruction that has been issued in error by the branch prediction is canceled, and the instruction issued in the correct direction following the instruction issued by the second step is attached with the second identifier. A third step to start;
An instruction control method for a processor, comprising:
A first step of issuing an instruction including a branch instruction with a first identifier attached and executing speculatively by branch prediction;
A second step of issuing an instruction in the correct direction with a second identifier following the instruction that has been issued in error when the first branch miss is detected;
After the first branch miss is detected and an instruction in the correct direction of the first branch miss is issued, if a second branch miss is detected in the previous old branch instruction, the instruction before the old branch instruction Waiting for all to complete, canceling all subsequent instructions, and then starting issuing instructions in the right direction for the second branch miss ; and
An instruction control method for a processor, comprising:
A first step of issuing an instruction including a branch instruction with a first identifier attached and executing speculatively by branch prediction;
A second step of issuing an instruction in the correct direction with a second identifier following the instruction that has been issued in error when the first branch miss is detected;
After the first branch miss is detected and an instruction in the correct direction of the first branch miss is issued, if a second branch miss is detected in an old branch instruction before that, the first branch miss is detected. A third step of starting issuing instructions in the correct direction of the second branch miss determined by detecting the second branch miss after canceling the issued instruction determined to be in the correct direction by detection;
After the second branch miss was detected and an instruction in the correct direction was issued, the instruction before the old branch instruction was completely completed, and was issued erroneously by the second branch prediction. A fourth step of canceling the instruction and then restarting issuing instructions in the correct direction;
An instruction control method for a processor, comprising:
A first step of issuing an instruction including a branch instruction with a first identifier attached and executing speculatively by branch prediction;
A second step of issuing an instruction in the correct direction with a second identifier following the instruction that has been issued in error when the first branch miss is detected;
After the first branch miss is detected and instruction issue in the correct direction of the first branch miss is started, if a second branch miss is detected with a new branch instruction in the instruction issued as the correct direction, the new branch miss is detected. A third step of waiting for all instructions before the branch instruction to complete, canceling all subsequent instructions, and starting issuing instructions in the right direction of the second branch miss ;
An instruction control method for a processor, comprising:
A first step of issuing an instruction including a branch instruction with a first identifier attached and executing speculatively by branch prediction;
A second step of issuing an instruction in the correct direction with a second identifier following the instruction that has been issued in error when the first branch miss is detected;
After detecting the first branch miss and starting issuing instructions in the correct direction of the first branch miss, if the second branch miss is detected with a new branch instruction in the instruction issued as the correct direction, the correct direction The instruction issued before the older branch instruction in which the first branch miss is detected is completely canceled while the instruction issued by the old branch instruction is canceled. A third step of releasing the inhibition and starting issuing instructions in the correct direction of the second branch miss ;
After an instruction is issued in the correct direction due to the detection of the second branch miss, the instruction issued by the detection of the first branch prediction is canceled after all instructions before the new branch instruction are completed. A fourth step of resuming issue of instructions in the correct direction due to the second branch miss;
An instruction control method for a processor, comprising:
In the processor instruction control method according to claims 7 to 11,
In the entry referenced by the register number used by the instruction, there is a rename map with a reorder buffer address storage area used for renaming and a plurality of valid flag areas corresponding to a plurality of identifiers attached by instruction control. If you have
When a register used by an instruction is renamed using a reorder buffer, the address of the reorder buffer used for renaming is stored in the entry of the rename map referenced by the register number, and attached to the instruction. Turn on the valid flag corresponding to the identifier
When a branch miss is detected, the valid flag of the rename map corresponding to the identifier attached to the instruction that has been issued in error is turned off, and the identifier corresponding to another identifier attached to the instruction issued in the correct direction By turning on the renaming map valid flag,
An instruction control method for a processor, characterized in that an instruction in a correct direction issued by detecting a branch miss is prevented from using rename information by an instruction issued in error.
A first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached, and speculatively executes the instruction as no exception occurs;
A second instruction control unit that issues an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as no exception occurrence when an exception occurrence is detected;
After all the instructions before the exception generation instruction are completed, the exception generation instruction and the instruction generated as no exception are canceled, and the instruction processing of the exception processing routine following the instruction issued by the second instruction control unit is issued . And a third instruction control unit that starts with two identifiers attached thereto.
A first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached, and speculatively executes the instruction as no exception occurs;
A second instruction control unit that issues an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
When the second exception occurrence is detected in the old instruction before the first exception occurrence is detected and the instruction of the exception handling routine in the correct direction is issued, the instruction before the old exception occurrence instruction is A third instruction control unit that waits for the completion of the exception, cancels the exception generation instruction and all subsequent instructions, and then starts issuing an instruction of the exception handling routine due to the second exception generation;
A processor comprising:
A first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached, and speculatively executes the instruction as no exception occurs;
A second instruction control unit that issues an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
When the second exception occurrence is detected in the old instruction before the first exception occurrence is detected and the instruction of the exception handling routine in the correct direction is issued, the first exception occurrence is detected. A third instruction control unit that starts issuing an exception handling routine instruction that is in the correct direction upon detection of the occurrence of the second exception after canceling the issued exception handling routine instruction;
The second exception is detected after the instruction of the exception processing routine is issued, the old Aya Ordinance previous instruction waiting for the completion of all, the first instruction and the exception has caused the occurrence A fourth instruction control unit that cancels an instruction that has been erroneously issued as having no exception caused by the instruction, and then resumes issuing an instruction of the exception processing routine by the occurrence of the second exception;
A processor comprising:
A first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached, and speculatively executes the instruction as no exception occurs;
A second instruction control unit that issues an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
When the second exception occurrence is detected by a new instruction in the instruction issued by the exception handling routine after the first exception occurrence is detected and the instruction issuance of the exception handling routine in the correct direction is started. A third instruction control unit which waits for completion of all instructions before the exception generation instruction, cancels the exception generation instruction and all subsequent instructions, and then starts issuing an exception processing routine instruction upon occurrence of the first exception When,
A processor comprising:
A first instruction control unit that issues an instruction including an exception occurrence instruction with a first identifier attached, and speculatively executes the instruction as no exception occurs;
A second instruction control unit that issues an exception processing routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
When the second exception occurrence is detected by a new instruction in the instruction issued by the exception processing routine after the first exception occurrence is detected and the instruction issuance of the exception handling routine in the correct direction is started. Waiting for all instructions before the older exception generation instruction in which the first exception has been detected to be completed in a state where instruction generation of the processing routine is suppressed, no exception is generated by the old exception generation instruction and the instruction. A third instruction control unit that cancels the instruction that has been issued in error, then cancels the inhibition, and starts issuing an exception processing routine instruction that is in the correct direction upon occurrence of the second exception;
After the instruction of the exception handling routine is issued due to the occurrence of the second exception, the second exception occurrence instruction and the first exception occurrence are waited until all the instructions before the new exception occurrence instruction are completed. A fourth instruction control unit that cancels an instruction issued in the exception handling routine and then resumes issuing an exception handling routine instruction upon occurrence of the second exception;
A processor comprising:
A first step of issuing an instruction including an exception generation instruction with a first identifier attached, and executing the instruction speculatively without occurrence of an exception;
A second step of issuing an exception handling routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when an exception occurrence is detected;
After it said exception occurrence instruction previous instruction has been completed, the instruction issue of the exception processing routine to cancel an instruction had issued following the instructions the second step is issued as no exception instruction and an exception occurs A third step starting with the second identifier attached ;
An instruction control method for a processor, comprising:
A first step of issuing an instruction including an exception generation instruction with a first identifier attached, and executing the instruction speculatively without occurrence of an exception;
A second step of issuing an exception handling routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
After the first exception occurrence is detected and an exception handling routine instruction in the correct direction is issued, when the second exception occurrence is detected in the old instruction before that, all the instructions before the old branch instruction are all A third step of waiting for completion, canceling the exception occurrence instruction and all subsequent instructions, and then starting issuing an exception processing routine instruction upon occurrence of the second exception;
An instruction control method for a processor, comprising:
A first step of issuing an instruction including an exception generation instruction with a first identifier attached, and executing the instruction speculatively without occurrence of an exception;
A second step of issuing an exception handling routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
When the second exception occurrence is detected in the old instruction before the first exception occurrence is detected and the instruction of the exception handling routine in the correct direction is issued, the first exception occurrence is detected. A third step of starting issuing an exception handling routine instruction that is in the correct direction upon detection of the occurrence of the second exception after canceling the issued exception handling routine instruction;
The second exception is detected after the instruction of the exception processing routine is issued, the old Aya Ordinance previous instruction waiting for the completion of all, the first instruction and the exception has caused the occurrence A fourth step of canceling an instruction that has been erroneously issued as having no exception caused by the instruction, and then resuming the instruction issuing of the exception handling routine by the occurrence of the second exception;
An instruction control method for a processor, comprising:
A first step of issuing an instruction including an exception generation instruction with a first identifier attached, and executing the instruction speculatively without occurrence of an exception;
A second step of issuing an exception handling routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
When the second exception occurrence is detected by a new instruction in the instruction issued by the exception handling routine after the first exception occurrence is detected and the instruction issuance of the exception handling routine in the correct direction is started. A third step of waiting for all instructions before the exception generation instruction to be completed, canceling the exception generation instruction and all subsequent instructions, and starting issuing an exception processing routine instruction by the first exception generation;
An instruction control method for a processor, comprising:
A first step of issuing an instruction including an exception generation instruction with a first identifier attached, and executing the instruction speculatively without occurrence of an exception;
A second step of issuing an exception handling routine instruction with a second identifier following an instruction that has been erroneously issued as having no exception when the first exception occurrence is detected;
When the second exception occurrence is detected by a new instruction in the instruction issued by the exception processing routine after the first exception occurrence is detected and the instruction issuance of the exception handling routine in the correct direction is started. Waiting for all instructions before the older exception generation instruction in which the first exception has been detected to be completed in a state where instruction generation of the processing routine is suppressed, no exception is generated by the old exception generation instruction and the instruction. A third step of canceling the instruction that has been issued in error, then canceling the inhibition and starting issuing an instruction of an exception handling routine that takes the correct direction upon occurrence of the second exception;
After an exception handling routine instruction is issued due to the second exception occurrence, the second exception occurrence instruction and the first exception occurrence exception are waited for completion of all instructions before the new exception occurrence instruction. A fourth step of canceling the instruction issued in the processing routine and then restarting the issuance of the instruction of the exception processing routine due to the occurrence of the second exception;
An instruction control method for a processor, comprising:

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