WO2004028959A2 - Procede et dispositif micromecanique - Google Patents

Procede et dispositif micromecanique Download PDF

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Publication number
WO2004028959A2
WO2004028959A2 PCT/DE2003/000704 DE0300704W WO2004028959A2 WO 2004028959 A2 WO2004028959 A2 WO 2004028959A2 DE 0300704 W DE0300704 W DE 0300704W WO 2004028959 A2 WO2004028959 A2 WO 2004028959A2
Authority
WO
WIPO (PCT)
Prior art keywords
coil
metallic conductor
conductor
substrate
etching step
Prior art date
Application number
PCT/DE2003/000704
Other languages
German (de)
English (en)
Other versions
WO2004028959A3 (fr
Inventor
Lars Metzger
Frank Fischer
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2004028959A2 publication Critical patent/WO2004028959A2/fr
Publication of WO2004028959A3 publication Critical patent/WO2004028959A3/fr

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0735—Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit

Definitions

  • the invention is based on a method and a device according to the type of the independent claims. Coils that are known by means of a
  • the coil is provided as a self-supporting coil over a deep cavity.
  • the cavity is produced by oxidizing substrate material in a first step in the region of the later cavity and then creating the cavity by means of an etching medium attacking the oxidized material.
  • This has the disadvantage that high temperatures are required to produce the oxidized substrate material.
  • the manufacture of such a coil is not compatible with the manufacture of standard semiconductor components, for example using CMOS technology.
  • the method according to the invention and the device according to the invention with the features of the claims in the rubbing have the advantage over the prior art that, according to the invention, silicon is not used as the sacrificial layer.
  • the area of the sacrificial layer is first deeply nested, for example using Deep Reactive Ion Etching DRIE and then laterally completely etched using an isotropic etching process, for example using a xenon difluoride or chloro rifluoride process.
  • the isotropic etching process can also wet chemical processes such as KOH etching can be used.
  • the method according to the invention is characterized by a simple process sequence and thus an inexpensive implementation compared to the prior art.
  • oxidation can be dispensed with.
  • the proposed process is a low-temperature process, as a result of which it can easily be used for integrated sensors which, in addition to the high-frequency component, provide further circuit elements integrated in a monolithic manner.
  • the connected conductor tracks can be completely passivated with insulators, since the etching process etches silicon extremely selectively with respect to insulators such as silicon dioxide, silicon nitrite or even dielectrics with a low K value.
  • the isotropic etching step is also extremely selective with respect to conductor bellow materials such as aluminum, aluminum alloys with copper or / and silicon, TfN or tungsten.
  • the coil layers or the metallic conductors can easily be protected against the etching attack by means of a passivation.
  • High-frequency component together to integrate electronic circuits on the same substrate, which were produced with a conventional technology for producing microelectronic circuits, for example CMOS. It is furthermore advantageous that the at least one metallic conductor is first structured, that a deep etching step is then carried out, and that another isotropic etching step is then carried out on it. This makes it possible to produce the high-frequency component particularly cost-effectively and with a low temperature load. It is also advantageous that the deep etching step is provided as a DRIE step. In this way, a particularly inexpensive manufacturing technology can be used,
  • the further isotropic etching step is carried out using a XeF 2 , C1F 3 , BrF 3 or SF S plasma or wet-chemically using TMAH or KOH or HN0 3 / HF etchant.
  • TMAH TMAH
  • KOH KOH
  • HN0 3 / HF etchant wet-chemically using TMAH or KOH or HN0 3 / HF etchant.
  • the at least one metallic conductor is a coil. This makes it possible according to the invention to produce a component which is to be produced particularly frequently and with great effort using the method according to the invention.
  • the metallic conductor is self-supporting or is provided on a supporting insulation layer.
  • FIG. 1 shows a known coil arrangement according to the prior art
  • FIG. 2 shows a first preliminary stage of the device according to the invention
  • FIG. 3 shows a second preliminary stage of the device according to the invention
  • FIG. 4 shows a third preliminary stage of the device according to the invention
  • FIG. 5 shows a fourth preliminary stage of the inventive device
  • FIG. 6 shows a fifth preliminary stage of the inventive device
  • FIG. 7 shows a sixth preliminary stage of the inventive device
  • FIG. 8 shows a seventh preliminary stage of the device according to the invention and FIG. 9 shows the device according to the invention.
  • filters for example coupled bandpass filters, tunable capacitors or inductors in micromechanical systems can also be represented, for example for LC resonators.
  • the challenges of radio frequency milo-electro-mechanical systems include capping, in particular the vacuum capping of high quality systems and the implementation of tiny plate spacings in tunable capacities, as well as the implementation of very large insulation distances, for example in coil designs or conductor tracks to reduce the dielectric losses in insulation layers or conductive component components.
  • Coils have generally been produced using surface micromechanical technology.
  • FIG. 1 on the left side of the figure, a view of a radio frequency coil is shown, in which the coil winding with the reference number 4, the upstream coil spool with the reference number 3 and the cavern below the coil, which is provided for air insulation , is designated by the reference number 5.
  • the substrate in particular silicon substrate, with the reference number 1, an insulation oxide with the reference number 2, the back-running coil conductor with the reference number 3, the coil winding with the Reference number 4 and the cavern is again designated with reference number 5.
  • the substrate in particular silicon substrate, with the reference number 1
  • an insulation oxide with the reference number 2 the back-running coil conductor with the reference number 3
  • the coil winding with the Reference number 4 and the cavern is again designated with reference number 5.
  • a seat structure is etched in the sacrificial layer area below the coil or below the coil winding using a DRIE (Deep Reactive Ion Etching) method at depths of between 50 and 100 ⁇ m.
  • the silicon supports are completely oxidized in a subsequent oxidation process and covered with an oxide in a CVD process (Chemical Vapor Deposition). This creates an almost planar oxide surface, on which further layers for coil contraction can be applied. Due to the large thickness of the oxide block that is formed, capacitances between the coil and the substrate are greatly reduced and losses are thus reduced.
  • this oxide support configuration is removed selectively with respect to the coil materials and the substrate layers as a sacrificial layer using etching media containing hydrofluoric acid, for example BOE (buffered oxide etch).
  • etching media containing hydrofluoric acid for example BOE (buffered oxide etch).
  • the large distance to conductive surfaces or the low dielectric constant of the cavity insulator (especially air) means that only small losses occur during high-frequency operation of the coil.
  • the method according to the invention provides for producing a self-supporting high-frequency component, the component being provided in particular as a coil.
  • the invention can not only be used for the insulation of coils, but can in principle also be applied to other component components in high-frequency components, such as, for example, conductor tracks, etc.
  • the method is designed to be CMOS-compatible, i.e. it can be on the same substrate as that
  • High-frequency component also mil ⁇ oelectronic circuits using a conventional process technology, in particular CMOS technology, to be made or provided. '
  • FIGS. 2 to 9 The production method according to the invention is described in FIGS. 2 to 9 on the basis of various preliminary stages and finally the device according to the invention.
  • FIG. 2 shows a first preliminary stage of the device according to the invention.
  • a first one is on a substrate 10, which is provided in particular as silicon suebate
  • Insulation layer 21 applied which according to the invention can be provided in a structured manner.
  • the first insulation layer 21 is provided, for example, from silicon dioxide or also from silicon nitride.
  • FIG. 3 shows a second preliminary stage of the device according to the invention, again with the substrate 10, the first insulation layer 21 and a first conductive layer 31.
  • the first conductive layer 31 is provided in a structured manner and forms part of the at least one metallic conductor provided according to the invention.
  • the first conductive layer 31 is therefore in particular made of a metal such as aluminum, gold and the like. Alternatively, it can also be provided to use silicon as the material of the conductor of the first conductive layer 31. However, the sheet resistance should be small, which is why the invention provides for the use of metals.
  • FIG. 4 shows a third preliminary stage of the device according to the invention.
  • the first insulation layer 21 and the first conductive layer 31 there is one second insulation layer 22 shown.
  • the second insulation layer 22 in particular the same material is provided as for the first insulation layer 21, in particular silicon dioxide or silicon nitride.
  • the second insulation layer 22 is also provided in a structured manner.
  • FIG. 5 shows a fourth preliminary stage of the device according to the invention.
  • the first insulation layer 21, the first conductive layer 31 and the second insulation layer 22 a second conductive layer 32 is shown.
  • the second conductive layer 32 is connected to the first conductive layer 31 in certain areas, which are given the reference number 39 in FIG. 5, so that an electrically low-resistance one
  • first conductive layer 31 and the second conductive layer 32 contact occurs between the first conductive layer 31 and the second conductive layer 32.
  • the first conductive layer 31 and the second conductive layer 32 together form the metallic conductor. 5, 6, 7, 8 and 9, a cross-sectional representation of a coil former is indicated as a metallic conductor.
  • the ones already described for the first conductive layer 31 also come for the second conductive layer or the second interconnect level 32
  • a third isolation level which is not shown in FIG. 5, can be deposited on the preliminary stage of the device according to the invention shown in FIG. 5.
  • FIG. 6 shows a fifth preliminary stage of the device according to the invention.
  • Area of the component in which there is no layer of the metallic conductor 31, 32 - compare in particular the top view in the left part of FIG. 1 - it is possible to carry out a deep etching in order to create a cavity below the conductor structure.
  • an opening must first be made through the insulation layers 21, 22.
  • Such openings are provided with the reference number 41 in FIG. 6.
  • the substrate 10, the first insulation layer 21, the second insulation layer 22, the first conductive layer 31 and the second conductive layer 32 are also shown in FIG. 6.
  • To open the areas provided with the reference symbol 41 it is provided according to the invention that a large-area opening or a large-area perforation of the areas 41 is created.
  • FIG. 7 shows a sixth preliminary stage of the device according to the invention.
  • the open areas provided with the reference number 41 from FIG. 6 were extended downwards into the substrate 10 by means of a deep etching step in order to form the cavity precursors 42.
  • the DRIE method is used in particular and an etching depth of 10 to 200 ⁇ m is achieved.
  • the substrate 10, the first and second insulation layers 21, 22 and the first and second conductive layers 31, 32 are shown in FIG. 7.
  • FIG. 8 shows the seventh preliminary stage of the device according to the invention.
  • an isotropic etching step is carried out into the cavity pre-stages 42, which removes the supports of the micromechanical structure designated by the reference number 11 in FIGS. 7 and 8.
  • the isotropic etching step is carried out according to the invention in particular by using etching media such as XeF 2 , C1F 3 , BrF 3 or SF e , ie by means of a
  • Plasma etching process or also carried out by means of a wet chemical etching process with etching media such as TMAH, KOH, HNO 3 / HF and the like.
  • etching media such as TMAH, KOH, HNO 3 / HF and the like.
  • the etching medium is provided with the reference symbol 45 in FIG. Otherwise, the substrate 10, the first and second insulation layers 21, 22 and the first and second conductive layers 31, 32 are shown again.
  • FIG. 9 shows the device according to the invention, the support structures 11 being removed by the isotropic etching process and a cavern 44 being produced under the structure of the metallic conductor 31, 32.
  • FIG. 9 again shows the substrate 10, the first and second insulation layers 21, 22 and the metallic conductor 31, 32.
  • thermoelectric process it is thus possible to produce any high-frequency components as micromechanical structures using a CMOS-compatible method. It is particularly important here that temperatures which are not too high are required when carrying out the method. Such a low-temperature process is characterized in that significantly lower temperatures are required than those temperatures which are required for the formation of thermally oxidized silicon. According to the invention, these are provided in particular as temperatures below 600 ° C.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé et un dispositif comprenant un composant haute fréquence produit au moyen d'un conducteur métallique à l'aide d'un procédé basse température.
PCT/DE2003/000704 2002-09-19 2003-03-06 Procede et dispositif micromecanique WO2004028959A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10243511.1 2002-09-19
DE2002143511 DE10243511A1 (de) 2002-09-19 2002-09-19 Verfahren und mikromechanische Vorrichtung

Publications (2)

Publication Number Publication Date
WO2004028959A2 true WO2004028959A2 (fr) 2004-04-08
WO2004028959A3 WO2004028959A3 (fr) 2004-12-29

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DE (1) DE10243511A1 (fr)
WO (1) WO2004028959A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2750177A3 (fr) * 2006-09-26 2014-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Formation d'interconnexions électriques à travers des plaquettes et d'autres structures utilisant une membrane diélectrique mince

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007020288B4 (de) * 2007-04-30 2013-12-12 Epcos Ag Elektrisches Bauelement

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051866A (en) * 1993-02-04 2000-04-18 Cornell Research Foundation, Inc. Microstructures and single mask, single-crystal process for fabrication thereof
US6239473B1 (en) * 1998-01-15 2001-05-29 Kionix, Inc. Trench isolation for micromechanical devices
WO2001098200A1 (fr) * 2000-06-21 2001-12-27 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Transistor vertical a grille mobile et son procede de production
US20020020895A1 (en) * 2000-08-01 2002-02-21 Ahn Kie Y. Low loss high Q inductor
US6388300B1 (en) * 1999-01-25 2002-05-14 Denso Corporation Semiconductor physical quantity sensor and method of manufacturing the same
US20020101300A1 (en) * 2000-06-06 2002-08-01 Kudrle Thomas D. Transmission line structures for use as phase shifters and switches

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051866A (en) * 1993-02-04 2000-04-18 Cornell Research Foundation, Inc. Microstructures and single mask, single-crystal process for fabrication thereof
US6239473B1 (en) * 1998-01-15 2001-05-29 Kionix, Inc. Trench isolation for micromechanical devices
US6388300B1 (en) * 1999-01-25 2002-05-14 Denso Corporation Semiconductor physical quantity sensor and method of manufacturing the same
US20020101300A1 (en) * 2000-06-06 2002-08-01 Kudrle Thomas D. Transmission line structures for use as phase shifters and switches
WO2001098200A1 (fr) * 2000-06-21 2001-12-27 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Transistor vertical a grille mobile et son procede de production
US20020020895A1 (en) * 2000-08-01 2002-02-21 Ahn Kie Y. Low loss high Q inductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2750177A3 (fr) * 2006-09-26 2014-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Formation d'interconnexions électriques à travers des plaquettes et d'autres structures utilisant une membrane diélectrique mince

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Publication number Publication date
WO2004028959A3 (fr) 2004-12-29
DE10243511A1 (de) 2004-04-01

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