WO2004021398A2 - Wafer-level seal for non-silicon-based devices - Google Patents

Wafer-level seal for non-silicon-based devices Download PDF

Info

Publication number
WO2004021398A2
WO2004021398A2 PCT/US2003/018103 US0318103W WO2004021398A2 WO 2004021398 A2 WO2004021398 A2 WO 2004021398A2 US 0318103 W US0318103 W US 0318103W WO 2004021398 A2 WO2004021398 A2 WO 2004021398A2
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
wafer
sacrificial material
active area
seal coating
Prior art date
Application number
PCT/US2003/018103
Other languages
French (fr)
Other versions
WO2004021398A3 (en
Inventor
Gregory D. Miller
Mike Bruner
Lawrence H. Ragan
Gary W. Green
Original Assignee
Silicon Light Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/231,356 external-priority patent/US6877209B1/en
Priority claimed from US10/231,357 external-priority patent/US6846423B1/en
Application filed by Silicon Light Machines Corporation filed Critical Silicon Light Machines Corporation
Priority to EP03791559A priority Critical patent/EP1540736A4/en
Priority to JP2004532581A priority patent/JP2005537661A/en
Priority to AU2003243451A priority patent/AU2003243451A1/en
Publication of WO2004021398A2 publication Critical patent/WO2004021398A2/en
Publication of WO2004021398A3 publication Critical patent/WO2004021398A3/en

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261Processes for packaging MEMS devices
    • B81C1/00277Processes for packaging MEMS devices for maintaining a controlled atmosphere inside of the cavity containing the MEMS
    • B81C1/00293Processes for packaging MEMS devices for maintaining a controlled atmosphere inside of the cavity containing the MEMS maintaining a controlled atmosphere with processes not provided for in B81C1/00285
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/02535Details of surface acoustic wave devices
    • H03H9/02818Means for compensation or elimination of undesirable effects
    • H03H9/02921Measures for preventing electric discharge due to pyroelectricity
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/02535Details of surface acoustic wave devices
    • H03H9/02984Protection measures against damaging
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/10Mounting in enclosures
    • H03H9/1064Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1092Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the surface acoustic wave [SAW] device on the side of the IDT's
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/01Packaging MEMS
    • B81C2203/0136Growing or depositing of a covering layer

Definitions

  • the present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.
  • Non-silicon-based devices are being manufactured for use in communications and other applications. Such devices are often sensitive to contamination or to the atmosphere in which they operate, and hence it is desirable for them to operate in a controlled atmosphere. Examples of these atmosphere- sensitive non-silicon-based devices include surface acoustic wave (SAW) devices, electro-optic modulators, acoustic-optic devices, and so on.
  • SAW surface acoustic wave
  • SAW devices are often used in communication devices, such as, for instance, radio frequency (RF) filters in mobile phone handsets and communication networks.
  • SAW devices utilize waves that propagate along the surface (or near surface) of a substrate.
  • SAW devices include those that utilize piezoelectrically-coupled Rayleigh waves and may also include those that utilize non-Rayleigh (skimming or "leaky") waves.
  • a typical SAW filter includes input and output transducers formed on a non- silicon-based piezoelectric substrate, such as, for example, lithium tantalate, lithium niobate, or single crystal quartz.
  • the transducers may be metallic electrodes, for example, interleaved aluminum fingers.
  • one operating at 2.5 GHz may have a minimum feature size of approximately 0.4 microns for the aluminum fingers of the transducers.
  • SAW devices One problem encountered with SAW devices is that the regions of the device where the acoustic waves are present can be very sensitive to the presence of surface contaminants that alter the wave velocities and consequently degrade the device performance. Even a monolayer of contaminant on the surface of the crystal can noticeably alter the device performance. Also, it is desirable for the SAW devices to operate in a low pressure (near vacuum) atmosphere, rather than in atmospheric air. Operating in such a low pressure atmosphere can decrease the viscous damping of the acoustic waves. Another problem associated with SAW devices is that a change in acoustic wave velocity is temperature dependent. In other words, a temperature change can change the velocity of the acoustic waves. This temperature dependence effectively limits the operable temperature range of SAW devices.
  • One embodiment of the invention relates to a method for sealing an active area of a non-silicon-based device on a wafer.
  • the method includes providing a sacrificial material over at least the active area of the non-silicon-based device, depositing a seal coating over the wafer so that the seal coating covers the sacrificial material, and replacing the sacrificial material with a target atmosphere.
  • Another embodiment of the invention relates to a non-silicon-based device sealed at the wafer level (i.e. prior to separation of the die from the wafer).
  • the device includes an active area to be protected, a contact area, and a lithographically- formed structure sealing at least the active area and leaving at least a portion of the contact area exposed.
  • Another embodiment of the invention relates to a method for sealing an active area of an SAW device on a wafer.
  • the method includes providing a sacrificial material over at least the active area of the SAW device, depositing a seal coating over the wafer so that the seal coating covers the sacrificial material, and replacing the sacrificial material with a target atmosphere.
  • Another embodiment of the invention relates to an SAW device sealed at the wafer level (i.e. prior to separation of the die from the wafer).
  • the device includes an active area to be protected, an electrical contact area, and a lithographically- formed structure sealing at least the active area and leaving at least a portion of the electrical contact area exposed.
  • FIG. 1A is a cross-sectional diagram depicting an unsealed non-silicon-based device (in this instance, an SAW device) as fabricated on the surface of a wafer.
  • FIG. 1 B, 1C, 1 D, 1 E, 1F, 1G, 1 H and 11 are cross-sectional diagrams depicting various steps in the process of sealing the non-silicon-based device in accordance with an embodiment of the invention.
  • FIG. 2 is a flow chart depicting a method for sealing an active area of a non- silicon device (in this instance, a wave propagation area of a SAW device) on a wafer in accordance with an embodiment of the invention.
  • a non- silicon device in this instance, a wave propagation area of a SAW device
  • Seals may be formed, for example, in metal or ceramic packages.
  • a metal package may be welded or soldered to seal it, and the individual leads may be sealed using separate glass seals to separate the leads from the metal.
  • a metal seal band attached by glassy material may be used to facilitate the sealing by welding or soldering, and the leads may be embedded in the ceramic itself.
  • Other types of packages and other sealing techniques at the packaging level may also be used.
  • a different and advantageous way to control the atmosphere in which a non-silicon-based device operates is to fabricate a seal at the wafer level (i.e. prior to separation of the die from the wafer) using integrated circuit manufacturing technology. Fabricating a seal at the wafer level has various advantages over doing so at the packaging level.
  • the sealed non-silicon-based device on the die can be tested on the wafer prior to dicing.
  • current die sizes for SAW devices are typically in the 1 to 1.5 mm range so that about 6000 to 7000 die may be fabricated on a single four inch wafer.
  • the wafer-level sealing of SAW devices allows for the identification and selection of devices that pass the acceptance testing before the die are separated from the wafer and so avoids the more cumbersome testing of individual die after the dicing and also avoids the subsequent packaging currently practiced.
  • a potential advantage is that the die so produced by sealing at the wafer level may be mountable on a printed circuit board (PCB) without further packaging.
  • PCB printed circuit board
  • Such direct mounting onto a PCB may be possible because the non- silicon-based device is sealed at the wafer level during the fabrication process.
  • Such direct mounting would avoid the additional costs and processing time associated with mounting in lead frames, wire bonding, and encapsulation. This may advantageously lead to production of the devices with higher quality, higher throughput, higher yield, and less expense.
  • Another potential advantage relates to compensating for thermal expansion of the non-silicon crystal. It is possible to compensate for thermal expansion by inducing a strain in the crystal using the seal structure.
  • the structural design and material used for the wafer-level seal may be used to induce such a strain.
  • the seal material would be chosen such that the material had a thermal coefficient-of- expansion (TCE) mismatch with the crystal.
  • TCE thermal coefficient-of- expansion
  • the structure would be designed so that the TCE mismatch would effectively produce a strain as a countervailing force against the normal thermal expansion of the crystal.
  • FIG. 1A is a cross-sectional diagram depicting an unsealed non-silicon-based device (in this instance, an SAW device) as fabricated on the surface of a wafer.
  • the unsealed SAW device includes a substrate 2 and transducer structures 4 and may be fabricated using conventional techniques.
  • the substrate 2 is typically a wafer of lithium tantalate, lithium niobate, or single crystal quartz. Such materials enable acoustic waves to travel substantially elastically across the surface of the substrate.
  • the transducer structures 4 are typically comprised of aluminum patterned into interdigitated electrode "fingers" and contacts for conducting electrical current to and from the structures 4. Typically, one of the transducer structures is for input and the other is for output. Wave propagation of interest occurs on the surface of the substrate 2 within the transducer structures 4 themselves and in the area between the transducer structures 4.
  • the SAW device may be used, for example, as a radio frequency (RF) filter. Many different device configurations may be used.
  • FIG. 1B, 1C, 1 D, 1 E, 1 F, 1G, 1 H and 11 are cross-sectional diagrams depicting various steps in the process of sealing the non-silicon-based device in accordance with an embodiment of the invention.
  • FIG. 1B is a cross-sectional diagram depicting the structure after the deposition of a sacrificial material 6.
  • the sacrificial material may be deposited as a (nearly) uniform coating of polysilicon.
  • the use of polysilicon as the sacrificial material 6 has an advantage that the deposition can be used to increase either the bulk or surface conductivity of SAW materials such as lithium niobate or lithium tantalate.
  • the sacrificial material may comprise amorphous silicon.
  • amorphous silicon may be deposited at a lower temperature than polysilicon.
  • the sacrificial material 6 may be a polymer material, such as polyimide, photoresist, or polymethyl methacrylate (PMMA). These polymer sacrificial materials may be attractive when low temperature processing is needed through the sealing process.
  • the polysilicon may be deposited at temperatures around 550 degrees
  • Amorphous silicon can be deposited at temperatures as low as 150 degrees Celsius and also may be dry etched in a highly selective manner using xenon difluoride gas.
  • FIG. 1C is a cross-sectional diagram depicting the structure after lithographic patterning of the sacrificial material 6.
  • the patterning removes undesired portions 8 of the sacrificial material while leaving remaining portions 10 of the sacrificial material.
  • the remaining sacrificial material 10 covers the portion of the SAW device to be sealed.
  • the remaining sacrificial material 10 should cover at least the wave propagation area of the SAW device because that area is to be kept clean of contamination.
  • the wave propagation area is generally between the two transducer structures 4 (as shown in FIG. 1A) as well as internal to a substantial portion of those structures 4, so FIG. 1C illustrates the remaining sacrificial material 10 as covering both the area between the transducer structures 4 and the wave propagation regions internal to those structures 4.
  • FIG. 1 D is a cross-sectional diagram depicting the structure after deposition of a seal coating 12.
  • the seal coating 12 may be deposited over the entire wafer and may comprise a relatively thick layer of, for example, a glassy material.
  • the glassy material may be, for example, a spin-on-glass or a sputtered glass.
  • the material may comprise silicon dioxide. Alternatively, the material may comprise silicon nitride or metal.
  • the seal coating 12 should be of a material and thickness so as to be impermeable to undesired contaminants. The proximity and electrical characteristics of these coatings must be considered in the design of the SAW device.
  • FIG. 1 E is a cross-sectional diagram depicting the structure after lithographic patterning of the seal coating 12.
  • the patterning removes portions 14 of the seal coating to expose the electrical contact pad portions of the transducers 4.
  • the patterning removes portions 16 of the seal coating to create vias (holes) through the seal coating to the sacrificial material below.
  • the vias are placed to avoid a wave propagation area of the SAW device.
  • FIG. 1 F is a cross-sectional diagram depicting the structure after etching away the remaining sacrificial material 10 by way of the via(s) to create a pocket 18 surrounded by a structure 20 of the seal coating.
  • the etching may be done by a dry etching process that does not leave undesirable residue.
  • the etching of a polysilicon (or amorphous silicon) sacrificial material on, for example, a lithium tantalate (or lithium niobate) wafer with a sealing layer of silicon dioxide (or silicon nitride or metal) may be accomplished by placing the wafer in a xenon-difluoride atmosphere.
  • the xenon- difluoride enters the vias and attacks the sacrificial material with high selectivity (i.e. leaving the substrate and sealing coating substantially un-etched).
  • the xenon- difuoride also removes the sacrificial material without leaving a substantial residue on the surface of the wafer. Leaving the acoustically active portion of the surface residue free prevents adverse alterations to wave propagation characteristics of the device.
  • a pocket is thereby formed between the seal coating structure 20 and the surface of the wafer in the region previously occupied by the remaining sacrificial material 10.
  • a different gas with similar characteristics to xenon- difluoride may be used to dry etch the sacrificial material.
  • FIG. 1G is a cross-sectional diagram depicting the structure after the wafer is placed in a target atmosphere. This may be done by placing the wafer in a sputtering, evaporating or other vacuum chamber pumped down to a target atmosphere.
  • the target atmosphere may comprise partial pressures of one or more target gases. The gas pressures in the chamber come to equilibrium across the vias 16 to attain the same gas pressures inside the pocket 22 as inside the chamber.
  • FIG. 1 H is a cross-sectional diagram depicting the structure after filling the via(s) 16 to seal the target atmosphere 22 in the pocket.
  • the vias (holes) 16 through the coating structure 20 may be filled 24, for example, by sputtering or evaporation of silicon dioxide or metal.
  • Sputtering when configured to be isotropic in nature, will fill in the vias 16 by coating the rims of the holes and building up material from the rims until the vias 16 are sealed.
  • the isotropic nature of sputtering will introduce some of the silicon dioxide or metal into the pocket.
  • the coating structure 20 may be designed such that the via(s) 16 are not over or are not in the vicinity of the wave propagation area. This is so that the amount of sputtered material that lands on the wave propagation area may be minimized or reduced to an insubstantial amount that only insignificantly affects the propagation of the surface acoustic waves.
  • evaporation may be used where the silicon dioxide or metal beam is positioned at an angle to the wafer. Evaporation tends to be highly directional in nature. By positioning the beam at a substantial angle to the wafer, the highly directional beam can fill 24 the vias 16 without introducing significant evaporated material into the pocket.
  • An additional advantage of evaporation is that a higher vacuum may be achieved in an evaporation chamber in comparison to a sputtering chamber.
  • the chosen gas and pressure are then locked into the pocket that is now sealed 24.
  • the sealed structure formed as described above should provide a hermetic seal.
  • a hermetic seal is substantially airtight in that it substantially keeps air or gas from getting in or out. However, even for a hermetic seal, small gas molecules will pass through slowly over time through diffusion and permeation.
  • the hermeticity of the seal can be substantially enhanced by coating it with a film of silicon nitride deposited using plasma-enhanced chemical vapor deposition (PECVD).
  • PECVD plasma-enhanced chemical vapor deposition
  • FIG. 11 is a cross-sectional diagram depicting the structure after electrodes (bumps) 26 have been formed on the contact portions of the transducer structures 4.
  • the electrodes 26 may be formed using conventional lithographic techniques. As depicted in FIG 11, the electrodes 26 are formed to be of a height that is greater than the height of the sealing structure. This makes the sealed device suitable for surface-mount soldering.
  • the devices Prior to mounting the sealed device onto the PCB board, the devices may be individually tested on the wafer and selected for acceptance or rejection. Thereafter, the wafer may be diced to produce individual die with the devices thereon. And the acceptable die may then be placed into a surface-mount-device tape-and-reel for subsequent surface-mount soldering onto a printed circuit board.
  • FIG. 2 is a flow chart depicting a method for sealing an active area of a non- silicon device (in this instance, a wave propagation area of a SAW device) on a wafer in accordance with an embodiment of the invention.
  • the method 100 includes nine steps (102, 104, 106, 108, 110, 112, 114, 116, and 118).
  • an unsealed device is fabricated on the wafer.
  • a cross- section of a fabricated SAW device before being sealed is illustrated in FIG. 1 A.
  • the unsealed device may be fabricated using conventional techniques on substrates such as lithium tantalate, lithium niobate, or quartz.
  • sacrificial material is deposited onto the wafer.
  • a cross-section after deposition of the sacrificial layer is illustrated in FIG. 1 B.
  • the sacrificial layer may comprise polysilicon, or amorphous silicon, or possibly a polymeric material.
  • the sacrificial layer is patterned using lithography.
  • a cross-section after sacrificial layer patterning is illustrated in FIG. 1C.
  • the remaining sacrificial material should cover at least the wave propagation area of the SAW device because that is the area to be sealed.
  • the seal coating is deposited onto the wafer.
  • a cross- section after seal coating deposition is illustrated in FIG. 1 D.
  • the seal coating may comprise a glassy material deposited by spin-on or sputtering.
  • the material may comprise silicon dioxide.
  • the material may comprise silicon nitride or metal.
  • the seal layer is patterned using lithography.
  • a cross- section after seal layer patterning is illustrated in FIG. 1 E. As described in relation to FIG. 1 E, the patterning exposes the electrical contact pad portions of the transducers 4. In addition, the patterning creates vias (holes) through the seal coating to the sacrificial material below.
  • the sacrificial material may be etched by way of the vias to create a pocket above the device.
  • a cross-section after etching the sacrificial material is illustrated in FIG.1 F. As described in relation to FIG. 1 F, the etching may be done by a dry etching process that does not leave undesirable residue.
  • the substrate is placed into a target atmosphere and allowed to equilibriate.
  • a cross-section after placement in the target atmosphere is illustrated in FIG.1G.
  • the gas pressures in the chamber come to equilibrium across the vias to attain the same gas pressures inside the pocket as inside the chamber.
  • the vias are filled to seal the pocket. This step is performed while the wafer is still in the target atmosphere. A cross-section after the vias are filled is illustrated in FIG. 1 H. As described in relation to FIG. 1 H, the vias may be filled, for example, by sputtering or evaporation of silicon dioxide or metal.
  • electrodes 26 are built upon the contacts.
  • a cross-section after the vias are filled is illustrated in FIG. 11.
  • the electrodes 26 are formed to be of a height that is greater than the height of the sealing structure so as to make the sealed device suitable for surface- mount soldering.
  • the ninth step 118 other steps may be performed to mount the device onto a printed circuit board (PCB).
  • the devices may be individually tested on the wafer, the wafer may be diced to produce individual die, and the acceptable die may then be placed into a surface-mount-device tape-and- reel for subsequent surface-mount soldering onto the PCB.
  • PCB printed circuit board
  • non-silicon-based devices may be lithographically constructed to include a means for receiving a signal in electrical form, a means for applying the signal to an active area of the substrate, and a means for hermetically sealing the active area without impeding receiving of the electrical signal.
  • the active area to be protected would, of course, correspond to the wave propagation area.
  • the technique may also be applicable to other near-surface devices.
  • Near-surface devices include, for example, acoustic, optic, non-linear optic, electro-optic, acoustic-optic, and other devices.

Abstract

One embodiment disclosed relates to a method (100) for sealing an active area of a non-silicon-based device on a wafer. The method includes providing (104) a sacrificial material over at least the active area of the non-silicon-based device, depositing (108) a seal coating over the wafer so that the seal coating covers the sacrificial material, and replacing (112, 114) the sacrificial material with a target atmosphere. Another embodiment disclosed relates to an SAW device sealed at the wafer level (i.e. prior to separation of the die from the wafer). The device includes an active area to be protected, an electrical contact area (4), and a lithographically-formed structure (24) sealing at least the active area and leaving at least a portion of the electrical contact area (4) exposed.

Description

WAFER-LEVEL SEAL FOR NON-SILICON-BASED DEVICES
Inventors: Gregory D. Miller, Mike Bruner, Lawrence Ragan, and Gary Green
REFERENCE TO RELATED APPLICATION
The present application claims priority to U.S. patent application no. 10/231 ,357, filed August 28, 2002, entitled "Wafer-Level Seal for Non-Silicon-Based Devices," and also claims priority to U.S. patent application no. 10/231 ,356, filed August 28, 2002, entitled "Seal for Surface Acoustic Wave Devices."
BACKGROUND OF THE INVENTION
1. Field Of The Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.
2. Description Of The Background Art
Various non-silicon-based devices are being manufactured for use in communications and other applications. Such devices are often sensitive to contamination or to the atmosphere in which they operate, and hence it is desirable for them to operate in a controlled atmosphere. Examples of these atmosphere- sensitive non-silicon-based devices include surface acoustic wave (SAW) devices, electro-optic modulators, acoustic-optic devices, and so on.
For example, let us consider SAW devices in more detail. SAW devices are often used in communication devices, such as, for instance, radio frequency (RF) filters in mobile phone handsets and communication networks. SAW devices utilize waves that propagate along the surface (or near surface) of a substrate. As used herein, SAW devices include those that utilize piezoelectrically-coupled Rayleigh waves and may also include those that utilize non-Rayleigh (skimming or "leaky") waves. A typical SAW filter includes input and output transducers formed on a non- silicon-based piezoelectric substrate, such as, for example, lithium tantalate, lithium niobate, or single crystal quartz. The transducers may be metallic electrodes, for example, interleaved aluminum fingers. As an example of the size of a typical SAW device, one operating at 2.5 GHz may have a minimum feature size of approximately 0.4 microns for the aluminum fingers of the transducers.
One problem encountered with SAW devices is that the regions of the device where the acoustic waves are present can be very sensitive to the presence of surface contaminants that alter the wave velocities and consequently degrade the device performance. Even a monolayer of contaminant on the surface of the crystal can noticeably alter the device performance. Also, it is desirable for the SAW devices to operate in a low pressure (near vacuum) atmosphere, rather than in atmospheric air. Operating in such a low pressure atmosphere can decrease the viscous damping of the acoustic waves. Another problem associated with SAW devices is that a change in acoustic wave velocity is temperature dependent. In other words, a temperature change can change the velocity of the acoustic waves. This temperature dependence effectively limits the operable temperature range of SAW devices.
SUMMARY
One embodiment of the invention relates to a method for sealing an active area of a non-silicon-based device on a wafer. The method includes providing a sacrificial material over at least the active area of the non-silicon-based device, depositing a seal coating over the wafer so that the seal coating covers the sacrificial material, and replacing the sacrificial material with a target atmosphere.
Another embodiment of the invention relates to a non-silicon-based device sealed at the wafer level (i.e. prior to separation of the die from the wafer). The device includes an active area to be protected, a contact area, and a lithographically- formed structure sealing at least the active area and leaving at least a portion of the contact area exposed.
Another embodiment of the invention relates to a method for sealing an active area of an SAW device on a wafer. The method includes providing a sacrificial material over at least the active area of the SAW device, depositing a seal coating over the wafer so that the seal coating covers the sacrificial material, and replacing the sacrificial material with a target atmosphere.
Another embodiment of the invention relates to an SAW device sealed at the wafer level (i.e. prior to separation of the die from the wafer). . The device includes an active area to be protected, an electrical contact area, and a lithographically- formed structure sealing at least the active area and leaving at least a portion of the electrical contact area exposed.
These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a cross-sectional diagram depicting an unsealed non-silicon-based device (in this instance, an SAW device) as fabricated on the surface of a wafer. FIG. 1 B, 1C, 1 D, 1 E, 1F, 1G, 1 H and 11 are cross-sectional diagrams depicting various steps in the process of sealing the non-silicon-based device in accordance with an embodiment of the invention.
FIG. 2 is a flow chart depicting a method for sealing an active area of a non- silicon device (in this instance, a wave propagation area of a SAW device) on a wafer in accordance with an embodiment of the invention.
The use of the same reference label in different drawings indicates the same or like components. Drawings are not to scale unless otherwise noted.
DETAILED DESCRIPTION
The above described problems and difficulties with non-silicon-based devices may be overcome by controlling the atmosphere in which the devices operate.
One way to achieve this would be to seal the devices on the packaging level during packaging of the individual die. Seals may be formed, for example, in metal or ceramic packages. For instance, a metal package may be welded or soldered to seal it, and the individual leads may be sealed using separate glass seals to separate the leads from the metal. As another example, in ceramic packages, a metal seal band attached by glassy material may be used to facilitate the sealing by welding or soldering, and the leads may be embedded in the ceramic itself. Other types of packages and other sealing techniques at the packaging level may also be used.
As disclosed in detail in the present application, a different and advantageous way to control the atmosphere in which a non-silicon-based device operates is to fabricate a seal at the wafer level (i.e. prior to separation of the die from the wafer) using integrated circuit manufacturing technology. Fabricating a seal at the wafer level has various advantages over doing so at the packaging level.
One advantage is that the sealed non-silicon-based device on the die can be tested on the wafer prior to dicing. For example, current die sizes for SAW devices are typically in the 1 to 1.5 mm range so that about 6000 to 7000 die may be fabricated on a single four inch wafer. The wafer-level sealing of SAW devices allows for the identification and selection of devices that pass the acceptance testing before the die are separated from the wafer and so avoids the more cumbersome testing of individual die after the dicing and also avoids the subsequent packaging currently practiced.
In addition, a potential advantage is that the die so produced by sealing at the wafer level may be mountable on a printed circuit board (PCB) without further packaging. Such direct mounting onto a PCB may be possible because the non- silicon-based device is sealed at the wafer level during the fabrication process. Such direct mounting would avoid the additional costs and processing time associated with mounting in lead frames, wire bonding, and encapsulation. This may advantageously lead to production of the devices with higher quality, higher throughput, higher yield, and less expense.
Another potential advantage relates to compensating for thermal expansion of the non-silicon crystal. It is possible to compensate for thermal expansion by inducing a strain in the crystal using the seal structure. The structural design and material used for the wafer-level seal may be used to induce such a strain. The seal material would be chosen such that the material had a thermal coefficient-of- expansion (TCE) mismatch with the crystal. The structure would be designed so that the TCE mismatch would effectively produce a strain as a countervailing force against the normal thermal expansion of the crystal.
In the present disclosure, numerous specific details are provided such as examples of apparatus, process parameters, materials, process steps, and structures to provide a thorough understanding of embodiments of the invention. Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.
FIG. 1A is a cross-sectional diagram depicting an unsealed non-silicon-based device (in this instance, an SAW device) as fabricated on the surface of a wafer. The unsealed SAW device includes a substrate 2 and transducer structures 4 and may be fabricated using conventional techniques. The substrate 2 is typically a wafer of lithium tantalate, lithium niobate, or single crystal quartz. Such materials enable acoustic waves to travel substantially elastically across the surface of the substrate. The transducer structures 4 are typically comprised of aluminum patterned into interdigitated electrode "fingers" and contacts for conducting electrical current to and from the structures 4. Typically, one of the transducer structures is for input and the other is for output. Wave propagation of interest occurs on the surface of the substrate 2 within the transducer structures 4 themselves and in the area between the transducer structures 4. The SAW device may be used, for example, as a radio frequency (RF) filter. Many different device configurations may be used.
FIG. 1B, 1C, 1 D, 1 E, 1 F, 1G, 1 H and 11 are cross-sectional diagrams depicting various steps in the process of sealing the non-silicon-based device in accordance with an embodiment of the invention. FIG. 1B is a cross-sectional diagram depicting the structure after the deposition of a sacrificial material 6. In one embodiment, the sacrificial material may be deposited as a (nearly) uniform coating of polysilicon. The use of polysilicon as the sacrificial material 6 has an advantage that the deposition can be used to increase either the bulk or surface conductivity of SAW materials such as lithium niobate or lithium tantalate. This is due to a chemical reduction process that is known to occur when these substrates are heated in vacuum. Also this chemical reduction process can occur at the interface between a readily-oxidized material such as silicon, thereby producing a thin skin of chemically reduced material having increased conductivity. This increased conductivity can be valuable in suppressing the build up of charge on these substantially insulating substrates which occurs due to a pyroelectric effect. Conventional lithium tantalate can build up thousands of volts of pyroelectrically-induced charge during temperature changes, and this built- up charge can potentially degrade the SAW performance through damage to the transducer structures or the formation of microscopic domains of reversed crystal orientation in the SAW active area, or can potentially damage sensitive electronic components or damage the wafer, even to the point of fracture (because the pyroelectrically-induced voltage may exceed the breakdown voltage of the wafer material). Consequently, using polysilicon sacrificial layers in fabricating SAW devices may result in devices with superior resistance to these deleterious pyroelectric effects.
In another embodiment, the sacrificial material may comprise amorphous silicon. Advantageously, amorphous silicon may be deposited at a lower temperature than polysilicon. In yet another embodiment, the sacrificial material 6 may be a polymer material, such as polyimide, photoresist, or polymethyl methacrylate (PMMA). These polymer sacrificial materials may be attractive when low temperature processing is needed through the sealing process. However, they may have the following disadvantages: (a) difficulty of removing material from within a pocket with significant lateral dimensions due to the directional nature of plasma etching; (b) impurities that do not react and thereby leave a residue (may not be an issue with PMMA); and (c) formation of water molecules that adsorb to the surfaces inside the pocket and may prevent hermeticity due to the moisture.
The polysilicon may be deposited at temperatures around 550 degrees
Celsius, below the Curie temperature of lithium tantalate, and therefore is a candidate material to use as the sacrificial material. Materials with deposition temperatures above the Curie temperature of the substrate (about 600 degrees Celsius for congruent lithium tantalate or about 695 degrees Celsius for stoichiometric lithium tantalate) would not make good candidates for use as the sacrificial material as their high temperatures would adversely affect the substrate material. Amorphous silicon can be deposited at temperatures as low as 150 degrees Celsius and also may be dry etched in a highly selective manner using xenon difluoride gas.
FIG. 1C is a cross-sectional diagram depicting the structure after lithographic patterning of the sacrificial material 6. The patterning removes undesired portions 8 of the sacrificial material while leaving remaining portions 10 of the sacrificial material. The remaining sacrificial material 10 covers the portion of the SAW device to be sealed. In particular, the remaining sacrificial material 10 should cover at least the wave propagation area of the SAW device because that area is to be kept clean of contamination. The wave propagation area is generally between the two transducer structures 4 (as shown in FIG. 1A) as well as internal to a substantial portion of those structures 4, so FIG. 1C illustrates the remaining sacrificial material 10 as covering both the area between the transducer structures 4 and the wave propagation regions internal to those structures 4.
FIG. 1 D is a cross-sectional diagram depicting the structure after deposition of a seal coating 12. The seal coating 12 may be deposited over the entire wafer and may comprise a relatively thick layer of, for example, a glassy material. The glassy material may be, for example, a spin-on-glass or a sputtered glass. The material may comprise silicon dioxide. Alternatively, the material may comprise silicon nitride or metal. The seal coating 12 should be of a material and thickness so as to be impermeable to undesired contaminants. The proximity and electrical characteristics of these coatings must be considered in the design of the SAW device.
FIG. 1 E is a cross-sectional diagram depicting the structure after lithographic patterning of the seal coating 12. The patterning removes portions 14 of the seal coating to expose the electrical contact pad portions of the transducers 4. In addition, the patterning removes portions 16 of the seal coating to create vias (holes) through the seal coating to the sacrificial material below. In a preferred embodiment, the vias are placed to avoid a wave propagation area of the SAW device.
FIG. 1 F is a cross-sectional diagram depicting the structure after etching away the remaining sacrificial material 10 by way of the via(s) to create a pocket 18 surrounded by a structure 20 of the seal coating. The etching may be done by a dry etching process that does not leave undesirable residue. For example, in one embodiment, the etching of a polysilicon (or amorphous silicon) sacrificial material on, for example, a lithium tantalate (or lithium niobate) wafer with a sealing layer of silicon dioxide (or silicon nitride or metal) may be accomplished by placing the wafer in a xenon-difluoride atmosphere. The xenon- difluoride enters the vias and attacks the sacrificial material with high selectivity (i.e. leaving the substrate and sealing coating substantially un-etched). The xenon- difuoride also removes the sacrificial material without leaving a substantial residue on the surface of the wafer. Leaving the acoustically active portion of the surface residue free prevents adverse alterations to wave propagation characteristics of the device. A pocket is thereby formed between the seal coating structure 20 and the surface of the wafer in the region previously occupied by the remaining sacrificial material 10. Alternatively, a different gas with similar characteristics to xenon- difluoride may be used to dry etch the sacrificial material.
FIG. 1G is a cross-sectional diagram depicting the structure after the wafer is placed in a target atmosphere. This may be done by placing the wafer in a sputtering, evaporating or other vacuum chamber pumped down to a target atmosphere. The target atmosphere may comprise partial pressures of one or more target gases. The gas pressures in the chamber come to equilibrium across the vias 16 to attain the same gas pressures inside the pocket 22 as inside the chamber.
FIG. 1 H is a cross-sectional diagram depicting the structure after filling the via(s) 16 to seal the target atmosphere 22 in the pocket. The vias (holes) 16 through the coating structure 20 may be filled 24, for example, by sputtering or evaporation of silicon dioxide or metal.
Sputtering, when configured to be isotropic in nature, will fill in the vias 16 by coating the rims of the holes and building up material from the rims until the vias 16 are sealed. The isotropic nature of sputtering will introduce some of the silicon dioxide or metal into the pocket. If the sputtered material lands on the region to be occupied by the surface acoustic wave, the propagation properties of the acoustic wave may be altered in a detrimental manner. To avoid this detrimental effect, the coating structure 20 may be designed such that the via(s) 16 are not over or are not in the vicinity of the wave propagation area. This is so that the amount of sputtered material that lands on the wave propagation area may be minimized or reduced to an insubstantial amount that only insignificantly affects the propagation of the surface acoustic waves.
Alternatively, evaporation may be used where the silicon dioxide or metal beam is positioned at an angle to the wafer. Evaporation tends to be highly directional in nature. By positioning the beam at a substantial angle to the wafer, the highly directional beam can fill 24 the vias 16 without introducing significant evaporated material into the pocket. An additional advantage of evaporation is that a higher vacuum may be achieved in an evaporation chamber in comparison to a sputtering chamber.
As depicted in FIG. 1 H, the chosen gas and pressure are then locked into the pocket that is now sealed 24. This advantageously provides a controlled atmosphere for the acoustically active portion of the device and protects that portion from undesirable contamination. The sealed structure formed as described above should provide a hermetic seal. A hermetic seal is substantially airtight in that it substantially keeps air or gas from getting in or out. However, even for a hermetic seal, small gas molecules will pass through slowly over time through diffusion and permeation. The hermeticity of the seal can be substantially enhanced by coating it with a film of silicon nitride deposited using plasma-enhanced chemical vapor deposition (PECVD).
FIG. 11 is a cross-sectional diagram depicting the structure after electrodes (bumps) 26 have been formed on the contact portions of the transducer structures 4. The electrodes 26 may be formed using conventional lithographic techniques. As depicted in FIG 11, the electrodes 26 are formed to be of a height that is greater than the height of the sealing structure. This makes the sealed device suitable for surface-mount soldering.
Prior to mounting the sealed device onto the PCB board, the devices may be individually tested on the wafer and selected for acceptance or rejection. Thereafter, the wafer may be diced to produce individual die with the devices thereon. And the acceptable die may then be placed into a surface-mount-device tape-and-reel for subsequent surface-mount soldering onto a printed circuit board.
FIG. 2 is a flow chart depicting a method for sealing an active area of a non- silicon device (in this instance, a wave propagation area of a SAW device) on a wafer in accordance with an embodiment of the invention. As depicted in FIG. 2, the method 100 includes nine steps (102, 104, 106, 108, 110, 112, 114, 116, and 118).
In the first step 102, an unsealed device is fabricated on the wafer. A cross- section of a fabricated SAW device before being sealed is illustrated in FIG. 1 A. As described in relation to FIG. 1A, the unsealed device may be fabricated using conventional techniques on substrates such as lithium tantalate, lithium niobate, or quartz.
In the second step 104, sacrificial material is deposited onto the wafer. A cross-section after deposition of the sacrificial layer is illustrated in FIG. 1 B. As described in relation to FIG. 1 B, the sacrificial layer may comprise polysilicon, or amorphous silicon, or possibly a polymeric material.
In the third step 106, the sacrificial layer is patterned using lithography. A cross-section after sacrificial layer patterning is illustrated in FIG. 1C. As described in relation to FIG. 1C, the remaining sacrificial material should cover at least the wave propagation area of the SAW device because that is the area to be sealed.
In the fourth step 108, the seal coating is deposited onto the wafer. A cross- section after seal coating deposition is illustrated in FIG. 1 D. As described in relation to FIG. 1 D, the seal coating may comprise a glassy material deposited by spin-on or sputtering. The material may comprise silicon dioxide. Alternatively, the material may comprise silicon nitride or metal.
In the fifth step 110, the seal layer is patterned using lithography. A cross- section after seal layer patterning is illustrated in FIG. 1 E. As described in relation to FIG. 1 E, the patterning exposes the electrical contact pad portions of the transducers 4. In addition, the patterning creates vias (holes) through the seal coating to the sacrificial material below.
In the sixth step 112, the sacrificial material may be etched by way of the vias to create a pocket above the device. A cross-section after etching the sacrificial material is illustrated in FIG.1 F. As described in relation to FIG. 1 F, the etching may be done by a dry etching process that does not leave undesirable residue.
In the seventh step 114, the substrate is placed into a target atmosphere and allowed to equilibriate. A cross-section after placement in the target atmosphere is illustrated in FIG.1G. As described in relation to FIG. 1G, the gas pressures in the chamber come to equilibrium across the vias to attain the same gas pressures inside the pocket as inside the chamber.
In the eighth step 116, the vias (holes) are filled to seal the pocket. This step is performed while the wafer is still in the target atmosphere. A cross-section after the vias are filled is illustrated in FIG. 1 H. As described in relation to FIG. 1 H, the vias may be filled, for example, by sputtering or evaporation of silicon dioxide or metal.
Finally, in the ninth step 118, electrodes 26 are built upon the contacts. A cross-section after the vias are filled is illustrated in FIG. 11. As described in relation to FIG. 11, the electrodes 26 are formed to be of a height that is greater than the height of the sealing structure so as to make the sealed device suitable for surface- mount soldering.
Subsequent to the ninth step 118, other steps may be performed to mount the device onto a printed circuit board (PCB). For example, the devices may be individually tested on the wafer, the wafer may be diced to produce individual die, and the acceptable die may then be placed into a surface-mount-device tape-and- reel for subsequent surface-mount soldering onto the PCB.
Although the above description focuses on a wafer-level seal for SAW devices, the technique may be applied to protect at the wafer level other devices employing non-silicon-based materials with an active area to protect. Such applications include a high dielectric strength vacuum insulation for domain patterning in ferroelectrics (such as lithium tantalate or lithium niobate), electro-optic modulators (for example, based as lithium tantalate or lithium niobate), and integrated optic structures. In each of these applications, non-silicon-based devices may be lithographically constructed to include a means for receiving a signal in electrical form, a means for applying the signal to an active area of the substrate, and a means for hermetically sealing the active area without impeding receiving of the electrical signal. For an SAW device, the active area to be protected would, of course, correspond to the wave propagation area. The technique may also be applicable to other near-surface devices. Near-surface devices include, for example, acoustic, optic, non-linear optic, electro-optic, acoustic-optic, and other devices.
While specific embodiments of the present invention have been provided, it is to be understood that these embodiments are for illustration purposes and not limiting. Many additional embodiments will be apparent to persons of ordinary skill in the art reading this disclosure. Thus, the present invention is limited only by the following claims.

Claims

CLAIMSWhat is claimed is:
1. A method for sealing an active area of a non-silicon-based device on a wafer, the method comprising:
providing a sacrificial material over at least the active area of the non-silicon- based device;
depositing a seal coating over the wafer so that the seal coating covers the sacrificial material; and
replacing the sacrificial material with a target atmosphere.
2. The method of claim 1 , wherein the seal coating is of a sufficient impermeability so as to hermetically seal the target atmosphere within a pocket.
3. The method of claim 1 , wherein providing the sacrificial material comprises:
depositing the sacrificial material over the wafer; and
lithographically patterning the sacrificial material so that the sacrificial material is over at least the active area of the non-silicon-based device.
4. The method of claim 1 , wherein the sacrificial material comprises a material from a group of materials consisting of polysilicon, amorphous silicon, and polymeric material.
5. The method of claim 1 , wherein the seal coating comprises a material from a group of materials consisting of silicon dioxide, silicon nitride, or metal.
6. The method of claim 1 , wherein the seal coating comprises a glassy material.
7. The method of claim 6, wherein the glassy material is from a group of glassy materials consisting of spin-on-glass and sputtered glass.
8. The method of claim 1 , wherein replacing the sacrificial material comprises:
lithographically patterning the seal coating to create a via through the seal coating and to expose electrical contact pads for the non-silicon-based device;
etching a sacrificial material by way of the via to create a pocket surrounded by the seal coating;
placing the wafer in the target atmosphere; and
filling the via to seal the target atmosphere in the pocket.
9. The method of claim 8, wherein etching the sacrificial material comprises an etching process that does not leave substantial residue.
10. The method of claim 9, wherein the sacrificial material comprises a silicon-based material, and wherein the etching process comprises placing the wafer in a xenon-difluoride atmosphere to dry etch the silicon-based material.
11. The method of claim 8, further comprising:
allowing an atmosphere in the pocket to equilibriate with the target atmosphere prior to filling the via.
12. The method of claim 8, wherein filling the via comprises sputtering of a fill material until the via is filled, and wherein the via is placed to avoid the active area of the non-silicon-based device.
13. The method of claim 8, wherein filling the via comprises evaporating a fill material until the via is filled, and wherein an angle between evaporating beam and wafer surface is sufficiently low to avoid introducing a substantial amount of the fill material into the pocket.
14. The method of claim 1 , further comprising:
building up electrodes connected to contact pads of the non-silicon-based device.
15. The method of claim 14, wherein the wafer is subsequently diced to produce individual die and acceptable die are placed into a surface-mount-device tape-and-reel for subsequent printed circuit board mounting.
16. The method of claim 1 , wherein the active area comprises a wave propagation area of the non-silicon-based device.
17. A non-silicon-based device sealed at the wafer level, the device comprising:
an active area to be protected;
a contact area; and
a lithographically-formed structure sealing at least the active area and leaving at least a portion of the contact area exposed.
18. The device of claim 17, wherein the lithographically-formed structure comprises a glassy material.
19. The device of claim 17, wherein the non-silicon-based device is fabricated on a substrate from a group of substrates consisting of lithium tantalate, lithium niobate, and quartz.
20. A lithographically-fabricated non-silicon-based device, the non-silicon- based device comprising: an active area of the non-silicon-based device that is atmospherically sensitive; and
a wafer-level means for sealing the active area of the non-silicon-based device.
21. A method for sealing an active area of a surface acoustic wave (SAW) device on a wafer, the method comprising:
providing a sacrificial material over at least the active area of the SAW device;
depositing a seal coating over the wafer so that the seal coating covers the sacrificial material; and
replacing the sacrificial material with a target atmosphere.
22. The method of claim 21 , wherein the seal coating is of a sufficient impermeability so as to hermetically seal the target atmosphere within a pocket.
23. The method of claim 21 , wherein providing the sacrificial material comprises:
depositing the sacrificial material over the wafer; and
lithographically patterning the sacrificial material so that the sacrificial material is over at least the active area of the SAW device.
24. The method of claim 21 , wherein the sacrificial material comprises a material from a group of materials consisting of polysilicon, amorphous silicon, and polymeric material.
25. The method of claim 21 , wherein the seal coating comprises a material from a group of materials consisting of silicon dioxide, silicon nitride, or metal.
26. The method of claim 21 , wherein the seal coating comprises a glassy material.
27. The method of claim 26, wherein the glassy material is from a group of glassy materials consisting of spin-on-glass and sputtered glass.
28. The method of claim 21 , wherein replacing the sacrificial material comprises:
lithographically patterning the seal coating to create a via through the seal coating and to expose electrical contact pads for the SAW device;
etching a sacrificial material by way of the via to create a pocket surrounded by the seal coating;
placing the wafer in the target atmosphere; and
filling the via to seal the target atmosphere in the pocket.
29. The method of claim 28, wherein etching the sacrificial material comprises an etching process that does not leave substantial residue.
30. The method of claim 29, wherein the sacrificial material comprises a silicon-based material, and wherein the etching process comprises placing the wafer in a xenon-difluoride atmosphere to dry etch the silicon-based material.
31. The method of claim 28, further comprising:
allowing an atmosphere in the pocket to equilibriate with the target atmosphere prior to filling the via.
32. The method of claim 28, wherein filling the via comprises sputtering of a fill material until the via is filled, and wherein the via is placed to avoid the active area of the SAW device.
33. The method of claim 28, wherein filling the via comprises evaporating a fill material until the via is filled, and wherein an angle between evaporating beam and wafer surface is sufficiently low to avoid introducing a substantial amount of the fill material into the pocket.
34. The method of claim 21 , further comprising:
building up electrodes connected to contact pads of the SAW device.
35. The method of claim 34, wherein the wafer is subsequently diced to produce individual die and acceptable die are placed into a surface-mount-device tape-and-reel for subsequent printed circuit board mounting.
36. The method of claim 21 , wherein the active area comprises a wave propagation area of the SAW device.
37. A surface acoustic wave (SAW) device sealed at the wafer level, the device comprising:
an active area to be protected;
an electrical contact area; and
a lithographically-formed structure sealing at least the active area and leaving at least a portion of the electrical contact area exposed.
38. The device of claim 37, wherein the lithographically-formed structure comprises a glassy material.
39. The device of claim 37, wherein the SAW device is fabricated on a substrate from a group of substrates consisting of lithium tantalate, lithium niobate, and quartz.
40. A lithographically-fabricated surface acoustic wave (SAW) device, the SAW device comprising:
means for carrying a surface acoustic wave; and
a wafer-level means for sealing the means for carrying the surface acoustic wave.
PCT/US2003/018103 2002-08-28 2003-06-09 Wafer-level seal for non-silicon-based devices WO2004021398A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP03791559A EP1540736A4 (en) 2002-08-28 2003-06-09 Wafer-level seal for non-silicon-based devices
JP2004532581A JP2005537661A (en) 2002-08-28 2003-06-09 Sealing of non-silicon-based devices at the wafer stage
AU2003243451A AU2003243451A1 (en) 2002-08-28 2003-06-09 Wafer-level seal for non-silicon-based devices

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/231,356 2002-08-28
US10/231,357 2002-08-28
US10/231,356 US6877209B1 (en) 2002-08-28 2002-08-28 Method for sealing an active area of a surface acoustic wave device on a wafer
US10/231,357 US6846423B1 (en) 2002-08-28 2002-08-28 Wafer-level seal for non-silicon-based devices

Publications (2)

Publication Number Publication Date
WO2004021398A2 true WO2004021398A2 (en) 2004-03-11
WO2004021398A3 WO2004021398A3 (en) 2004-06-03

Family

ID=31980954

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/018103 WO2004021398A2 (en) 2002-08-28 2003-06-09 Wafer-level seal for non-silicon-based devices

Country Status (5)

Country Link
EP (1) EP1540736A4 (en)
JP (1) JP2005537661A (en)
KR (1) KR20050044799A (en)
AU (1) AU2003243451A1 (en)
WO (1) WO2004021398A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005099088A1 (en) * 2004-03-26 2005-10-20 Cypress Semiconductor Corp. Integrated circuit having one or more conductive devices formed over a saw and/or mems device
EP2316789A1 (en) * 2009-11-03 2011-05-04 Nxp B.V. Device with microstructure and method of forming such a device
US9021669B2 (en) 2006-08-07 2015-05-05 Kyocera Corporation Method for manufacturing surface acoustic wave apparatus
US11631586B2 (en) 2012-08-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Heterogeneous annealing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5777422A (en) * 1995-09-29 1998-07-07 Sumitomo Electric Industries, Ltd. Diamond-ZnO surface acoustic wave device having relatively thinner ZnO piezoelectric layer
US6310420B1 (en) * 1995-12-21 2001-10-30 Siemens Aktiengesellschaft Electronic component in particular an saw component operating with surface acoustic waves and a method for its production
US6509623B2 (en) * 2000-06-15 2003-01-21 Newport Fab, Llc Microelectronic air-gap structures and methods of forming the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS558191A (en) * 1978-07-05 1980-01-21 Nec Corp Elastic surface wave device
JPH01213018A (en) * 1988-02-22 1989-08-25 Fujitsu Ltd Structure of surface acoustic wave device
JPH09172339A (en) * 1995-12-19 1997-06-30 Kokusai Electric Co Ltd Surface acoustic wave device and manufacture of the same
JP2000114918A (en) * 1998-10-05 2000-04-21 Mitsubishi Electric Corp Surface acoustic wave device and its manufacture
JP2001053178A (en) * 1999-06-02 2001-02-23 Japan Radio Co Ltd Electronic component with electronic circuit device sealed and mounted on circuit board, and manufacture of the electronic component
DE69933380T2 (en) * 1999-12-15 2007-08-02 Asulab S.A. Method for hermetically encapsulating microsystems on site

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5777422A (en) * 1995-09-29 1998-07-07 Sumitomo Electric Industries, Ltd. Diamond-ZnO surface acoustic wave device having relatively thinner ZnO piezoelectric layer
US6310420B1 (en) * 1995-12-21 2001-10-30 Siemens Aktiengesellschaft Electronic component in particular an saw component operating with surface acoustic waves and a method for its production
US6509623B2 (en) * 2000-06-15 2003-01-21 Newport Fab, Llc Microelectronic air-gap structures and methods of forming the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1540736A2 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005099088A1 (en) * 2004-03-26 2005-10-20 Cypress Semiconductor Corp. Integrated circuit having one or more conductive devices formed over a saw and/or mems device
US7750420B2 (en) 2004-03-26 2010-07-06 Cypress Semiconductor Corporation Integrated circuit having one or more conductive devices formed over a SAW and/or MEMS device
US9021669B2 (en) 2006-08-07 2015-05-05 Kyocera Corporation Method for manufacturing surface acoustic wave apparatus
US9882540B2 (en) 2006-08-07 2018-01-30 Kyocera Corporation Method for manufacturing surface acoustic wave apparatus
EP2316789A1 (en) * 2009-11-03 2011-05-04 Nxp B.V. Device with microstructure and method of forming such a device
CN102050417A (en) * 2009-11-03 2011-05-11 Nxp股份有限公司 Device with microstructure and method of forming such a device
CN102050417B (en) * 2009-11-03 2012-07-25 Nxp股份有限公司 Device with microstructure and method of forming such a device
US8426928B2 (en) 2009-11-03 2013-04-23 Nxp B.V. Device with microstructure and method of forming such a device
US11631586B2 (en) 2012-08-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Heterogeneous annealing method

Also Published As

Publication number Publication date
JP2005537661A (en) 2005-12-08
AU2003243451A1 (en) 2004-03-19
EP1540736A4 (en) 2006-03-08
EP1540736A2 (en) 2005-06-15
AU2003243451A8 (en) 2004-03-19
KR20050044799A (en) 2005-05-12
WO2004021398A3 (en) 2004-06-03

Similar Documents

Publication Publication Date Title
US6877209B1 (en) Method for sealing an active area of a surface acoustic wave device on a wafer
US7750420B2 (en) Integrated circuit having one or more conductive devices formed over a SAW and/or MEMS device
US7045459B2 (en) Thin film encapsulation of MEMS devices
US6828713B2 (en) Resonator with seed layer
TWI239319B (en) Packaging microelectromechanical structures
EP2267895B1 (en) Electronic component, circuit board, electronic apparatus, and method for manufacturing the electronic component
EP1973228B1 (en) Method for manufacturing surface acoustic wave device and surface acoustic wave device
US7466022B2 (en) Wafer-level seal for non-silicon-based devices
US20070052324A1 (en) Surface acoustic wave device and method for fabricating the same
WO2013019515A1 (en) Metal thin shield on electrical device
US20040021529A1 (en) Resonator with protective layer
US20060234476A1 (en) Electronic component and method for its production
CN112039456A (en) Packaging method and packaging structure of bulk acoustic wave resonator
JP2002016466A (en) Surface acoustic wave device and producing method therefor
WO2004021398A2 (en) Wafer-level seal for non-silicon-based devices
CN100525097C (en) Electronic component and method for manufacturing the same
US11706987B2 (en) Semiconductor device and method of forming a semiconductor device
US8268660B2 (en) Process for fabricating micromachine
JP4608993B2 (en) Micro electromechanical element, method for manufacturing the same, and electronic apparatus
CN114337585A (en) Single crystal film bulk acoustic resonator, preparation method thereof and filter
JP2002299984A (en) Production method for surface acoustic wave device
JPH08125478A (en) Manufacture of surface acoustic wave element

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1020057003297

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2004532581

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2003791559

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 20038237172

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 1020057003297

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2003791559

Country of ref document: EP