WO2004019534A3 - Method and system for multiplication of binary numbers - Google Patents

Method and system for multiplication of binary numbers Download PDF

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Publication number
WO2004019534A3
WO2004019534A3 PCT/IB2003/004524 IB0304524W WO2004019534A3 WO 2004019534 A3 WO2004019534 A3 WO 2004019534A3 IB 0304524 W IB0304524 W IB 0304524W WO 2004019534 A3 WO2004019534 A3 WO 2004019534A3
Authority
WO
WIPO (PCT)
Prior art keywords
signal
multiplication
binary numbers
lowbar
port
Prior art date
Application number
PCT/IB2003/004524
Other languages
French (fr)
Other versions
WO2004019534A2 (en
Inventor
Clemens M Zierhofer
Original Assignee
Med El Elektromed Geraete Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Med El Elektromed Geraete Gmbh filed Critical Med El Elektromed Geraete Gmbh
Priority to AU2003269332A priority Critical patent/AU2003269332A1/en
Publication of WO2004019534A2 publication Critical patent/WO2004019534A2/en
Publication of WO2004019534A3 publication Critical patent/WO2004019534A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even

Abstract

A multiplier for multiplying a first signal representing a first binary number a = [aN_1 ... al ao] and a second signal representing a second binary number b = [bN_1 ... bl bo]. The multiplier includes a first port for receiving the first signal, and a second port for receiving the second signal. A triangle array is operatively coupled to the first signal and the second signal. An adder adds elements of the triangle array to produce a third signal representing a product of the first signal and the second signal.
PCT/IB2003/004524 2002-08-22 2003-08-22 Method and system for multiplication of binary numbers WO2004019534A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003269332A AU2003269332A1 (en) 2002-08-22 2003-08-22 Method and system for multiplication of binary numbers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40524102P 2002-08-22 2002-08-22
US60/405,241 2002-08-22

Publications (2)

Publication Number Publication Date
WO2004019534A2 WO2004019534A2 (en) 2004-03-04
WO2004019534A3 true WO2004019534A3 (en) 2004-10-28

Family

ID=31946833

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/004524 WO2004019534A2 (en) 2002-08-22 2003-08-22 Method and system for multiplication of binary numbers

Country Status (2)

Country Link
AU (1) AU2003269332A1 (en)
WO (1) WO2004019534A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0260515A2 (en) * 1986-09-17 1988-03-23 INTERSIL, INC. (a Delaware corp.) Digital multiplier architecture with triple array summation of partial products
EP0517374A1 (en) * 1991-05-14 1992-12-09 Hewlett-Packard Company Digital color matrixing circuit
US5343416A (en) * 1992-11-02 1994-08-30 Intel Corporation Method and apparatus for re-configuring a partial product reduction tree

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0260515A2 (en) * 1986-09-17 1988-03-23 INTERSIL, INC. (a Delaware corp.) Digital multiplier architecture with triple array summation of partial products
EP0517374A1 (en) * 1991-05-14 1992-12-09 Hewlett-Packard Company Digital color matrixing circuit
US5343416A (en) * 1992-11-02 1994-08-30 Intel Corporation Method and apparatus for re-configuring a partial product reduction tree

Also Published As

Publication number Publication date
AU2003269332A1 (en) 2004-03-11
WO2004019534A2 (en) 2004-03-04
AU2003269332A8 (en) 2004-03-11

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