WO2004017209A3 - Optimized write back for context switching - Google Patents

Optimized write back for context switching Download PDF

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Publication number
WO2004017209A3
WO2004017209A3 PCT/IB2003/003262 IB0303262W WO2004017209A3 WO 2004017209 A3 WO2004017209 A3 WO 2004017209A3 IB 0303262 W IB0303262 W IB 0303262W WO 2004017209 A3 WO2004017209 A3 WO 2004017209A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
cache
main memory
references
difference
Prior art date
Application number
PCT/IB2003/003262
Other languages
French (fr)
Other versions
WO2004017209A2 (en
Inventor
Anton P Kostelijk
Original Assignee
Koninkl Philips Electronics Nv
Anton P Kostelijk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Anton P Kostelijk filed Critical Koninkl Philips Electronics Nv
Priority to AU2003247098A priority Critical patent/AU2003247098A1/en
Publication of WO2004017209A2 publication Critical patent/WO2004017209A2/en
Publication of WO2004017209A3 publication Critical patent/WO2004017209A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

An electronic device (200) has a data processing unit (220) with access to a memory architecture including a main memory (240) and a cache (260) under control of data management circuitry (280). The cache lines (264) of cache (260) are extended with a field (262) for storing a data difference bit pattern indicating a difference between the data element in the cache line (264) and the corresponding data element in the main memory (240). Data management circuitry (280) incorporates a first data storage element (282) and a second data storage element (284) for storing references to the boundaries of a contiguous stack or frame of data elements in main memory (240). When the data elements in the data frame have become irrelevant, control circuitry (286) generates relevant references to the data elements in the frame and further control circuitry (288) compares those references with the references stored in the cache lines (264). If a match is found, the corresponding data difference bit pattern is set to a value indicating the absence of a difference between the data element in the cache line (264) and the corresponding data element in the main memory (240) without writing back the data element from the cache (260) to main memory (240).
PCT/IB2003/003262 2002-08-14 2003-07-17 Optimized write back for context switching WO2004017209A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003247098A AU2003247098A1 (en) 2002-08-14 2003-07-17 Optimized write back for context switching

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02078363.5 2002-08-14
EP02078363 2002-08-14

Publications (2)

Publication Number Publication Date
WO2004017209A2 WO2004017209A2 (en) 2004-02-26
WO2004017209A3 true WO2004017209A3 (en) 2004-08-05

Family

ID=31725455

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/003262 WO2004017209A2 (en) 2002-08-14 2003-07-17 Optimized write back for context switching

Country Status (3)

Country Link
AU (1) AU2003247098A1 (en)
TW (1) TW200415467A (en)
WO (1) WO2004017209A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5622251B2 (en) * 2012-06-26 2014-11-12 東芝三菱電機産業システム株式会社 Data management apparatus, data management method, and data management program
GB2533768B (en) * 2014-12-19 2021-07-21 Advanced Risc Mach Ltd Cleaning a write-back cache

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5119485A (en) * 1989-05-15 1992-06-02 Motorola, Inc. Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation
US6209061B1 (en) * 1998-03-02 2001-03-27 Hewlett-Packard Co. Integrated hierarchical memory overlay having invariant address space span that inactivates a same address space span in main memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5119485A (en) * 1989-05-15 1992-06-02 Motorola, Inc. Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation
US6209061B1 (en) * 1998-03-02 2001-03-27 Hewlett-Packard Co. Integrated hierarchical memory overlay having invariant address space span that inactivates a same address space span in main memory

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CHARLESWORTH A: "The Sun Fireplane System Interconnect", CONFERENCE ON HIGH PERFORMANCE NETWORKING AND COMPUTING, PROCEEDINGS OF THE 2001 ACM/IEEE CONFERENCE ON SUPERCOMPUTING, ACM PRESS, NEW YORK, NY, USA, 10 November 2001 (2001-11-10) - 16 November 2001 (2001-11-16), Denver, Colorado, pages 1 - 14, XP002281147, ISBN: 0-7695-1357-3 *
PHILIPS: "Data Book - TM 1300 Media Processor - Product Specification - ToC - Chapters 4, 5, Appendix A-1,2,20,21,79", 30 September 2000, PHILIPS SEMICONDUCTORS, SUNNYVALE,CA 94088, XP002281148 *

Also Published As

Publication number Publication date
WO2004017209A2 (en) 2004-02-26
AU2003247098A1 (en) 2004-03-03
TW200415467A (en) 2004-08-16
AU2003247098A8 (en) 2004-03-03

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