200415467 玫、發明說明： 【發明所屬之技術領域】 本發明係有關於一電子裝置記憶體結構的資料管理之方 法。 【先前技術】 現ί%段’例如數位信號處理器（DSPs)與中央處理單元 (CPUs)的資料處理單元的處理速度已到達可每秒執數百萬 指令的位準。典型上，此指令可唤醒在電子裝置主記憶體 中儲存的資料處理。因為資料處理單元的最大主記憶體資 料存取頻率是遠低於它的處理能力，所以此會造成效率問 逑/果，因為資料處理的工作頻率是受到主記憶體存取 龙、率的支配，所以來自主記憶體的資料存取會導致資料處 理單元的次佳效率。 此效率問題可透過使用例如-專屬記憶體裝置的快取儲 存益將電子裝置的記憶體結構擴充而解決，而且該專屬記 置可快速由資料處理單元存取。-快取儲存器可整 泛在貝料處理單元（亦即位準 取儲存咨）、或位於資料處 快取儲/近（即是㈣2快取料器），以允許快速存取。 為了二典型可儲存由資料處理單元時常需要的資料， 為了要儘可能避免主記憶體耗時存取的 用於暫時資㈣存的快取 ，’·、 題，尤其是如果在快取儲存&成資料完整性問 主記憶體的對應資料，如同θ。、二:被更新’而未更新在 若要控制在寫回快取儲疋斤：的快取儲存器的情況。 緒存㈣資料完整性問冑，在快取 86938 200415467 儲存器的每條快取線要透過一资料不因 竹不问位兀圖案做旗號設 定，例如，快取線内容不同位元表示在快取儲存器的資料 與主記憶體間的不同’會在赃狀湘现協定的—快取線 狀態旗標是表示在快取儲存器中的資料狀態。此資料不同 位元圖案是用來表示在快取儲存器的資料線是否更新，而 典需將更新的貝料烏回到^ 陪麵 1 Μ判王记k體。雖然此不必然嚴格需 要，但是資料不同位元圖案血刑3 , 匕isi衣典型疋在與暫時儲存資料元件 相同的快取線位址；例如，[分 • ]如位兀位在專屬查閱表的實施是 同樣可實施。目前，如果资祖令田ΰσ 一 ， 果貝枓處理早疋想要使用其他資料 將快取線覆窝，資料不同位元 J红7C圖木便要評估，而且在快 線允許覆寫之前，如果位分同安主一丄 、、 位兀圖衣表不在快取儲存器的資料 與在主1己憶體的對應资料門古 "枓間有不-致，資料便會寫回主記 憶體。 美國專利案號6,2 19 757揭+六目士 ，57柄不在具有一堆疊快取與一資料 快取的處理器中維持資料完整 ”枓 ^ ^ , φ . $万去。堆璺快取儲存器 包含由中央處理器存取的快 .m 耳、、泉位址。中央處理器是配置 在罘一位址上執行換作 作例如減鼻或加算，以產生一第-位址，並放置在堆疊快 王罘一 且1^取储存态的上面。㈣，盥在第一200415467 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for data management of the memory structure of an electronic device. [Prior art] The processing speed of data processing units such as digital signal processors (DSPs) and central processing units (CPUs) has reached a level capable of executing millions of instructions per second. Typically, this command wakes up the processing of data stored in the electronic device's main memory. Because the maximum main memory data access frequency of the data processing unit is much lower than its processing capacity, this will cause efficiency problems / effects, because the working frequency of data processing is governed by the main memory access rate and rate. , So data access from main memory will result in the next best efficiency of the data processing unit. This efficiency problem can be solved by expanding the memory structure of the electronic device using, for example, a cache memory of an exclusive memory device, and the exclusive memory can be quickly accessed by the data processing unit. -The cache memory can be integrated in the shell processing unit (that is, the level storage unit) or located at the data cache unit (near the 2 cache unit) to allow quick access. In order to typically store the data that is often required by the data processing unit, in order to avoid as much as possible the main memory time-consuming access to the cache for temporary data storage, the problem, especially if the cache & For data integrity, ask the corresponding data in main memory, like θ. Second, it is updated ’without updating. To control the situation of the cache in the write-back cache: For the question of data integrity, in the cache 86938 200415467, each cache line of the memory must be set by a data-free pattern without flags. For example, different bits in the cache line indicate that The difference between the data in the fetch memory and the main memory will be agreed upon in a stolen state—the cache line status flag indicates the state of the data in the cache memory. The different bit patterns of this data are used to indicate whether the data line in the cache memory is updated, and the code needs to return the updated shell material to the ^ accompanying surface. Although this is not necessarily strictly required, but the blood bite 3 with different bit patterns of data is typically located at the same cache line address as the temporarily stored data element; for example, [分 •] If the position is in an exclusive lookup table The implementation is equally applicable. At present, if the ancestor of the ancestor Tian Tian 一 ，, if the processing of the shellfish wants to use other data to cover the cache line, the different bits of the data J Red 7C will be evaluated, and before the fast line allows overwriting, If the position is the same as that of the master, the data in the cache memory is not in the cache memory and the corresponding data in the memory of the master 1 is different, the data will be written back to the main memory. . US patent No. 6,2 19 757 + six eyes, 57 handles do not maintain data integrity in a processor with a stack cache and a data cache "枓 ^ ^, φ. $ 10,000 go. The memory contains fast, mear, and spring addresses that are accessed by the central processing unit. The central processing unit is configured to perform a substitution on, for example, nose reduction or addition to generate a first-address, and Place on the top of the stacking fast king 罘 and 1 ^ take storage state. ㈣, wash first
位址的快取線有關的一 X “兀會《有效改變洁血％ j能 避免由中央#掷哭六 （又又成播效狀悲，以 然而，此解決並未局限於從資1存無效資料。 窝回次數。此是缺增二、+快取儲存器到主記憶體的 通常需要比在為從快取錯存器寫回到主記憶體 耗時。在柘h 士 /、行恿理早兀間的資料流量更 耗守在類似本文切換、中斷#挪十 處里或函式呼叫終止的情況 86938 200415467 月:：ft取典型必須使用新的資料更新。因為在新快取儲 ^ 的售具料會在新資料從主記憶體拾取之前寫到主記憶 體，並儲存在快取儲存器，所以此更新典型會觸發許多寫 回Q為在王記憶體與快取儲存器間的資料流量尖峰，所 、匕曰在事件開始期間造成嚴重的效率問題。 【發明内容】 本發明係有關於一電子裝置記憶體結構的資料管理之方 該電子裝置包含一資料處理單元，該記憶體結構 :由通貝料處理單元存取，該記憶體結構包含一快取儲存 ⑽與：王'己憶體；1亥方法包含下列步驟：將來自主記憶體 的-資料7C件儲存在快取儲存器，以供資料處理單元的快 速存取；透過資料處理單元而使用一進-步資料元件將在 5儲存器的資料元件覆寫，造成資料元件的修改’·及將 一貝料不同位元圖案設定成m圖案值，以表示在資料 疋件與進一步資料元件間的不同。 現階段，例如數位信號處理器（DSPs)與中央處理單元 (fPUs)的資料處理單元的處理速度已到達可每秒執數百萬 札7的位卞。典型i ’此指令可唤醒在電子裝置主記情- 中儲存的資料處理。因為資料處理單元的最大主記憶體: :存取頻率是遠低於它的處理能力，所以此會造成效率問 題。結果，因為資料處理的工作頻率是受到主記憶體存取 頻率的支配，戶斤以來自主記憶體的資料存取會導致資料 理單元的次佳效率。 此效率問題可透過使用例如—專屬記㈣裝置㈣取儲 86938 200415467 存器將電子裝置的記憶體結構擴充而解決，而且該專屬記 憶體裝置可快速由資料處珲罝；左而 處理早兀存取。一快取儲存器可整 合在資料處理單元（亦即位準卜㈣儲存器）、或位於資料處 理早㈣接近（即是位準2快取儲存器），以允許快速存取。 快取儲存器典型可儲存由資料泠 ― 、 ，、枓處理早疋時常需要的資料， 為了要L可月匕U兄王吕己憶體耗時存取的時常發生。炊而， 用於暫時資料儲存的快取 % 氏取儲存咨使用會造成資料完整性問An address related to the cache line of the "U" will effectively change the "clean blood"% can avoid crying from the central # (also a sad effect, but this solution is not limited to the first deposit Invalid data. Number of nesting times. This is the lack of two. + Cache memory to the main memory usually takes more time than writing back to the main memory from the cache error memory. The data flow between early and early periods is more depleted in situations similar to this article's switchover, interruption # to move ten places or the termination of the function call 86938 200415467 Month: ft fetch must typically be updated with new data. Because in the new cache store The sales materials of ^ will be written to the main memory before new data is picked up from the main memory and stored in the cache memory, so this update will typically trigger many write back Q between the king memory and the cache memory The data traffic spikes, so the problem caused serious efficiency problems during the beginning of the event. [Summary of the Invention] The present invention relates to a data management method for the memory structure of an electronic device. The electronic device includes a data processing unit, the memory Body structure: made by Tumbe Processing unit access, the memory structure contains a cache storage and: Wang 'Ji Yi body; 1 Hai method includes the following steps: the future autonomous memory-data 7C pieces are stored in the cache memory for data processing Quick access of the unit; using a step-by-step data element to overwrite the data element in the 5 memory through the data processing unit, causing the modification of the data element 'and setting different bit patterns of a shell material to m pattern values To indicate the differences between data files and further data components. At this stage, the processing speed of data processing units such as digital signal processors (DSPs) and central processing units (fPUs) has reached millions of frames per second. Bit 7: Typical i 'This command can wake up the data processing stored in the electronic device's main memory-because the maximum main memory of the data processing unit:: the access frequency is much lower than its processing capacity, so this Will cause efficiency problems. As a result, because the working frequency of data processing is dominated by the access frequency of the main memory, the data access of the autonomous memory since the households will cause the second time of the data management unit Efficiency. This efficiency problem can be solved by using, for example, a dedicated memory device to retrieve storage 86938 200415467 to expand the memory structure of the electronic device, and the dedicated memory device can be quickly processed by the data; Wu access. A cache memory can be integrated in the data processing unit (ie level memory), or located close to the data processing early (ie level 2 cache memory) to allow fast access. The cache memory can typically store the data often used by the data to process the premature 疋, in order to require time-consuming access to the body of the brother Lü Wang, Wang Lu Jiyi. For cooking, for temporary Cache% of data storage
超，尤其是如果在快取锼左哭AA、之M 、 渚存的為料被更新，而未更新在 王記憶體的對應資料，如η σ上 ^ 冋疋在所謂的快取儲存器的情況。 右要控制在寫回快跑辟+ _ , . 5予备的資料％整性問題，在快取 儲存器的每條快取線要透 ^ ^， 貝枓不冋位兀圖案做旗號設 疋’例如一快取線内交 冋位元表示在快取儲存器的資料 人王α己彳思f豆間的不同，备 ^ W q 曰在mesi與M0ESI協定的一快取線 狀態旗禚疋表不在快 ..Rθ + 储存益中的資料狀態。此資料不同 .^ ^ ,、’、在快取儲存器的資料線是否更新，而 典^將更新的資料窩回|、、 要，伸是皆料不门王死憶體。雖然此不必然嚴格需 Γ 元圖案典型U與暫時儲存資料元件 相同的快取線位址；例如，一 同樣可實施。目前，如果資：：位在專屬查閱表的實施是 將快取線覆寫1料不W 理單元想要使用其他資料 線允許覆寫之案便要評估，而且在快取 、 711圖案表示在快取儲存器的資料 Μ在王記憶體的對岸資 ^ 憶體。 枓間有不-致，資料便會寫回主記 美國專利案號6，2 19 7 5 7揭-士 ，〇7揭7在具有一堆疊快取與一資料 86938 200415467 快取的處理器中維持資料完整性 包含由中央處理哭存取 禽t快取儲存备 在第-位… 線位址。_央處理器是配置 執行操作，例如減算或如算，以產生-第二 位址’並放置在堆疊快取儲存器的上面 位址的快取線有同的厂a 時’與在第一 會從有效改變成無效狀態，以 ^由中t處理器存取在資料快取儲存器中的無效資料。 尤、而，此解決並未局限 寫回次數。此是_，m p 存"到王記憶體的 ^ ^ ^ . ’ 、為仗快取儲存器寫回到主記憶體 5子态舁^料處理單元間的資料流量更 耗時。在類似本文切換、中斷處理或函式呼叫終止的情況 二:=典型必須使用新的資料更新。因為在㈣ "料會在新資料從主記憶體拾取之前寫到主記憶 ⑯並儲存在快取儲存器，所以此更新典型會觸發許多寫 口因為在王吕己憶體與快取儲存器間的資料流量尖峰，所 以此會在事件開始期間造成嚴重的效率問題。 另外，本發明的一目的是要減少在主記憶體及與需要快 耳儲存W更新事件發生有關的快取儲存器之間的資料流 ° 本*明係透過獨立的申請專利範圍來描述。冑屬的申請 專利範圍係疋義有利的具體實施例。 本發明是根據因為資料變成無關或過時，儲存在快取儲 存。°的貝料不必寫回主記憶體的某些情況下而實施。例如， 當函式呼叫、或程序終止時，在只與一函式呼叫或一程序 有關的快取儲存器中的資料會變成無關。對於函式呼叫、 86938 200415467 或程序而言，資料處理單元使用一堆疊，或更明確而言， 使用一堆疊訊框，以儲存執行中函式或程序的區域變數。 函式呼叫終止典型會造成資料處理單元使用來自堆疊的一 新堆疊訊框，而使在先前使用的堆疊訊框中的資料無關。 將來自在快取儲存器中先前使用堆疊訊框影像的資料寫回 王死憶體因此不需I ’而且可在本發明避免。因為特別是 在本文切換期間，例如一中斷呼叫、一錯誤處理、一線緒 開關或-工作開關、在主記憶體與快取儲存器間的密集資 料流量必須發生，而嚴肅負面影響到電子裝置的效率，所 以此是重要的。透過避免從快取儲存器到主記憶體的多餘 寫回，這些負面影響便可降低。 、 ，，v 叫〜丁 Π冷止；類似Super, especially if the contents of cache AA, M, Z are updated in the cache, but the corresponding data in the king memory is not updated, such as η σ ^ 冋 疋 in the so-called cache memory Happening. Right to control the write back and run + _,. 5 prepared data% integrity issues, each cache line in the cache memory must be transparent ^ ^, do not set the flag to set the flag. 'For example, the cross-bits in a cache line indicate the difference between the cacher's data source, King Alpha, and 豆. ^ W q is a cache line status flag in the mesi and M0ESI agreement. Table is not fast .. Rθ + data status in storage benefits. This data is different. ^ ^ ,, ’, whether the data line in the cache memory is updated, and Code ^ puts the updated data back to | ,, and, it is impossible to predict the death of the king. Although this does not necessarily strictly require that the Γ element pattern typically has the same cache line address as the temporarily stored data element; for example, one can also be implemented. At present, if the implementation of the exclusive look-up table is to overwrite the cache line with a data line, the case that the unit wants to use another data line to allow overwriting must be evaluated, and the cache, 711 pattern indicates that The data in the cache memory is on the other side of the memory. If there is no response, the data will be written back to the main US patent case No. 6, 2 19 7 5 7 and 7 0 7 in a processor with a stack cache and a data 86938 200415467 cache. Maintaining the integrity of the data consists of the central processing unit accessing the cache and storing it in the -bit ... line address. _ The central processor is configured to perform operations, such as subtraction or calculation, to generate-the second address 'and place the cache line at the upper address of the stack cache memory when the cache line has the same factory a' as in the first Will be changed from valid to invalid state, and the invalid data in the data cache is accessed by the processor. In particular, this solution does not limit the number of write-backs. This is _, m p saves ^ ^ ^. To the king memory, and writes back to the main memory for the cache memory 5 substates. The data flow between the data processing units is more time consuming. In situations similar to this article's handover, interrupt handling, or function call termination 2: = Typically, new data must be used to update. Because ㈣ " is expected to write to the main memory before new data is picked up from the main memory and store it in cache memory, this update typically triggers many writes because in Wang Luji ’s body and cache memory Data traffic spikes, so this can cause serious efficiency issues during the start of the event. In addition, an object of the present invention is to reduce the data flow between the main memory and the cache memory related to the occurrence of an update event that requires ear storage. The present invention is described through the scope of independent patent applications. The scope of patent application is a concrete and advantageous embodiment. The present invention is based on the fact that data becomes irrelevant or outdated and is stored in a cache. ° Shell material does not need to be written back to main memory in some cases. For example, when a function call or procedure terminates, the data in the cache memory associated with only one function call or procedure becomes irrelevant. For function calls, 86938 200415467 or procedures, the data processing unit uses a stack, or more specifically, a stack frame to store local variables of the function or procedure in execution. Function call termination typically causes the data processing unit to use a new stack frame from the stack, leaving the data in the previously used stack frame irrelevant. Writing back data from the previously used stacked frame images in the cache memory to Wang Shimei's body therefore does not require I 'and can be avoided in the present invention. Because especially during the switching of this article, for example, an interrupted call, an error handling, a thread switch or-work switch, dense data traffic between the main memory and the cache memory must occur, and seriously affects the electronic device's Efficiency, so this is important. By avoiding redundant write back from cache memory to main memory, these negative effects can be reduced. ,,, V is called ~ 丁 Π 冷 止; similar
數位影像處理的其他岸用卩1 + V ，、他L用（其中一 Dsp可修改同時由 樣所取代的一數位聲频式里 耳乂、次於像資料取樣）DSp快 内容典型會變成血關及官门^ ^喊存咨的 成”、、關及冩回到主記憶體會變成 可避免。其他有用的應用屬A _、☆、 綠並亦Other digital image processing uses 卩 1 + V, and other uses (one Dsp can modify a digital audio-type earphone, which is replaced by samples at the same time, followed by image data sampling) DSp fast content will typically turn into blood "Guan and the official gate ^ ^ chanting the success of the counselor", and Guan and 冩 return to the main memory will become avoidable. Other useful applications are A _, ☆, green and also
^ 〜域可透過表示資料變选、M A AA 命令處理單元來執行，例 又成過時的 J 1 j 如 C命令”FREE，，。 此外，例如對於屬於 ,,4, 、 …、有在快取儲存器的影像特殊訊框 的所有資料元件而言，告 不幵缘訊框 .佳一牛义U ㈤進—步資料元件過時而焱需估 進-，貝枓元件將資料元件覆寫3争，將：而使用 設定成一位元圖案值 _ 、5么元®案 口木值以表7F在資料元件與進—一 件間出現不同的步驟通常 ,貝料元 、吊可於複數個資料不 施，其中該等資料不同 十不问位元中實 、 U 7C疋與在快取儲存器 數個進一步資料元件、 °°儲存的複 久舁在王記憶體儲存的 # W相闕複數個 86938 200415467 資料兀件有關。在本發明的本文+，—位元圖案是由單一 位元所組成。 更新快取儲存與避免寫回的處理包括從主記憶體的複數 個資料Tt件選取第―資料元件位置的第―參考；並從主記 憶體的複數個資料元件選取一最後資料元件位置的第二參 考。 f此處理，複數個資料不同位元圖案是在來自主記憶體 的複數個資料元件的第一資料元件位置的第—參考、與來 自主圮憶體的複數個資料元件的最後資料元件位置的第二 參考的基礎上選擇。第一值典型參考主記憶體二資：： 件位址，然而，當資料訊框的大小是預先知道時，第二值 便會是此位址的偏移，或可以是在主記憶體中進一步位址 的參考，以表示主記憶體的最後資料元件的位置。 目前’本發明的另一目的係透過如申請專利範圍第㈣之 電子裝置而實施。此-裝置可避免從快取儲存器多餘寫回 到主記憶體，造成對電子裝置效率負面影響。 ” 在本發明電子裝置的一具體實施例，資料管理裝置包人 -資料儲存元件1以將複數個資料元件的一第元 件位置的第一參考儲存在主記憶體；一 半t , 711 進一步資料儲存元 件，用以將複數個資料元件的最後資料元件位置的第 考儲存在主記憶體；控制電路，其耦合到該資料儲存元參 與進一步資料儲存元件，用以從主記憶體的資枓元件2件 產生進一步資料元件位置的進一步參考·及隹― 圍 、、、 ，久疋一步控制電 路’其可根據該進一步值而反應無關的進一步資一 ，貝科元件辨 86938 -12- 200415467 識來设足資料不同位元圖案。 此配置只需要例如位於快取控制器或在資料處理單元的 有限額外硬體資源。它允許透過控制電路而在由值及進— 步值所疋義的資料訊框位址範園上執行簡單的迴路。控制 電路亦可檢查是否到達迴路的結纟，而進—步控制電路可 將進一步值與在快取儲存器中 果一比較發現變成無關的進一 儲存的位址資訊相比較；如 步資料元件確認，而且它的 表小1不需 ’可獲得有 資料不同位元圖案設定成”相同，，或一類似值， 要寫回王圮憶體。結果，隨著有限的硬體資源 效改善裝置效率。 有利地的ι辨識包含在快取儲存器的快取線中目前訊 框位凡的識別’以表示快取線的内容是否屬於來自目前由 資料處理單元所使用主記憶體的_資料訊框。 用以標示包含屬於目前所使用資料訊框的資料的快取線 的-額外位元（即是目前訊框位元）使用的優點是此資料訊框 包括的快取線偵測能與資料處理單元的其他工作 =，如此便可進一步改善電子裝置的效率。雖然它會導： ^複雜的㈣儲存器資料管·，但是因為在-不中斷指令 成中的-資料訊框開關確實表示在快取儲存器的所有" 訊框位元值必須更新，相強調此不必然是H 額外操作不是非常耗時。 1 因為 如果資料儲存元件與進-步資料儲存元件… 、 料儲存裝置，以將複數個資料訊框的：：：的資 憶體，此會是一優點。 I储存在主記 86938 200415467 ^著一專屬資料儲存裝置的出現（例如一堆疊訊框邊界暫 存。。）/、有關於堆疊指標值的資訊必須提供給裝置，以設 定-資料不同位元圖案，如此便可簡化必須提供以允許避 免知典關資料寫回的資訊。 一在本發明的進—步具體實施例，用以設定—資料不同位 凡圖案的裝置是反應一專屬的指令。 此扎令典型包含：一第一引數，以表示來自主記憶f# 複數個資料元件的第-資料元件的位置；及一進一步引數， 乂表不來自王記憶體複數個資料元件的最後資料元件的位 引數以足我來自主記憶體複數個資料元件的一 罘一資料元件位置的偏移。此優點是，如果任何資訊，非 常小的資訊必須透過用以設定一資料不同位元圖案的裝置 所取回，而且優點是包含所需的硬體數量。 在本發明的另一具體實施例，$以設定一資料不同位元 圖案的裝置是反應用以偵測一事件的專屬電路，以表示進 一步資料元件是否變成無關。 當一堆疊指標或訊框指標的值改變時，例如一推入訊框、 或一取出訊框指令執行，用以設定-資料不同位元圖案的 裝置可透過例如—簡單*較器電路的專屬硬fi來直接發 、風·自堆瓦指標的值。此優點是不需要專屬的指令。 、:發明的仍然進一步目的可透過如申請專利範圍第U項 (扎令組而實施。在指令組中包括一避免寫回指令可於本 又切梃及包括資料處理單元的電子裝置類似事件期間允許 允許效率改善。 86938 -14- 200415467 【實施方式j 本發明係合併一兩；壯、 其中該兩 E 置圮憶體結構的資料管理方法， ^ 裝置具有如圖1所示的一資料虔一 , 結構舍厶—、、 /、种處理早兀。記憶體 再乙口—王I己憶體與一快 單元存取。血刑h费 彳料兩者可由資料處理 快取儲存器來:取的主記憶體是資料處理單元經由 在資料管理方、本Μ $ ^ 於取，… ，一資料元件是從主記憶體 σ 5子在快取儲存器’以供資料處理單元的快速存 透過儲存資料與特別時常❹的資料，在快取儲存器， 王記憶體的時間消耗存取可避免，而且資料處理單元的處 理速度會增加，造成必要的資料可更容易使用。 在貝料官理万法的第二步驟，一進一步資料元件（即是， 由資料處理單元修改的資料元件）會寫回到在修改前取出的 快取儲存器位置。換句話說，在快取儲存器的最初資料元 件係透過修改的資料元件重寫。然而，既然修改的資料元 件不是寫回到主記憶體’所以主記憶體包含不再更新的資 料版本；記憶體可說是過時。因此，在更的資料複製到主 記憶體前，一機構必須放置在適當地方，以避免在快取儲 存器的更新資料損失。 在資料管理方法的第三步驟，一資料不同位元圖案是設 定成一位元圖案值’以表示在資料元件與進一步資料元件 間的不同，即是在主記彳思骨豆貝料元件的舊值與在快取儲存 器的更新資料元件間的不同。此一位元圖案是由單一位元 所組成，然後該單一位元可保持兩個值，即是用來表示資 86938 -15- 200415467 •斗内奋的不同與相同，其中前者表示在主記憶體的資料與 在決取儲存器的副本間的不同，而後者表示這些資料元件 是相同。ΎΤ . …、而，例如使用在類似MESI與MOESI協定分享資 源結構的更複雜位元圖案是同要可實施。當資料處理單元 存取快取错存器，以在該等快取線之一上做寫動作時，資 料不同7C圖案便會評估，而且如果遇到—位元圖案值， 以表示在主記憶體的資料元件與快取儲存器的進一步資料 的：同，進-步資料元件便會被配置在快取錯存的 “里早疋做寫動作之前寫回到主記憶體寫。此配置包 括進一步資料元件在暫時緩衝器的儲存。 然而，資料管理方法的第四步驟是在當遇到一位元圖安 值表不在主記憶體的資料元件與在快取儲存器的進—步= ^件間的不同時的—快取儲存器重寫之前提供 來 寫回王記憶體。當在快取儲存的進—步采 作造成無關的進一步資料元件情況時，資料：一 ·”、動 便會立即設定成-位元圖案在、°义70圖案 一 +资祖-址冷* 以表不在快取儲存器的進 广科兀件人在王記憶體的資料元件間的 在，而無需將進-步資料元件寫回到主記憶體。不存 變成無相關的在快取儲存器的資料範例會終 理單元執行程序或函式呼叫的終止。血刑上、—+處 單元會在執行時使用堆叠來儲存與副常二’一資料處理 料％例如函式，或程序。每個副常式佔用資 堆&，例如-堆璺訊框，而且該堆叠訊框可 ^的 或在副常式執行期間能綠士七⑷彡、 疋固疋大小 又大或收縮。堆叠通常保持在主記 86938 -16 - 200415467 憶體，但是當預期時常存取在這些部份特殊資料時，一邱 份堆疊的複製可保持在快取儲存器。 ^ 拙厂咕. …、叩，當完成副常式 執订時，在相關堆疊訊框的資料便 又 < 雒關。所以，即使 與結束副常式有關的主記憶體中的資料是過時，此資料 :新是不必要的，因為它不能重新使用1此，根據本發 明，從快取儲存器到主記憶體的耗時寫回可透過將相闊快 :線的不同位元圖案設定成一位元圖案值，以允許快取儲 存器立即重寫。 =諳此技者顯然知道在快取儲存器的資料在其他環境亦 會變成無關；在類似數位影像處理的應用中，其中—阿 修改同時由下-取樣取代的一數位聲頻或視訊資料，⑽快 取儲存器的内容典型會變成無關，並寫回主記憶體變成多 餘’並亦可避免。其他有用的應用領域可透過表示資料變 成不再使用命令的處理單元來執行，例如c命列"free" = 而且其他範例可使用，而不致脫離本發明的說明。 典型上’在第四步驟，在與快取儲存器中儲存的複數個 進—步資料7L件有關的複數個資料不同位元圖案可更新。 :然變成無關的資料通常是與在主記憶體的資料元件相鄰 範圍m ’所以第四步驟通常包括在主記憶體資料元件範 中第Λ料元件位置的第一參考、與來自主記憶體的複 數個資料元件的最後資料元件位置的第二參考基礎上來選 擇複數個進一步資料不同位元圖案的附屬步驟。隨後，在 不同值範圍的所有表示主記憶體位址是與在快取儲存器中 儲存的仅址相比較，而且如果比較發現相關的位元圖案值 86938 200415467 疋设定成表7F —位元圖案值的值，以表示在快取儲存的進 步貝料元件與主圮憶體的資料元件之間是否沒有不同。 第一值與第二值可當作（參考到）位址來提供，但是第二值可 選擇性當作該第一值的位址參考偏移來提供。此在主記憶 體的相鄰資料區塊具有固定大小的實施是很有用。此偏移 可在專屬的位元圖案更新指令中以一參數的形式(例如引數) 來提供。 的一電子裝置200。電子裝 例如一中央處理器或DSP， 圖1顯示用以實施本發明方法 置200具有一資料處理單元22〇， 並可存取包括一王記憶體24〇與一快取儲存器的一記憶 體結構。在此特殊具體實施例中，快取儲存器26g包括：複 數個位置262’以儲存資料不同位元圖案；及複數個快取線 = 4，，用讀存資料元件及其主記憶體位址資訊。快取儲存 -的貝料官理可由反應資料處理單元22q的資料管理電路 2 8 0來控制。 、為了本發明的緣故，資料管理電路28〇已使用額外硬體擴 以產生對於在王記憶體240的資料元件連續範圍的複數 ，考以避免將無關的資料寫回到主記憶體240部份。资 ^管理電路280包括-資料儲存元件282與一進—步資料儲 2疋件284 分別儲存在弟色圍中第一資料元件的第一參 盘、、與—在IS圍中最後資料元件的第二參考。資料儲存元件叫 資!!儲存元件284可以是類似—小的專屬記憶體或 斤存器的未在圖顯示的一部份專屬資料儲存裝置， 办如可用來儲存對於在主記憶體2辦續範圍邊界的參考。 86938 -18> 200415467 田參考可以是貧位址、或到此一位址的指標，例如一堆 ®指標符。 具料官理電路280進一步包含控制電路286，以增量方式 攸主尤憶體240的資料元件範圍來產生對進一步資料元件位 置的進一步參考。基本上，控制電路286包含一參考產生器， 而且最好可從第一參考到第二參考來逐一產生所有進一步 多考。既然目標資料元件是位在主記憶體24〇的連續範圍， 所以在控制電路286的進一步參考或位址產生可透過眾所週 知的技術執行。控制電路286典型包括未在圖顯示的一比較 备，用以將一產生的進一步參考與第一或第二參考相比較， 此是因進一步參考產生的向上或向下方向而定，以決定進 一步參考產生是否完成，在此情況，進一步參考產生會結 束。 控制電路286耦合到進一步控制電路288，以從控制電路 286獲得第一參考、或一產生的進一步參考，而且典型包括 未在圖顯示的一進一步比較器，用以將獲得的參考與在複 數個快取線264中儲存的參考相比較。如果一比較參考是在 快取線264發現，在位置262儲存的相關資料不同位元圖案 便會設定成一值，以表示在快取儲存器260的進一步資料元 件與在主記憶體240的相關資料元件之間是否沒有不同。在 單一位元的位元圖案情況，位元可隨著内容是否相同戋不 同而設定。一般強調雖然複數個位置262是以快取儲存哭“Ο 的整體部份來描述，但是此並非嚴格必要實施，其中形成 一分開表的複數個位置262亦可實施。而且，即使顯示的資 86938 -19- 料言理電路2 g ο是從資料處 此. 早7" 220分開，但是-般強調 元220沾— ，、+ &里黾路280等合在資料處理單 兀22〇的實施是同樣可實施。 卞义里早 在本發明的一具體實施例， 一 令組，t包括4處理早兀220可反應一指 取情卜 的—專屬的指令，以避免多餘從快 =存:骑回到主記憶體勝典型上，在函式呼叫或 力員似事件終止之後， ’ 執行的專屬指令。此—指：:=!由資料處理單元22。 7具有透過資料資料單元220而分 别错存在資料儲存元 ΑΑ # τ 〇“、貝枓儲存兀件284的當作參數 炎^-參考與第二參考。或纟，專屬的指令能只包括單一 例如^似在貝料處理單元220中儲存的—堆疊指標值 、多偏牙多w在王冗憶體的資料元件連續範圍是固定大 小時，此會特別㈣，在此情況，偏移係定義資料元件範 圍的大小。由於專屬指令與堆疊指標處理有密切關係，所 以專屬指令能與一堆疊指標處理指令組合，以減少在指令 勺才曰7數里。結果，負責處理堆疊指標值的硬體能與硬 把、且口以避免彳< 快取儲存器260多餘寫回到主記憶體24〇， 此從區域負荷的觀點是有利的。 目i，其餘圖是針對圖丨描述。除非特別說明，否則對應 的參考數丰具有相同意義。圖2是提供電子裝置2〇〇的另一 具體實施例。電子裝置2〇〇能使用額外硬體29〇擴充，以監 督目刖堆®指標、或訊框指標、在資料處理單元22〇的專屬 暫存备222中儲存值的變化。此可在搜尋指令中透過監督實 際的暫存器222、或透過監督資料處理單元22〇的指令流程 86938 -20- 200415467 、在, 、其中该搜尋的指令可導致在暫存器222中的值修 改 J 1 ^ 歹如一推入（push)訊框或取出（pop)訊框指令。 —專屬硬體290包括未在圖顯示的一暫存器與未在圖顯示的 —=較器電路，以將一堆疊指標值儲存在暫存器，並比較 料處理單兀220的暫存器222中的堆疊指標實際值。明 頭地，當專屬硬體290配置來監督堆疊指標處理指令時，未 在圖_示的比較器電路便不需要。 如果堆疊指標值的變化可觀察到避免從快取儲存器26〇多 餘寫回王記憶體240，一向上成長堆疊的堆疊或訊框指標值 減少、或在向下成長堆疊的堆疊或訊框指標值增加，專屬 硬體290便會使用堆疊或訊框指標的舊與新值供應給第一資 料儲存元件282與第二資料儲存元件284，並觸發資料管理 私各280以避免從快取儲存器260多餘寫回到主記憶體24〇 的王域體的位址範圍，其中該主記憶體的位址範圍是位 在隹武或Λ框指標的售與新值之間。一般指出對於此一實 施而τ，不需要用以避免多餘寫回的專屬指令；專屬硬體29〇 可接管此一指令的角色。 圖3是參考圖2來描述。除非特別說明，否則對應的參考 數罕具相同意義。圖3表示在圖2顯示的電子裝置·擴充。 在此具Iff施例’在快取儲存器26()的快取線⑽的一部份 263可運送一額外控制位元，即是在進—步控制電路2δδ控 制下的-目前訊框位元，此表示伴隨的快取線是否屬於來 自由資料處理單元220目前使用主記憶體的内容訊框。在快 取線264的此-位元實施能以類似資料不同位元圖案的眾所 86938 •21 · 200415467 週知方式實施，因此，不進-步做任何描述。 在此具體貫施例，負責避免從快取 、、. 省备2 6 0夕餘宫回到 主記憶體240的一部份資料管 一·’ 了 ΐ操Γ二資料儲存元件282與第二資料儲存元件284 可運迗由資料處理單元22〇前 ^ ^ τ使用g枓訊框範圍的邊界 值。在快取儲存器260的進一步资 逆艾貝村几件（來自主記憶體240 的'貝料疋件範圍的資料元件影像）是使用在快取線⑽的位 疋位置263中目前訊框以的旗號，以表示在伴隨快取線的 ㈣是否屬於由資料處理器22㈣前所使用的資料訊框。目 前，在除了與從從快取儲存器26〇餘寫回到主記憶體⑽ 的產生有關的操作之外的操作執行期間，資料處理單元22〇 需要快取線264的重寫，以運送與新資料元件目前所使用的 資料訊框有關的-進—步資料㈣’丨中該新資料元件是 位在由第一資料儲存元件2 8 2與第二資料儲存元件2 8 4的參 考所表示的資料元件範圍夕卜新資料元件的主記憶體位置 是否位在由資料處理單元22〇目前所使用的資料訊框範圍外 能以前述方式透過控制電路286評估。 當是此種情況時，資料管理電路28〇便會評估在位置262 的資料不同位元圖案，而且如需要，可強制寫回到主記憶 體240。此外，相關的快取線264的目前訊框位元是設定成 值’以表示在快取線2 6 4的資料是否位在由資料處理單元 220目前所使用的資料訊框範圍外。 此具體實施例的優點是資料管理電路240是當資料管理電 86938 •22- 200415467 路280動作而避免將無關的資料從快取儲存器26〇寫回到主 記憶體24G時’只必須評估在快取儲存器⑽的目前訊框位 元，而不是在快取儲存器26〇的快取線264中的行位址參考。 此表示在此一事件期間的電子裝置2〇〇效率進一步改善。明 頭地，當資料管理電路280被激勵來無關資料的寫回時，與 變成無關資料有關的資料不同位元圖案將設定成進一步位 兀圖案值，而且快取線264的目前訊框位元會根據資料處理 單几220使用的新堆疊或訊框來重新設定及更新。 >王意，上述具體實施例只是說明而不是對本發明的限制， 熟諳此技者可設計許多選擇性具體實施例，而不致於脫離 又後申請專利㈣圍。纟中請專利範圍中，在靠間的任 何參考符唬將不構成對申請專利範圍的限制。字眼，，包含，， 不排除除了在申請專利範圍中列出之外的元件或步驟。在 元件幻的 不排除複數個此元件。本發明可透過包含數 個μ ^几件的硬體實施。在申請列舉數個裝置專利的裝置 中數個化些裝置可透過硬體的一項目與相同項目而具體 二她事貝上’某些措施可相互引用，而不同的申請專利 範圍並不表示這些措施的組合不能有利地使用。 【圖式簡單說明】 本&月疋經由非限制的範例與附圖而更詳細描述，其中： 圖1係根據本發明而顯示一電子裝置的具體實施例； 圖2係根據本發明而顯示一電子裝置的另一具體實施例； 及 圖3係根據本發明而顯示一電子裝置的仍然另一具體實施 86938 -23- 200415467 例。 【圖式代表符號說明】 200 電子裝置 262 爛位 264 快取線 220 資料處理單元 240 主記憶體 260 快取儲存器 282 第一資料儲存元件 284 進一步資料儲存元件 280 資料管理電路 286,288 控制電路 222 專屬暫存器 290 額外硬體 263 位元位置 86938 - 24 -^ ~ The domain can be executed through the display data selection and MA AA command processing unit. For example, the outdated J 1 j such as the C command "FREE". In addition, for example, for the belonging to, 4 ,,…, there is a cache All the data elements of the special frame of the image in the memory are unavailable. Jia Yi Niu Yi U—Progress—the data elements are out of date and need to be evaluated—because the elements overwrite the data elements. , And use: set to a one-bit pattern value _, 5 Mo Yuan® case wood value as shown in Table 7F in the data element and progress-different steps between one piece usually, shell material element, hanging can be in multiple data There are several different data elements in the cache, U 7C 疋 and several further data components in the cache memory, °° stored for a long time, # W 相 阙 stored in Wang memory, a plurality of 86938 200415467 The data element is related. In the text of the present invention, the bit pattern is composed of a single bit. The process of updating the cache storage and avoiding write back includes selecting the first data from the plurality of data Tt files in the main memory. The first reference of the component position; and from the main memory The second reference of the last data element position is selected for the plurality of data elements of the f. In this process, the different bit patterns of the plurality of data are the first reference and the first data element position of the plurality of data elements from the main memory. The second reference from the last data element position of the plurality of data elements from the main memory is selected based on the second reference. The first value is typically referenced from the main memory data: the address of the element, however, when the size of the data frame is in advance When known, the second value will be the offset of this address, or it may be a reference to a further address in the main memory to indicate the location of the last data element of the main memory. Currently 'another object of the invention It is implemented by an electronic device such as the scope of the patent application. This device can avoid redundant writing from the cache memory to the main memory, which will adversely affect the efficiency of the electronic device. "In a specific implementation of the electronic device of the present invention For example, the data management device includes a human-data storage element 1 to store a first reference of a first element position of the plurality of data elements in the main memory; half t, 711 A further data storage element for storing the last data element position of the plurality of data elements in the main memory; a control circuit coupled to the data storage element to participate in the further data storage element for obtaining data from the main memory枓 Element 2 generates further information for further reference to the position of the element, and 隹 围-,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,-,-,-,-,-,,-, Identify the different bit patterns of the data. This configuration requires only limited additional hardware resources, such as located in the cache controller or in the data processing unit. It allows a simple loop to be performed on the data frame address range defined by the value and step value through the control circuit. The control circuit can also check whether the loop has been reached, and the further control circuit can compare the further value with the further stored address information found to become irrelevant in the cache memory; such as the step data component confirmation And, its table size 1 does not need to 'get data with different bit patterns set to the same, or a similar value, to write back to Wang Zheyi's body. As a result, with limited hardware resources, the efficiency of the device is improved. Favorable Local identification is included in the current frame of the cache line in the cache memory to identify whether the content of the cache line belongs to the _data frame from the main memory currently used by the data processing unit. The advantage of using extra bits (that is, the current frame bit) to mark the cache line that contains data belonging to the currently used data frame is that the cache line detection and data processing unit included in this data frame Other work =, so that the efficiency of the electronic device can be further improved. Although it will lead to: ^ complicated ㈣ memory data management, but because of-data is not interrupted into the-data The frame switch does indicate that all the "quotation frame bit values in the cache must be updated. It is emphasized that this is not necessarily H. The extra operation is not very time-consuming. 1 because if the data storage element and the advanced data storage element ..., Data storage device to store multiple data frames ::: information memory, this would be an advantage. I stored in the master 86938 200415467 ^ the emergence of a dedicated data storage device (such as a stack frame border temporarily Save ...) /, information about the stacking index value must be provided to the device to set-different bit patterns of the data, so that the information that must be provided to allow the data to be written back to avoid knowledge can be simplified. A step-specific embodiment is used to set the device with different patterns of data to reflect a unique instruction. This command typically includes: a first argument to represent the first-data from a plurality of data elements in the main memory f # The position of the component; and a further argument, which indicates that the bit argument of the last data element from the plurality of data elements in the king memory is sufficient for me to come from the plurality of main memory elements The position of the data element is shifted one by one. This advantage is that if any information, very small information must be retrieved by the device used to set a different bit pattern of the data, and the advantage is that it contains the required hardware In another specific embodiment of the present invention, the device for setting a different bit pattern of data is a dedicated circuit for detecting an event to indicate whether further data elements become irrelevant. When a stacking indicator or When the value of the frame indicator changes, for example, a push-in frame or a frame-removal instruction is executed, a device with different bit patterns of data can be sent directly through, for example, a dedicated hard fi of a simple * comparator circuit. The value of the wind self-stacking indicator. This advantage is that no special instructions are needed. The further purpose of the invention can be implemented by applying for patent scope item U (Zaring Group. Included in the instruction group is to avoid writing The return instruction may allow efficiency to be improved during similar events in electronic devices including data processing units. 86938 -14- 200415467 [Embodiment j The present invention is a combination of one or two; the data management method of the memory structure of the two E units, wherein the device has a data unit shown in FIG. ,, /, Kind of treatment early. Memory Zyikou—Wang Yiji memory and fast unit access. Both the blood penalty and the data can be obtained from the data processing cache memory: the main memory taken is the data processing unit fetched from the data management party, this M $ ^, a data element is from the main memory σ 5 in the cache memory for the fast storage of the data processing unit. Through the storage of data and particularly frequently stored data, in the cache memory, the time consumption access of the king memory can be avoided, and the processing speed of the data processing unit Will increase, making necessary information easier to use. In the second step of the method, a further data element (that is, a data element modified by the data processing unit) is written back to the cache memory location retrieved before the modification. In other words, the original data element in the cache is overwritten by the modified data element. However, since the modified data element is not written back to the main memory ’, the main memory contains a version of the data that is no longer updated; the memory is stale. Therefore, before more data is copied to main memory, an organization must be placed in a suitable place to avoid the loss of updated data in the cache memory. In the third step of the data management method, a bit pattern of different data is set to a bit pattern value to indicate the difference between the data element and the further data element. The value differs from the updated data element in the cache. This one-bit pattern is composed of a single bit, and then the single bit can hold two values, that is, it is used to represent the asset 86938 -15- 200415467 The physical data differs from the copy of the decision store, which indicates that these data elements are the same. ΎΤ... However, more complex bit patterns such as those used in similar MESI and MOESI agreements to share resource structures are equally feasible. When the data processing unit accesses the cache misregister to perform a write operation on one of these cache lines, the different 7C patterns of the data are evaluated, and if a bit pattern value is encountered, it is indicated in the main memory The data element of the body and the further data of the cache memory: In the same way, the step data element will be configured to be written back to the main memory before the write operation in the cache memory. This configuration includes Further data elements are stored in the temporary buffer. However, the fourth step of the data management method is when a data element whose value table is not in the main memory and the data element in the cache memory is advanced-step = ^ The different time-cache memory is provided before rewriting to write back to the king memory. When the progress-cache operation in the cache store causes irrelevant further data element conditions, the data: a. " It will be immediately set to -bit pattern in, ° 70 pattern + + ancestor-address cold * to show the existence of the hardware components in the cache memory in the cache, without the need to The further data element is written back to the main memory. An example of data that has not been saved in the cache memory becomes termination of the execution of the procedure or function call. On the blood penalty, the-+ unit will use stacking to store and process data such as functions, or programs. Each subroutine occupies a stack & for example, a stack frame, and the stack frame can be ^ or can be larger or smaller during the execution of the subroutine. The stack is usually kept in memory 86938 -16-200415467, but when it is expected that some special data will be accessed from time to time, a copy of the stack can be kept in cache memory. ^ Humble Factory Gu ...…, 叩, when the sub-routine order is completed, the data in the relevant stack frame will be < 雒 guan again. So, even if the data in the main memory related to the end subroutine is outdated, this data: new is unnecessary because it cannot be reused. 1 According to the present invention, from cache memory to main memory The time-consuming write-back allows the cache memory to be rewritten immediately by setting the different bit patterns of the phase-wide: line to one-bit pattern values. = 谙 This technician obviously knows that the data in the cache memory will become irrelevant in other environments; in applications like digital image processing, where-A modifies a digital audio or video data which is also replaced by down-sampling, ⑽ The contents of the cache memory will typically become irrelevant, and writing back to main memory becomes redundant 'and can also be avoided. Other useful fields of application can be performed by processing units that represent data as no longer using commands, such as the c-line " free " = and other examples can be used without departing from the description of the present invention. Typically, in the fourth step, the different bit patterns in the plurality of data related to the 7L pieces of the step-up data stored in the cache memory can be updated. : However, the data that becomes irrelevant is usually adjacent to the data element in the main memory, m '. So the fourth step usually includes the first reference of the Λ data element position in the main memory data element range, and the first reference from the main memory Based on the second reference of the last data element position of the plurality of data elements, a subsidiary step of selecting a plurality of further data with different bit patterns is selected. Subsequently, all the indicated main memory addresses in different value ranges are compared with the only addresses stored in the cache memory, and if the comparison finds the relevant bit pattern value 86938 200415467 疋 set to Table 7F-Bit pattern Value to indicate whether there is no difference between the cached progressive component and the main memory's data component. The first and second values can be provided as (referenced) addresses, but the second value can optionally be provided as the address reference offset of the first value. This is useful for implementations with fixed sizes of adjacent data blocks in main memory. This offset can be provided as a parameter (such as an argument) in the dedicated bit pattern update instruction.的 一个 电子 装置 200。 An electronic device 200. An electronic device is, for example, a central processing unit or a DSP. FIG. 1 shows that a device 200 for implementing the method of the present invention has a data processing unit 22 and can access a memory including a king memory 24 and a cache memory. structure. In this particular embodiment, the cache memory 26g includes: a plurality of locations 262 'to store different bit patterns of data; and a plurality of cache lines = 4, which are used to read data components and their main memory address information . Cache storage-the shell material can be controlled by the data management circuit 280 of the response data processing unit 22q. For the sake of the present invention, the data management circuit 28 has used additional hardware expansion to generate a complex number for the continuous range of data elements in the King Memory 240, to avoid writing irrelevant data back to the main memory 240. . The data management circuit 280 includes a data storage element 282 and a further data storage 2 file 284, which are respectively stored in the first parameter of the first data element in the Dusseldorf, and-the last data element in the IS gate. Second reference. The data storage element is called data !! The storage element 284 can be similar—small dedicated memory or a part of the dedicated data storage device that is not shown in the figure. It can be used to store the data in the main memory 2. A reference to a range boundary. 86938 -18 > 200415467 The field reference can be a poor address, or an index to this one, such as a bunch of ® indicators. The material management circuit 280 further includes a control circuit 286 that incrementally uses the data element range of the main memory 240 to generate further references to the location of the further data elements. Basically, the control circuit 286 includes a reference generator, and it is preferable to generate all further tests one by one from the first reference to the second reference. Since the target data element is located in a continuous range of the main memory 24, further reference or address generation in the control circuit 286 can be performed by well-known techniques. The control circuit 286 typically includes a comparison device not shown in the figure, which is used to compare a generated further reference with the first or second reference, which is determined by the upward or downward direction of the further reference to determine the further reference. Whether the reference generation is complete, in which case further reference generation ends. The control circuit 286 is coupled to the further control circuit 288 to obtain a first reference, or a generated further reference from the control circuit 286, and typically includes a further comparator not shown in the figure, for comparing the obtained reference with a plurality of The reference stored in cache line 264 is compared. If a comparison reference is found on the cache line 264, the different bit patterns of the related data stored at position 262 will be set to a value to indicate the further data elements in the cache memory 260 and the related data in the main memory 240 Is there no difference between the components. In the case of a single bit pattern, the bit can be set according to whether the content is the same or not. It is generally emphasized that although the plurality of positions 262 are described as an integral part of the cache storage "0", this is not strictly necessary to implement, and a plurality of positions 262 forming a separate table can also be implemented. Moreover, even the displayed information 86938 -19- The logic circuit 2 g ο is from the source. As early as 7 " 220 separate, but the general emphasis on the element 220 —-, + & 黾 280, etc. in the implementation of the data processing unit 22 〇 It is also possible to implement it. As early as in a specific embodiment of the present invention, Yiyili, a command set, t includes 4 processing early Wu 220 can respond to one finger to obtain emotion-exclusive instructions, to avoid redundant from fast = save: riding back To the main memory, typically, after the termination of a function call or a staff-like event, the 'execute exclusive command. This—refers to :: =! By the data processing unit 22. 7 has a wrong existence through the data data unit 220, respectively. The data storage element ΑΑ # τ 〇 ", the storage unit 284 is used as a parameter ^-reference and second reference. Or, the exclusive instruction can only include a single, for example, ^ like stored in the shell material processing unit 220-stacking index value, multiple partial teeth, and more. When the continuous range of the data element of the Wang Chongyi body is a fixed size, this will be special Alas, in this case, the offset defines the size of the data element range. Since the exclusive instruction is closely related to the processing of stacked indicators, the exclusive instruction can be combined with a stacked indicator processing instruction to reduce the number of instructions in the instruction spoon. As a result, the hardware and the hardware responsible for processing the stack index value are prevented from writing to the < cache memory 260 redundantly and written back to the main memory 24, which is advantageous from the viewpoint of area load. Head i, the rest of the figure is described for the figure. Unless otherwise specified, the corresponding reference numbers have the same meaning. FIG. 2 is another embodiment of the electronic device 200. The electronic device 2000 can be expanded with additional hardware 290 to monitor changes in the Membrane® indicator, or frame indicator, stored in the dedicated temporary storage 222 of the data processing unit 22. This can be achieved through the supervision of the actual register 222 in the search instruction, or through the instruction flow of the supervision data processing unit 22〇 86938 -20- 200415467, where, the search instruction can lead to the value in the register 222 Modify the J 1 ^ such as a push frame or a pop frame instruction. —Exclusive hardware 290 includes a register not shown in the figure and — = comparator circuit not shown in the figure to store a stack index value in the register and compare the register of the processing unit 220 Actual value of the stack indicator in 222. Apparently, when the dedicated hardware 290 is configured to supervise the stack index processing instruction, a comparator circuit not shown in the figure is not needed. If the change of the stacking index value can be observed to avoid the redundant writing from the cache memory 26 to the king memory 240, the stacking or frame index value of the stack that grows upwards decreases, or the stacking or frame that grows downwards the stack. When the indicator value increases, the dedicated hardware 290 will use the old and new values of the stack or frame indicator to supply the first data storage element 282 and the second data storage element 284, and trigger the data management private 280 to avoid saving from the cache. The device 260 redundantly writes back the address range of the king domain of the main memory 24, where the address range of the main memory is between the sales and the new value of the 隹 wu or Λ box index. It is generally pointed out that for this implementation, τ does not need a dedicated instruction to avoid redundant writeback; dedicated hardware 29 can take over the role of this instruction. FIG. 3 is described with reference to FIG. 2. Unless otherwise specified, corresponding reference numbers rarely have the same meaning. FIG. 3 shows the electronic device and extension shown in FIG. 2. Here is an example of Iff'in the part 263 of the cache line of the cache memory 26 () can carry an extra control bit, which is under the control of the step control circuit 2δδ-the current frame bit This indicates whether the accompanying cache line belongs to the content frame from the data processing unit 220 currently using the main memory. This -bit implementation on cache line 264 can be implemented in a well-known manner similar to the different bit patterns of the data. 86938 • 21 · 200415467 Well-known way, therefore, no further description will be made. Here is a specific implementation example, responsible for avoiding a portion of the data pipe from the cache, back to the main memory 240 from the 2600 Xi Yu Gong. The data storage element 282 and the second The data storage element 284 can be used by the data processing unit 2220 to use the boundary value of the frame range. A few further pieces of Aibei Village in the cache memory 260 (images of the data elements in the 'Shell file range from the main memory 240') are used in the position 263 of the cache line. Flag to indicate whether the frame accompanying the cache line belongs to the data frame used by the data processor 22. Currently, during the execution of operations other than operations related to the generation of writes from the cache memory 260 back to the main memory ，, the data processing unit 222 needs to rewrite the cache line 264 to transport the The current data frame used by the new data element is related to-step-by-step data. The new data element is indicated by the reference of the first data storage element 2 8 2 and the second data storage element 2 8 4 Whether the main memory position of the new data element is outside the range of the data frame currently used by the data processing unit 22 can be evaluated by the control circuit 286 in the aforementioned manner. When this is the case, the data management circuit 28 will evaluate the different bit patterns of the data at position 262 and, if necessary, force a write back to the main memory 240. In addition, the current frame bit of the relevant cache line 264 is set to a value 'to indicate whether the data on the cache line 264 is outside the range of the data frame currently used by the data processing unit 220. The advantage of this specific embodiment is that when the data management circuit 240 operates when the data management circuit 86938 • 22- 200415467 Road 280 is operated and avoids writing irrelevant data from the cache memory 26 to the main memory 24G ', it must only be evaluated in The current frame bit of the cache memory, rather than the row address reference in the cache line 264 of the cache memory 26. This indicates that the efficiency of the electronic device 2000 during this event has further improved. Clearly, when the data management circuit 280 is stimulated to write back irrelevant data, the different bit patterns of the data related to becoming irrelevant data will be set to further bit pattern values, and the current frame bit of the cache line 264 It will be reset and updated according to the new stack or frame used by the data processing table 220. > Wangyi, the above-mentioned specific embodiments are merely illustrations rather than limitations on the present invention. Those skilled in the art can design many optional specific embodiments without departing from it and then apply for patent coverage. In the scope of patent application, any reference sign in the middle will not constitute a limitation on the scope of patent application. The word, including, does not exclude elements or steps other than those listed in the scope of the patent application. The element magic does not exclude a plurality of this element. The present invention can be implemented by hardware including several pieces. Among the devices that apply for the listing of several device patents, several devices can be specific through an item of hardware and the same item. Some measures can be cited, and the scope of different patent applications does not indicate these. The combination of measures cannot be used to advantage. [Brief Description of the Drawings] The present & moonlight is described in more detail through non-limiting examples and drawings, in which: Fig. 1 shows a specific embodiment of an electronic device according to the present invention; Fig. 2 shows according to the present invention Another specific embodiment of an electronic device; and FIG. 3 shows still another specific implementation of an electronic device according to the present invention, 86938-23-23200415467. [Illustration of representative symbols of the figure] 200 electronic device 262 bad bit 264 cache line 220 data processing unit 240 main memory 260 cache memory 282 first data storage element 284 further data storage element 280 data management circuit 286,288 control circuit 222 exclusive Register 290 extra hardware 263 bit locations 86938-24-