WO2003104987A3 - Verfahren zum codieren/decodieren von vliw cached befehlen - Google Patents

Verfahren zum codieren/decodieren von vliw cached befehlen Download PDF

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Publication number
WO2003104987A3
WO2003104987A3 PCT/DE2003/001748 DE0301748W WO03104987A3 WO 2003104987 A3 WO2003104987 A3 WO 2003104987A3 DE 0301748 W DE0301748 W DE 0301748W WO 03104987 A3 WO03104987 A3 WO 03104987A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction word
tvliw
hvliw
instruction
processor
Prior art date
Application number
PCT/DE2003/001748
Other languages
English (en)
French (fr)
Other versions
WO2003104987A2 (de
Inventor
Helge Betzinger
Yuhi Tang
Original Assignee
Philips Semiconductors Dresden
Helge Betzinger
Yuhi Tang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Semiconductors Dresden, Helge Betzinger, Yuhi Tang filed Critical Philips Semiconductors Dresden
Priority to DE10393298T priority Critical patent/DE10393298D2/de
Priority to US10/516,675 priority patent/US20050246515A1/en
Priority to AU2003257376A priority patent/AU2003257376A1/en
Priority to EP03756954A priority patent/EP1509842A2/de
Priority to JP2004511991A priority patent/JP3981117B2/ja
Publication of WO2003104987A2 publication Critical patent/WO2003104987A2/de
Publication of WO2003104987A3 publication Critical patent/WO2003104987A3/de

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/447—Target code generation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

Die Erfindung betrifft ein Verfahren zur Ansteuerung von Funktionseinheiten in einem Prozessor, wobei in einer Konfigurationsphase eine aus einer Übersetzung eines Programmcodes stammende Folge von Primärinstruktionsworten eine Fraktionierung in eine Folge von Instruktionswortteile erfährt, wobei in einem Programmablauf den Prozessor ansteuernde Instruktionsworte in der vollen Instruktionswortbreite erzeugt und in einem Instruktionswortspeicher (Cache) zwischengespeichert werden. Die erfindungsgemässe Aufgabenstellung, in der Ausführungsphase eine Steigerung der Prozessorperformance durch Erhöhung des Komprimierungsgrad der Primärinstruktionsworte in ihre fraktionierten Instruktionswortteilen unabhängig von speziellen Merk malen (z. B. Periodizität) der FIW (Funktions-Instruktions-Wortteile) zu erreichen, wird dadurch gelöst, dass in der Konfigurationsphase in einem ersten Schritt die Fraktionierung eines Primärinstruktionswortes in ein TVLIW (Tagged Very Long Instruction Word) erfolgt und in einem zweiten Schritt wird jeweils das vorliegenden TVLIW in ein HVLIW (Headed Very Lang Instruction Word) gewandelt. In dem HVLIW wird ein General Header vorangestellt. Das HVLIW ersetzt mit seiner codeverdichteten Struktur alle Funktionen des TVLIW (1).
PCT/DE2003/001748 2002-06-05 2003-05-28 Verfahren zum codieren/decodieren von vliw cached befehlen WO2003104987A2 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE10393298T DE10393298D2 (de) 2002-06-05 2003-05-28 Verfahren zum codieren/decodieren von VLIW cached Befehlen
US10/516,675 US20050246515A1 (en) 2002-06-05 2003-05-28 Method for the coding/decoding of vliw cached instructions
AU2003257376A AU2003257376A1 (en) 2002-06-05 2003-05-28 Method for the coding/decoding of vliw cached instructions
EP03756954A EP1509842A2 (de) 2002-06-05 2003-05-28 Verfahren zum codieren/decodieren von vliw cached befehlen
JP2004511991A JP3981117B2 (ja) 2002-06-05 2003-05-28 キャッシュに記憶するｖｌｉｗ命令の符号化／復号化方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10225099 2002-06-05
DE10225099.5 2002-06-05

Publications (2)

Publication Number Publication Date
WO2003104987A2 WO2003104987A2 (de) 2003-12-18
WO2003104987A3 true WO2003104987A3 (de) 2004-12-29

Family

ID=29723087

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/001748 WO2003104987A2 (de) 2002-06-05 2003-05-28 Verfahren zum codieren/decodieren von vliw cached befehlen

Country Status (6)

Country Link
US (1) US20050246515A1 (de)
EP (1) EP1509842A2 (de)
JP (1) JP3981117B2 (de)
AU (1) AU2003257376A1 (de)
DE (1) DE10393298D2 (de)
WO (1) WO2003104987A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10142157B2 (en) * 2010-06-10 2018-11-27 Blackberry Limited Method and system for reducing transmission of redundant data
CN102662637B (zh) * 2012-03-30 2014-10-15 中国人民解放军国防科学技术大学 超长指令字处理器指令发射方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19859389C1 (de) * 1998-12-22 2000-07-06 Systemonic Ag Verfahren zur Ansteuerung von Funktionseinheiten in einem Prozessor und Prozessoranordnung zur Durchführung des Verfahrens

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6101592A (en) * 1998-12-18 2000-08-08 Billions Of Operations Per Second, Inc. Methods and apparatus for scalable instruction set architecture with dynamic compact instructions

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19859389C1 (de) * 1998-12-22 2000-07-06 Systemonic Ag Verfahren zur Ansteuerung von Funktionseinheiten in einem Prozessor und Prozessoranordnung zur Durchführung des Verfahrens

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WEISS M H ET AL: "DYNAMIC CODEWIDTH REDUCTION FOR VLIW INSTRUCTION SET ARCHITECTURES IN DIGITAL SIGNAL PROCESSORS", PROCEEDINGS IWISP. INTERNATIONAL WORKSHOP ON IMAGE AND SIGNAL PROCESSING ON THE THEME OF ADVANCES IN COMPUTATIONAL INTELLIGENCE, XX, XX, 4 November 1996 (1996-11-04), pages 517 - 520, XP000911908 *

Also Published As

Publication number Publication date
EP1509842A2 (de) 2005-03-02
AU2003257376A8 (en) 2003-12-22
AU2003257376A1 (en) 2003-12-22
WO2003104987A2 (de) 2003-12-18
JP2005529402A (ja) 2005-09-29
JP3981117B2 (ja) 2007-09-26
US20050246515A1 (en) 2005-11-03
DE10393298D2 (de) 2005-05-25

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