WO2003101002A1

WO2003101002A1 - Correlator method and apparatus

Info

Publication number: WO2003101002A1
Application number: PCT/IB2003/002246
Authority: WO
Inventors: Adrian W. Payne
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2002-05-29
Filing date: 2003-05-21
Publication date: 2003-12-04
Also published as: AU2003233001A1; GB0212326D0

Abstract

The present invention provides for a correlator arrangement for correlating a serial bit sequence and comprising a plurality of correlators each of which is arranged to correlate a respective part of the said bit sequence, the arrangement including means for separating the said bits sequence into the said respective parts, wherein there is an overlap between the said respective parts such that the bits in the overlapping portions of the said parts are received for correlation at the same time by more than one of the said plurality of correlators, the said plurality of correlators being arranged to produce respective correlation peaks, or so-called peaks, in response to the correlation result, which said respective pings are processed in order to produce a correlation output for the arrangement. Improved performance of the timing synchronisation can therefore be achieved without requiring additional measures such as the employment of a digital phase-locked-loop and the invention can find ready use in component intergraded circuits, radio receiver systems for use with, for example, Bluetooth and Zigbee and in particular for use in preamble/access code time alignment or for chip code detection in a spread spectrum system.

Description

DESCRIPTION

CORRELATOR METHOD AND APPARATUS

The present invention relates to a correlator apparatus and method.

Correlators are arranged to provide for the detection of the presence of a replica of a finite length reference binary code sequence appearing in a relatively I ong s ignal sequence o f b its. S uch d evices f ind m any a pplications such as in signal processing, spread spectrum communications, code synchronisation/detection, and error correction coding. Quite commonly, correlators are employed in radio receivers to detect the arrival of a modulated signal a nd i n an attempt to d etermine the time at which the received s ignal correlates most closely to the expected signal. Such timing information is then employed to enable demodulation of the remainder of the signal, which comprises an unknown sequence of data. The use of a correlator in this manner to determine the time of arrival of the signal comprises a particularly important aspect of a radio system in which the time of arrival is not otherwise accurately known or determined. However, it is considered that the accuracy with which known correlators function, and, in particular, can achieve timing synchronisation, will determine the performance of the receiver if no other means for optimising the synchronisation of the received signal, such as using a digital phase-locked- loop, are employed. Any error that arises in the timing synchronisation can disadvantageously lead to an increase in bit error rate, and further might cause frame error or other degradation in performance. For example, in a positioning system, a reduction in the accuracy of the positioning fix can occur.

The present invention seeks to provide for a correlator apparatus and method having advantages over known such apparatus and methods. According to one aspect of the present invention there is provided a correlator arrangement for correlating a serial bit sequence and comprising a plurality of correlators each of which is arranged to correlate a respective part of the said bit sequence, the arrangement including means for separating the said bit sequence into the said respective parts, wherein there is an overlap between the said respective parts such that bits in the overlapping portions of the said parts are received for correlation at the same time by more than one of the said plurality of correlators, the said plurality of correlators being arranged to produce respective correlation peaks in response to the correlation result, which said respective correlation peaks are processed in order to produce a correlation output for the arrangement.

If the correlation sequence is relatively long, and only one correlator is employed to correlate over the whole sequence, this would lead to relatively heavy processing demand. In correlating over shorter separated segments of the sequence by means of a plurality of smaller correlators, the processing requirements of each correlator are therefore reduced and the ping output from each correlator can be subsequently employed to provide an overall correlation result relating to the complete sequence.

In providing for the aforementioned overlap, the correlation length offered by each correlator is advantageously increased without increasing the total length over which the signal is correlated. This means that each correlator can then be arranged to produce a stronger correlation, relative to noise, and thus a more easily distinguishable correlation peaks, or ping, than would be the case with non-overlapping correlators. Preferably, the said plurality of respective parts comprises a series of overlapping sequential segments of the serial bit sequence.

Yet further, the present invention can be arranged such that a portion of the serial bit sequence received is only delivered to a single correlator so as to be correlated only once. This has the advantage of reducing the influence of those bits. For example, delivering some initial received bits has the advantage of reducing the influence of those initial bits on the timing synchronisation determination which can enhance the overall accuracy of the arrangement since the initial bits received can often contain inaccuracies due to an inaccurate DC offset correction.

Further, the invention can be advantageously arranged such that a predetermined, or variable, weighting can be applied to each correlator such that the pings produced therefrom are weighted so as to further enhance the accuracy of the arrangement. For example, if one of the said plurality of correlators contains a long sequence of 1s and 0s, then the correlation thereby offered maybe less accurate and so its output can be appropriately weighted by, for example, multiplication of its output by a constant which would be less than 1 to reduce the output's weight, or greater than 1 , to increase the output's weight.

As will be appreciated, the output pings from the said plurality of correlators are advantageously processed in an appropriate manner so as to provide a correlation result for the complete arrangement. Such processing of the output pings advantageously serves to produce an output result offering greater resolution than if a single ping were derived merely from the single long correlator as known in the art. Such greater resolution arises since the ping is narrower in the present invention.

Preferably, the processing step employs the alignment in time of the outputs of all of the said plurality of correlators. Normalisation of the multiple correlator outputs, for example to 1 , to the maximum value of the outputs, and quantisation steps, can be employed so as to assist with the processing and the plurality of signals can then be clipped at a value, for example, 0.25, so as to assist with the identification of a ping output from each of the plurality of correlators. Any signal below the 0.25 clipping threshold is then lost.

The plurality of signals then obtained from the said plurality of correlators can be multiplied together in order to produce a single signal output comprising a single ping.

The arrangement can advantageously be adapted such that where any one of the output signals from the said plurality of correlators is a value of 0 due to the above-mentioned clipping, there is no need to multiply such values together since it can be predetermined that the output of such multiplication will in any case be 0 and this can advantageously reduce the processing operations required.

The output signals obtained can then be readily processed to refine the signal and determine the actual time of the maximum value corresponding to the output ping of the arrangement.

According to another aspect of the present invention, there is provided a method of correlating a serial bit sequence, comprising the steps of separating the said bit sequence into a plurality of parts, delivering the said plurality of parts to a respective plurality of correlators in a manner such that there is an overlap between the said respective parts such that bits in the overlapping portions of the said parts are received for correlation at the same time by more than one of the said plurality of correlators.

Preferably the bit sequence is divided into a series of overlapping sequential segments. Also, an initial series of bits of the bit sequence can be delivered to any one correlator.

The method may also include the step of selectively weighing the outputs of the said plurality of correlators.

Advantageously the method includes the steps of delaying the output of at least one of the correlators so as to align output pings therefrom. Yet further, the method may include the step of multiplying the outputs from the said plurality of correlators.

The invention is described further hereinafter, by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a schematic view of a correlator according to the prior-art;

Fig. 2 is a schematic view of a correlator arrangement according to an embodiment of the present invention; and

Fig. 3 is a graphical representation of a simulated comparison between a correlator arrangement embodying the present invention, and a correlator according to the prior-art. Turning first to Fig. 1 , there is illustrated, in schematic form, a correlator currently known in the prior-art and which comprises a matched filter arrangement 10. The matched filter arrangement 10 comprises a shift register 12 for receiving the incoming bit sequence, and a shift register 14 arranged to receive a reference bit sequence for comparison with the bit sequence received in the shift register 12. The bit sequence received by the shift register 12 with the correlator 10 arrives at the correlator by way of the input 16.

With reference to the location 18 of the most recent bit received in the shift register 12, and its comparison with the corresponding location 20 in the reference register 12, it will be appreciated that the bit values in each locations 18, 20 are delivered to a logical XOR gate 26 and the output thereof is delivered to an adder 28 for summation with the output from an adjacent XOR gate.

This prior-art matched filter arrangement will produce a peak output, referred to as a ping, when a sequence of bits received in the shift register 12 corresponds to an expected sequence of bits of the same l ength p reloaded into the shift register 14. The sequences of bits are generally over-sampled for accurate timing synchronisation and the output 30 from the matched filter arrangement is known to be further processed by averaging/filtering the signal, or by using curve-fitted techniques, in order to seek to achieve timing synchronisation.

However, the accuracy and operation of such known correlators is disadvantageously limited.

Turning now to Fig. 2, there is illustrated an embodiment of the present invention in which, rather than employing merely a single matched filter correlator, a plurality, in the illustrated example of four, of correlators are employed.

As illustrated, the correlator arrangement 32 embodying the present invention therefore comprises four separate matched filter correlators 34-40 which are arranged to receive respective parts of a input bit sequence as recovered and obtained by a demodulator/slicer 42. The manner in which an incoming bit sequence 44 for the correlator arrangement 32 is divided into four parts for the four matched filters 34-40 respectively is also illustrated schematically in Fig. 2. As will be appreciated, the four parts 46-52 are each 22 bits in length and are provided as an overlapping sequence in which the first 11 bits of each segment overlap with the last 11 bits of the preceding segment as illustrated from the comparison of segments 48 with 46, 50 with 48 and 52 with 50.

It will therefore be appreciated that, in this illustrated example, the complete bit sequence length as demodulated and separated at the demodulator/slicer 42 is 55 bits. Such a length is common as found in an access code as used in accordance with a Bluetooth arrangement.

Thus, as illustrated, each of the separate correlators 34-40 is arranged to correlate over 22 bits of the overall 55 bit sequence, and there is an overlap of 11 bits between the parts 46-52 corresponding to each of the correlators 34- 40. From the timing represented by reference to the schematic illustration 44 of the complete bit sequence, it will be appreciated that the four correlators 34-40 produce four successive pings which are 11 bits apart but which are subsequently p rocessed so a s to p roduce a single, relatively accurate p ing, which can advantageously be employed for timing synchronisation. In the illustrated example, the outputs of the correlators 34, 36 and 38 are delivered to respective delay elements 54, 56 and 58 each of which is arranged to introduce a different value of delay. For example, the delay 54 introduces a 33 bit delay, the delay 56 introduces a 22 bit delay and the delay 58 introduces an 11 bit delay. No delay however is introduced to the output from the correlator 40 which is simply delivered, by means of line 60, to a processor 62 for combining and processing each of the four outputs derived from the correlators 34-40 and so as to produce an output time of arrival signal 64 relevant to the complete bit sequence 44.

As will be appreciated from the magnitude of delays introduced by the delays 54-58, the correlator results d elivered f rom t he correlators 34-40 a re therefore delivered to the processor 64 at the same time. One particular advantage of the arrangement illustrated in Fig. 2 is that the first 1 1 bits of the segment 46 are in fact only correlated once, in the correlator 34, and therefore have less impact on the timing synchronisation determination. This can prove particularly advantageous insofar as the first bits of the serial bit sequence 44 are often found to contain inaccuracies due to inaccurate DC offset corrections.

It is appreciated that a correlation over a relatively short sequence of data will not produce a strong correlation, and so will not therefore produce an easily distinguishable ping. The invention is particularly advantageous in that, in order to increase the correlation length, without increasing the total length over which the signal is correlated, the successive correlators 34-40 are arranged to correlate overlapping segments of the bit sequence and so the bits in the overlapping portions are correlated in more than one of the correlates 34-40. Although not illustrated in Fig. 2, the invention can provide for the weighting of the pings produced from the correlators 34-40. That is, if one of the correlators 34-40 is considered to contain a long sequence of 1 s and 0s, then its correlation may be found to be less accurate, so that the weighting of the ping produced can be reduced in some manner. The invention allows for the weighing of the individual correlators 34-40 in a responsive manner that will, overall, give the most likelihood of producing a strong correlation with the received signal.

At the start of reception of a packet, it is necessary to estimate and then cancel the unwanted and unknown DC offset of the received signal, until this is achieved accurately, the correlator will not produce a strong correlation. Therefore, reducing the importance of the first portion of the signal relative to the whole correlation as mentioned above can prove advantageous in this regard. This can be achieved by lowering the weight the first correlator or, as in the illustrated example, merely allowing for this initial portion of the signal to be correlated by only one of the 4 of the plurality of correlators 34-40. In the alternative discussed above, it may be determined that the data sequence the correlator contains a long sequence of 1 s, or 0s, and as this means that there is less information in this portion of the signal, it can be determined to reduce the weight of this portion of the signals. Or yet further, if it is known that there is a regular repetitive interfering signal that will coincide with some portion of the received signal, then it can be determined to reduce the weight of such a portion of the signal. The weighting of each correlator 34-40 can advantageously be achieved, in a responsive manner, relative to the others, by inclusion of a multiplication factor on the output ping of the correlator by a multiplication constant which, to reduce the weighting, would be less than 1 , or to increase the weighting, would be greater than 1. Returning to Fig. 2, it should be appreciated that the series of pings output from the correlators 34-40 produces a series of estimates of where the received signal 44 is aligned with an expected signal. The processor 62 can be arranged to function as follows.

When all but the last correlator have completed their correlation, the multiple outputs are aligned in time. The multiple correlator outputs can then be n ormalised, for example to 1 , to the maximum value of a ll of them. The signals can then be quantised to a lower word-length and so the subsequent processing can be conducted at a relatively low word-length.

The multiple signals are next clipped at some value above 0, say 0.25 and so the signals will not be 0 except when a ping arises.

The multiple signals are then multiplied together (i.e. all of the corresponding samples from each signal are multiplied together) to produce a single signal that should comprise a single ping. Where any one of the signals has a value of 0, because of previous clipping, there is then no need to multiply these values together because the output of the multiplication will be zero. This can significantly reduce the processing operations required.

The signals can be processed in conventional manner to refine the signal and determine the time of the maximum value and any further processing would typically include some averaging/filtering. A configuration of the invention based on the figure shown above has been simulated in Signal Processing Workstation (SPW) a software tool from Cadence Design System Inc. A further simulation can be employed for the summation of the timing synchronisation error (TSE) over one hundred packets. The results are plotted as a function of signal strength for the overlapping correlator and a conventional matched filter (single correlator SC) and are illustrated in Fig. 3. This shows that there is significant improvement in timing synchronisation through the use of the overlapping correlator. It is anticipated that more careful refinement of the processing technique used to resolve the timing from the multiple correlator (MC) outputs could produce even better performance than is shown in this figure. From Fig. 3 however it will be noticed that at very low signal-to-noise ratios, the overlapping correlator starts to degrade more rapidly and becomes worse than the matched filter. This is because at low signal-to-noise ratios, the shorter correlations do not produce pings that are sufficiently higher than the peaks produce by the noise. In practice, however the point at which the overlapping correlator starts to perform badly is at a signal-to-noise ratio that is well below a level that can be usefully demodulated.

In order to then identify the time at which a ping occurs conventional processing can be employed. For example, if it is known that the ping should occur within a specified time window, and a delay can be tolerate, then one can use a simple technique of storing the output of the correlator during the time window and then choosing the maximum value.

If it is not convenient to tolerate a delay then it will be necessary to spot the maxima of the ping exactly as it happens.

Further, if it is possible to reset the receiver repeatedly every time it is determined that previously it was a false alarm but not the ping really has occurred, then it will be necessary merely to detect the maximum value so far determined.

In order to detect a maxima in a signal, if can prove appropriate to detect that the signal was previously increasing but now is falling. To reduce the likelihood of falsely detecting pings in the noise, it could be arranged to detect that the signal was previously increasing at greater than a particular rate but now is falling at grater than a particular rate. Typically it would be required to integrate the signal to identify the rate of change of the signal.

Further it could prove suitable to make use of the time window in which the signal is expected to arrive. For example if there are two identical peaks one could choose the peak that is closest to the centre and the signal could be weighted maximum at the centre of the window.

Also, since the correlation usually has two minimas either side of maxima, i.e. when the correlation is maximally dissimilar, one could look for these minimas as well as the maxima to aid detecting the real maxima in the noise.

From close inspection of the maxima, i.e. the ping, it may not look like a smooth single maxima in the signal. Instead, typically at low signal to noise ratio, it may look somewhat amorphous.

To improve the accuracy with which the exact time of arrival can be detected, the signal could be arranged or filtered in a sliding window of a suitable width relative the expected width of the ping. This would advantageously serve to clean up the maxima.

It would also prove possible to detect the middle of the maxima by taking the average time of each edge of the maxima as this may be more accurate than the centre of the maxima, i.e. use a more mathematical approach. This could involve fitting a straight line to each edge of the maxima and seeing where they coincide.

It will therefore be appreciated that the present invention provides for a modified form of correlator that can detect accurately, for example, he arrival of a radio signal modulated with a known sequence of bits. The correlator can be employed for timing synchronisation by selecting a time of arrival at which the incoming signal is most correlated with reference data.

Improved p erformance of the timing synchronisation c an therefore be achieved without requiring additional measures such as the employment of a digital phase-locked-loop and the invention can find ready use in component intergraded circuits, radio receiver systems for use with, for example, Bluetooth and Zigbee and in particular for use in preamble/access code time alignment or for chip code detection in a spread spectrum system.

Claims

1. A correlator arrangement (32) for correlating a serial bit sequence (44) and comprising a plurality of correlators (34-40) each of which is arranged to correlate a respective part (46-52) of the said bit sequence (44), the arrangement including means (42) for separating the said bit sequence (44) into the said respective parts (46-52), wherein there is an overlap between the said respective parts (46-52) such that bits in the overlapping portions of the said parts (46-52) are received for correlation at the same time by more than one of the said plurality of correlators (34-40) , the said plurality of correlators (34-40) being arranged to produce respective correlation peaks in response to the correlation result, which said respective correlation peaks are processed in order to produce a correlation output for the arrangement (32).

2. An arrangement as claimed in Claim 1 , wherein the said respective parts (46-52) comprise a series of overlapping sequential segments of the bit sequence (44).

3. An arrangement as claimed in Claim2, wherein a series of bits representing an initial portion of the bit sequence (44) and as found within the first (46) of the said respective parts (46-52) is delivered only to one of the said plurality of correlators (34-40).

4. An arrangement as claimed in any one of Claims 1-3, wherein a weighting factor is introduced into the outputs of each of the said plurality of correlators (34-40).

5. An arrangement as claimed in any one of Claims 1-4, wherein the Correlation peaks obtained from the said plurality of the correlators (34-40) are delivered to a processing means (62) for the processing thereof so as to produce a single output correlation peak (64) relevant to the said serial bit sequence (44).

6. An arrangement as claimed in any one the preceding claims, and including delay means (54-58) for delaying the outputs from at least one of the said plurality of correlators (34-40) so as to align the correlation peaks therefrom in time.

7. An arrangement as claimed in any one or more of the preceding claims, wherein the outputs from each of the said plurality of correlators (34- 40) are multiplied together within the processing means (62) in order to produce a single signal exhibiting a single correlation peak.

8. A method of correlating a serial bit sequence (44), comprising the steps of separating the said bit sequence into a plurality of parts (46-52), delivering the said plurality of parts (46-52) to a respective plurality of correlators (34-40) in a manner such that there is an overlap between the said respective parts (46-52) such that bits in the overlapping portions of the said parts are received for correlation at the same time by more than one of the said plurality of correlators (34-40).

9. A method as claimed in Claim 8, wherein the bit sequence (44) is divided into a series of overlapping sequential segments.

10. A method as claimed in Claim 9, wherein an initial series of bits of the bit sequence is delivered to only one correlator (34).

11. A method as claimed in Claim 8, 9 or 10, and including the step of selectively weighing the outputs of the said plurality of correlators (34-40).

12. A method as claimed in Claim 8, 9, 10 or 11 , including the steps of delaying the output of at least one of the correlators (34-40) so as to align output correlation peaks therefrom.

13. A method as claimed in any one or more of Claims 8 to 12, including the step of multiplying the outputs form the said plurality of correlators (34-40).