WO2003096328A1

WO2003096328A1 - Disc device signal processing device

Info

Publication number: WO2003096328A1
Application number: PCT/JP2003/005301
Authority: WO
Inventors: Koichi Tada; Shigekazu Minechika; Yoshihiro Aoi; Koichi Ogawa; Ichizo Sakamoto
Original assignee: Sanyo Electric Co., Ltd.
Priority date: 2002-05-07
Filing date: 2003-04-24
Publication date: 2003-11-20
Also published as: JP2003323720A

Abstract

A disc device signal processing device includes a VGA to which two different gain control voltages are applied and the VGA amplifies an FCM signal by the gain corresponding to the gain control voltage applied. The FCM signals amplified have peak levels detected by a peak hold circuit. According to the gain control voltages applied to the VGA and the peak levels detected by the peak hold circuit, a DSP approximates the VGA characteristic by a quadratic curve. According to this quadratic curve, an optimal gain control voltage where the optimal peak level can be obtained is calculated. The VGA amplifies the FCM signal according to the optimal gain control voltage calculated.

Description

Specification

FIELD OF THE INVENTION Field of the Invention

The present invention relates to a signal processing device for a disk drive, and more particularly to, for example, rotating a disk recording medium in which a track is formed on a recording surface and a predetermined mark is formed on the track at predetermined intervals, and a laser beam is applied to the recording surface. The present invention relates to a disk device that detects a predetermined mark signal related to a predetermined mark by irradiating the mark, and executes a predetermined process based on the predetermined mark signal.

Conventional technology

On a magneto-optical disk such as an ASMO (Advanced Storage Magnetic Disk), predetermined marks such as an FCM (Fine Clock Mark) and an address mark are formed at predetermined intervals on a track. Various operations such as speed adjustment are controlled based on the FCM signal and the address mark signal detected from the reflected light when the FCM and the address mark are traced.

However, the peak levels of the FCM signal and the address mark signal vary depending on the difference in the magneto-optical disc and the difference in the characteristics of the optical pickup. Therefore, the FCM signal and the address mark signal may not be properly distinguished from the detected FCM signal and the address mark signal.

Therefore, a gain control voltage is applied to each VGA (Variable Gain Amplifier) to which the FCM signal or the address mark signal is input, and the FCM signal or the address mark signal is amplified to reduce the peak level. It is always constant. That is, the peak level of the FCM signal and the address mark signal is determined by the gain control voltage. Conventionally, the determination of the gain control signal has been performed as follows. First, two types of gain control voltages are applied to the VGA, and the peak level of each FCM signal or address mark signal is measured. Next, the measured two points are approximated by a straight line. Then, a desired gain control voltage is obtained by substituting a desired peak level into this linear equation.

By the way, the conventional VGA has, for example, a gain setting range of 1 dB to 10 dB. had. However, this gain setting width was not enough to absorb the variation in the peak level of the FCM signal and the address mark signal due to the difference in the reflectivity of the magneto-optical disk and the difference in the laser power. For this reason, a VGA with a wider gain setting range, for example, −10 dB to +10 dB, has been used.

However, in VGA having a wide gain setting range, the peak levels of the FCM signal and the address mark signal change exponentially with respect to the gain control voltage. Therefore, if the characteristics of the VGA that changes exponentially are approximated by a straight line as in the past, there is a problem that the error increases. Summary of the Invention

Therefore, a main object of the present invention is to provide a novel disk drive.

It is another object of the present invention to provide a signal processing device for a disk device, which can appropriately determine a signal reproduced from a disk even when a peak level fluctuates.

According to a first aspect of the present invention, in a signal processing device for performing predetermined signal processing on an amplified signal amplified by an amplifying means to which a control voltage is applied, a specification for specifying at least two control voltages in which a peak level of the amplified signal exceeds a threshold value Means, estimating means for estimating a quadratic function indicating the amplification characteristic of the amplifying means based on the control voltage specified by the specifying means and a peak level corresponding to the control voltage, and an amplified signal based on the quadratic function A signal processing apparatus comprising: a calculating unit that calculates an optimum control voltage at which a peak level of the control signal becomes an optimum level.

According to a second aspect of the present invention, in a signal processing device for performing predetermined signal processing on an amplified signal amplified by an amplifying unit to which a control voltage is applied, a memory means for storing a reference amplification characteristic; Measuring means for measuring the first peak level of the amplified signal amplified by the means, detecting means for detecting the second peak level corresponding to the reference control voltage with reference to the reference amplification characteristic, first peak level of the second peak level Means for multiplying the target peak level by the ratio to A signal processing device comprising a specifying unit that specifies a control voltage corresponding to a multiplied value of a multiplying unit as an optimum control voltage with reference to the multiplying unit.

In the first invention, the specifying means specifies at least two control voltages at which the peak level of the amplified signal exceeds the threshold. Based on the control voltage specified by the specifying means and the peak level corresponding to the control voltage, a quadratic function indicating the amplification characteristic of the amplifying means is estimated by the estimating means. Based on the quadratic function, the optimum control voltage at which the peak level of the amplified signal becomes the optimum level is calculated by the calculating means. Then, the optimum control voltage is applied to the amplifier, and the signal is amplified to the optimum level by the amplifier.

In the second invention, the reference amplification characteristic of the amplification means is stored in the memory means. The first peak level of the amplified signal amplified by the amplification means to which the reference control voltage has been applied is measured by the measurement means. The second peak level corresponding to the reference control voltage is detected by the detection unit with reference to the reference amplification characteristic. The ratio of the second peak level to the first peak level is multiplied by the multiplying means by the target peak level. The control voltage corresponding to the multiplied value by the multiplying means is specified as the optimum control voltage by the specifying means with reference to the reference amplification characteristic. Then, the optimum control voltage is applied to the amplifier, and the signal is amplified to the optimum level by the amplifier.

According to these inventions, the optimum control voltage for the amplifying means is determined based on a quadratic function that approximates the output characteristics of the amplifying means, or the optimum control voltage is determined by using the output characteristics serving as the reference of the amplifying means. Since the control voltage is determined, a more precise optimal control voltage can be obtained. Therefore, the predetermined mark signal can be amplified to the optimum level, so that the predetermined mark signal can be properly determined even when the peak level fluctuates due to the difference between the magneto-optical disks and the characteristic of the optical pickup.

The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is an illustrative view showing an entire configuration of an embodiment of the present invention. FIG. 2 is an illustrative view explaining a state of an FCM and an address mark.

Figure 3 is a circuit diagram showing the photodetector, TE signal detection circuit, FE signal detection circuit, and FCM signal detection circuit.

FIG. 4 is a waveform diagram showing the address mark signal.

FIG. 5A is a waveform diagram showing an FCM signal detected from a land track, and FIG. 5B is a waveform diagram showing an FCM signal detected from a groove track. FIG. 6 is a graph showing the signal characteristics of a VGA that amplifies the FCM signal.

FIG. 7 is a flowchart showing a part of the operation of the DSP.

FIG. 8 is a flowchart showing another part of the operation of the DSP.

FIG. 9 is a flowchart showing another part of the operation of the DSP.

FIG. 10 is a graph showing how the optimum gain control voltage is obtained.

FIG. 11 is a flowchart showing a part of the operation of the DSP.

FIG. 12 is a flowchart showing another part of the operation of the DSP.

FIG. 13 is a flowchart showing another part of the operation of the DSP. BEST MODE FOR CARRYING OUT THE INVENTION

Referring to FIG. 1, an optical disk device 10 of this embodiment includes an optical pickup 12 provided with an optical lens 14. The optical lens 14 is supported by the tracking function 16 and the focus function 18, and the laser light emitted from the laser diode 20 is converged by such an optical lens 14. The recording surface of the magneto-optical disk 50 such as ASM〇 is irradiated. As a result, desired data is recorded on the magneto-optical disk 50 or reproduced from the magneto-optical disk 50.

As shown in FIG. 2, land tracks and groove tracks are alternately formed every other track on the surface of the magneto-optical disk 50, and FCM and address marks are embossed at predetermined intervals on each track. Formed by Specifically, the land track is formed in a convex shape, and the FCM on the land track is formed in a concave shape. On the other hand, the groove track is formed in a concave shape, and the FCM on the group track is formed in a convex shape. Also, the address mark is 301

It is formed so as to undulate (wobble) on the track boundaries, and the amplitude of this wave is equivalent to 1Z2 of each track width. Therefore, the address mark is formed in a concave shape on the land track and is formed in a convex shape on the groove track. In FIG. 2, the hatched portion is a concave portion, and the white portion is a convex portion. Returning to FIG. 1, the reflected light from the recording surface passes through the optical lens 14 and irradiates the photodetector 22. The output of the photodetector 22 is input to an FE signal detection circuit 24, a TE signal detection circuit 26, and an FCM signal detection circuit 28, which detect a FE (Focus Error) signal, a TE (TrackingError) signal, and an FCM signal, respectively. Is done. The optical detector 22, the FE signal detection circuit 24, the TE signal detection circuit 26, and the FCM signal detection circuit 28 are configured as shown in FIG. The photodetector 22 is composed of four detection elements 22a to 22d. The outputs of the detection elements 22a to 22d are different in the FE signal detection circuit 24, the TE signal detection circuit 26, and the FCM signal detection circuit 28. Is calculated. Specifically, equation (1) is calculated in the FE signal detection circuit 24, equation (2) is calculated in the TE signal detection circuit 26, and equation (3) is calculated in the FCM signal detection circuit 28.

FE = (A + C) ― (B + D)… (1)

TE = (A + D) one (B + C)… (2)

FCM = (A + B)-(C + D)… (3)

Note that “A” to “D” in Expressions (1) to (3) correspond to the outputs of the detection elements 22 a to 22 d, respectively. The detection elements 22a and 22d detect the left half light component of the laser light in the tracing direction, and the detection elements 22b and 22c detect the right half light component of the laser light in the tracing direction.

The FE signal and the TE signal are supplied to a DSP (Digital Signal Processor) 40 via A / D converters 42a and 42b, respectively. The DSP 44 executes a focus servo process based on the FE signal, and executes a tracker servo process and a thread sample process based on the TE signal. A focus work control signal is generated by the focus servo process, and is output to the focus work 18 via the D / A converter 42b. In addition, a tracking actuating control signal is generated by the tracking serpo process, and is output from the DZA converter 42a. It is output on the 16th of tracking practice. Further, a thread control signal is generated by the thread support process, and is output from the D / A converter 42 c to the thread motor 48.

As shown in Fig. 2, the swing width of the address mark occupies 1/2 of each track width, and as can be seen from Fig. 2 and equation (2), the TE signal is a half of the left half laser light component from the left half laser light component. It is generated by subtracting the laser light component. Therefore, in the tracking state where the laser light traces the center of the track, the level of the TE signal fluctuates according to the unevenness of the address mark as shown in FIG. This fluctuation is much larger than the fluctuation based on the tracking deviation, and the fluctuation component generated by scanning such an address mark is defined as an address mark signal.

The address mark signal is supplied to a peak hold circuit 32 and an address detection circuit 34 via a VGA (Voltage Controlled Amplifier) 30. The peak hold circuit 32 detects the peak level of the address mark signal, and outputs a peak hold signal indicated by a chain line in FIG. This peak hold signal is input to the DSP 44 via the A / D converter 42c, and the DSP 44 generates a gain control signal for controlling the gain of the VGA 30 based on the input peak hold signal. I do. The generated gain control signal is supplied to the VGA 30 via the DZA converter 46e, whereby the level of the address mark signal is adjusted.

The FCM signal output from the FCM signal detection circuit 28 is supplied to the peak hold circuit 38 and the FCM processing circuit 40 via the VGA 36. The FCM signal changes as shown in FIG. 5A when the laser beam scans over the land track, and changes as shown in FIG. 5B when the laser beam scans over the groove track. The peak hold circuit 32 detects such a peak level of the FCM signal and outputs a peak hold signal indicated by a chain line in FIG. 5 (A) or FIG. 5 (B). The output peak hold signal is supplied to the AZD converter 42 (03 44 via 1). The DSP 44 generates a VGA 36 gain control signal based on the input peak hold signal, and generates the generated gain control signal. Is supplied to the VGA 36 via the D / A converter 46 d. Therefore, the level of the FCM signal is also adjusted based on the gain control signal. The address detection circuit 34 detects an address value from the address mark signal whose level has been adjusted by the VGA 30, and inputs the detected address value to the signal processing circuit 41. On the other hand, the FCM processing circuit 40 performs processing such as land group discrimination based on the FCM signal whose level has been adjusted by the VGA 36, and provides the processing result to the signal processing circuit 41. The signal processing circuit 41 generates a timing signal based on the input address value and the determination result, and the DSP 44 performs processing in response to the generated timing signal. The gain setting range of VGA30 and VGA36 is -10 dB to +10 dB, which is wider than conventional ones.

As shown in FIG. 6, the peak level of the address mark signal included in the output from the TE signal detection circuit 26 and the peak level of the FCM signal output from the FCM signal detection circuit 28 are shown in FIG. There are variations due to differences in the magneto-optical disk 50 and differences in the optical pick-up 12). Therefore, in order to properly determine the FCM signal address mark signal and properly perform processing using the FCM signal and address mark signal, the gain of VGA 30 and VGA 36 should be adjusted appropriately and peak level variations should be reduced. It needs to be suppressed.

Therefore, in the disk device 10 of this embodiment, the gain control signal is determined as follows. First, the peak level of the FCM signal or the address mark signal is actually measured at two points (points A and B) where the peak level of the FCM signal or the address mark signal is equal to or higher than a predetermined signal level. . Next, the slope between points A and B is calculated. Using the calculated slope, a straight line connecting points A and B is approximated by a quadratic curve, and a gain control signal is calculated from the quadratic curve. In the VGA30 and VGA36, in which the gain setting width is wider than before, the peak levels of the FCM signal and the address mark signal change exponentially with respect to the gain control voltage. Therefore, by approximating points A and B with a quadratic curve, it is possible to approximate with less error than with linear approximation.

The operation of the DSP 44 will be described below with reference to the flowcharts shown in FIGS. Although the DSP 44 is actually formed by a logic circuit, a flow diagram is used for convenience of explanation.

First, focus servo and tracking are performed in steps SI, S3 and S5 in Fig. 7. 5301

Execute support and thread support. That is, a tracking work overnight control signal, a focus work overnight control signal and a thread control signal are generated based on the FE signal and the TE signal taken from the A / D converters 42a and 42b. Output from the DZA converter 46a to 46c. Subsequently, in steps S7 and S9, the peak level adjustment of the FCM signal and the peak level adjustment of the address mark signal are respectively performed. When the peak level adjustment is completed, the AZD converters 4 2e and 4e in step S11. 4 Perform various controls based on the output of f.

The FCM peak level adjustment processing in step S7 is executed according to the subroutine shown in FIG. First, in step S21, output to the D / A converter 46d

Set the output (gain control voltage) to VGA 36 (shown as "DA" in the flow chart) to 0.5 V.

Next, in step S23, it is determined whether the output to the DZA converter 46d is 2.3 V. When the output to the D / A converter 46 d is 2.3 V or more, abnormal termination at step S 47 occurs because the peak level of the FCM signal cannot be obtained, as can be seen from Fig. 6. I do. On the other hand, when the output to the DZA converter 46 d is not 2.3 V, the process proceeds to step S 25.

In step S25, the currently set gain control voltage is applied to the VGA 36 via the D / A converter 46d, and the peak level of the FCM signal is measured in step S27. Then, the current gain control voltage is stored in the work area Ax, and the peak level of the FCM signal, which is the measurement result, is stored in the work area Ay. If the peak level of the FCM signal has the characteristics of curve 3 shown in Fig. 6, the coordinates in the graph in Fig. 6

(x, y) = (A x, Ay) is the first A point. When the work area is simply described as Ax or Ay, it indicates a value stored in the work area A x or the work area Ay. The same applies to the following work areas.

In step S29, it is determined whether the measured peak level of the FCM signal is lower than 1.0 V. If the peak level of the FCM signal is lower than 1.0 V, the gain control voltage is increased by 0.2 V in step S31, and the process returns to step S23. In step S25, the currently set gain control voltage is again converted to DZA It is applied to the VGA 36 via the detector 46d, and the peak level of the FCM signal is measured in step S27. Then, the current gain control voltage is stored in the work area Ax, and the peak level of the FCM signal, which is the measurement result, is stored in the work area Ay. Thus, the coordinates of point A are updated.

When the peak level of the FCM signal is lower than 1.0 V, as shown in FIG. 6, the slope of the graph is gentle, and the error increases when the curve is approximated by a quadratic curve. Therefore, the part where the peak level of the FCM signal is lower than 1.0 V is excluded. On the other hand, when the peak level of the FCM is equal to or higher than 1.0 V, the process exits the loop including Step S23 to Step S31. When exiting the loop, point A is determined by the values stored in query area Ax and work area Ay.

Then, the axis of x = Ax becomes the temporary y axis, and the current peak level (Ay) of the FCM signal becomes the intercept b on the temporary y axis. In FIG. 6, in curve 1, x = 0 (dB) is the provisional y-axis, and the intercept b is 1.0. In curve 2, x = -l 0 (dB) is the temporary y-axis, and the intercept b is 1.25. Then, in curve 3, x = -6 (dB) is the temporary y axis, and the intercept b is 1.0. In step S33, the gain control voltage is increased by 0.2 V, and in step S35, the updated gain control voltage is applied to the VGA 36 via the DZA converter 46d. In step S37, the peak level of the FCM signal is measured. The gain control voltage updated in step S33 is stored in the work area Bx, and the peak level measured in step S37 is stored in the private area By. Thus, the coordinates (X, y) = (Bx, By) are determined as point B.

Next, in step S39, the slope a of the spring AB connecting point A and point B is calculated according to equation (4), and the calculated value of slope a is stored in work area a.

a = (By-Ay) / (Bx— Ax)… (4)

In step S41, the line segment AB is approximated by the quadratic curve shown in equation (5). In step S43, equation (6) obtained by transforming equation (5) is added to the target FCM The optimum gain control voltage corresponding to the target peak level of the FCM signal is calculated by substituting the signal peak level value. Optimal gain obtained in this way T / JP03 / 05301

The control voltage is applied to the VGA 36 via the DZA converter 46 d in step S45. As a result, the FCM signal having the target peak level is output from the VGA 36.

y = a · c · x ² + b… (5)

Here, c is a coefficient based on a rule of thumb.

The address level adjustment processing in step S9 is performed according to a subroutine shown in FIG. 9, and this subroutine is applied to the application destination of the gain control voltage output in step S65, step S75, and step S85. Is VGA30, and is the same as Sakare chin shown in FIG. 8 except that the signal for measuring the peak level in step S67 and step S77 is an address mark signal.

As can be seen from the above description, two different gain control voltages are applied to the VGA 36, and the VGA 36 amplifies the FCM signal with a gain according to the applied gain control voltage. The peak level of each amplified FCM signal is detected by a peak hold circuit 38. DSP 44 uses a quadratic curve to determine the characteristics of VGA 36 based on each gain control voltage applied to VGA 36 and each peak level detected by peak hold circuit 38. Approximate. Then, based on the quadratic curve, the optimum gain control voltage at which the optimum peak level is obtained is calculated. The VGA 36 amplifies the FCM signal based on the calculated optimal gain control voltage. The optimum gain control voltage is calculated for the address mark signal in the same manner as described above, and the calculated optimum gain control voltage is applied to the VGA 30.

As described above, since the characteristics of the VGA are approximated by the quadratic curve, a more strict optimal gain control voltage can be obtained. Therefore, even when the peak level fluctuates due to the difference between the magneto-optical disks and the difference between the characteristics of the optical pickup, the FCM signal address mark signal can be appropriately determined.

In this embodiment, the peak level of the positive polarity of the FCM signal or the address signal is detected in order to calculate the optimum gain control voltage, but the peak level of the negative polarity is detected. You may. In other words, the peak level of the negative polarity of the FCM signal (or address mark signal) amplified with two different gains is The optimum gain control voltage can also be obtained by performing a predetermined calculation on the above two gains and the corresponding two peak levels, which are detected by a bias circuit.

In the following embodiment, the relationship between the standard gain control voltage and the peak level of the FCM signal (VGA characteristics) is stored in advance as a table, and the optimal gain control voltage is determined using this table. By applying the optimum gain control voltage to the VGA 36, the level of the FCM signal is adjusted. The same applies to the level adjustment of the address mark signal.

More specifically, referring to FIG. 10, first, the peak level of the FCM signal when the gain control voltage is 1.5 V (OdB) is actually measured. Let this measurement point (1.5, a) be point A. Next, referring to the table, obtain the peak level of the FCM signal when the gain control voltage is also 1.5V (OdB). Let this score (1.5, b) be point B. Then, the ratio r of the peak level of the FCM signal between the points A and B is calculated, and the target ratio of the FCM peak level is divided by the calculated ratio r to correspond to the target FCM peak level α (gain (The control voltage is the same.) Find the FCM peak level on the table] 3. Finally, referring to the table, the (optimal) gain control voltage X corresponding to the FCM peak level 3 is obtained. Then, the optimum gain control voltage X is applied to the VGA 36.

The operation of the DSP 44 will be described below with reference to FIGS. 11 to 13. Although the DSP 44 is actually formed by a logic circuit, a flow diagram is used for convenience of explanation.

The processing of the main routine shown in FIG. 11 is the same as the operation of FIG. 7 of the previous embodiment except for the processing of step S107 and step S109.

The FCM level adjustment processing in step S107 is executed according to the subroutine shown in FIG. First, in step S121, a 1.5V harvest control voltage is applied to the VGA 36, and in step S123, the FCM peak level at point A (see FIG. 10) is measured. If the measurement result at this time is a, the coordinates of point A are (1.5, a).

Next, in step S125, the gain control voltage is set to 1.5 Get the FCM peak level at V. If the value of the FCM peak level obtained at this time is b and the obtained point is point B, the coordinates of point B are (1.5, b).

In step S127, the ratio r of the gain control voltage between the actually measured value (point A) and the table value (point B) is calculated according to equation (7).

r = a / b… (7)

Here, let the target FCM peak level be, and let X be the gain control voltage when the FCM peak level becomes one. That is, X is the optimal gain control voltage. The point at the coordinates (, x) is point C in FIG. Then, the FCM peak level corresponding to the gain control voltage X on the table is set to / 3. The point at the coordinates (β, X) is point D in FIG. Then, since it is considered that Expression (8) holds, Expression (9) is further obtained from Expression (8), and Expression (9) is calculated in Step S129.

a: b = «:] 3… (8)

β = (b / a) = / τ… (9)

Then, in step SI31, a gain control voltage X corresponding to the FCM peak level] 3 is obtained by referring to the table. This gain control voltage is the optimum gain control voltage that can obtain the target FCM peak level α when applied to the VGA 36. In step S133, the optimum gain control voltage X thus obtained is applied to the VGA.

The address level adjustment processing in step S109 is executed in accordance with the subroutine shown in FIG. 13. In this subroutine, the application destination of the gain control voltage output in step S141 and step S153 is VGA30. This is the same as the subroutine shown in FIG. 12, except that the signal for measuring the peak level in S143 is an address mark signal.

As can be seen from the above description, in this embodiment, first, the FCM peak level a was actually measured at the point where the gain control voltage was 1.5 V, and the gain control voltage was set to 1.5 times using a table prepared in advance. The standard FCM peak level b at V is obtained, and the ratio r between the FCM peak levels a and b is obtained. Next, the target FCM peak The level ratio is given by the ratio r, and the FCM peak level | 8 on the corresponding table is obtained with the same gain control voltage as the FCM peak level α. Then, the gain control voltage X corresponding to the FCM peak level / 3 is obtained by referring to the table. The target FCM peak level α can be obtained by applying the obtained optimal gain control voltage X to the VGA.

As described above, the gain control voltage corresponding to the target FCM peak level is calculated using the ratio between the value in the standard VGA characteristic held in the take-up and the measured value, so that a more strict The optimum gain control voltage can be obtained. Therefore, even if the peak level of the signal fluctuates due to the difference between the magneto-optical disks and the difference in the characteristics of the optical pickup, the FCM signal address mark signal can be appropriately determined.

While this invention has been described and illustrated in detail, it is obvious that it is used by way of illustration and example only and should not be construed as limiting, the spirit and scope of the invention being attached to Limited only by the language of the claim.

Claims

The scope of the claims

1. A signal processing device for performing predetermined signal processing on an amplified signal amplified by an amplification unit to which a control voltage is applied,

Specifying means for specifying at least two control voltages in which the peak level of the amplified signal exceeds a threshold,

Estimating means for estimating a quadratic function indicating an amplification characteristic of the amplifying means based on the control voltage specified by the specifying means and a peak level corresponding to the control voltage; and

A signal processing device, comprising: calculating means for calculating an optimum control voltage at which a peak level of the amplified signal becomes an optimum level based on the quadratic function.

2. The signal processing device according to claim 1, wherein the estimating unit sets a lowest peak level exceeding the threshold value as an intercept of the quadratic function.

3. A signal processing device for performing predetermined signal processing on an amplified signal amplified by an amplifying means to which a control voltage is applied,

Memory means for storing a reference amplification characteristic,

Measuring means for measuring a first peak level of an amplified signal amplified by the amplifying means to which the reference control voltage is applied;

Detecting means for detecting a second peak level corresponding to the reference control voltage with reference to the reference amplification characteristic;

Multiplying means for multiplying a target peak level by a ratio of the second peak level to the first peak level; and

A signal processing device comprising: a specifying unit that specifies a control voltage corresponding to a multiplied value of the multiplying unit as an optimum control voltage with reference to the reference amplification characteristic.

4. A signal processing device according to any one of claims 1 to 3, wherein a disk recording medium having tracks formed on a recording surface and marks formed at predetermined intervals on the tracks is detachably held. Further comprising holding means,

The amplifying unit amplifies a mark signal reproduced from the disk recording medium held by the holding unit and related to the mark.