JP2003323720A - Signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To properly discriminate an FCM signal, even if a peak level varies by the difference of a disk or the characteristic of an optical pickup. <P>SOLUTION: Two mutually different gain control voltages are impressed by VGA 36, and the VGA 36 amplifies the FCM signal by the gains, corresponding to the impressed gain control voltages. Peak levels for each amplified FCM signal are detected by a peak hold circuit 38. A DSP 44 approximates the characteristic of the VGA 36 by a quadratic curve, based on each gain control voltage impressed by the VGA 36 and each peak level detected by the peak hold circuit 38. Then, the optimal gain control voltage to be obtained by the optimal peak level based on the quadratic curve is calculated. The VGA 36 amplifies the FCM signal, based on the derived optimal gain control voltage. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk device, and more particularly, to, for example, rotating a disk recording medium in which tracks are formed on a recording surface and predetermined marks are formed on the tracks at predetermined distances, and a laser is formed on the recording surface. The present invention relates to a disk device that emits light to detect a predetermined mark signal related to a predetermined mark, and executes predetermined processing based on the predetermined mark signal.

[0002]

2. Description of the Related Art ASMO (Advanced Storage Magneto O
For magneto-optical disks such as ptical disks, FCM (F
predetermined marks such as ine clock mark) and address marks are formed at predetermined intervals on the track, and various operations such as disk rotation speed adjustment are detected from the reflected light when tracing the FCM and address marks. FC
It is controlled based on the M signal and the address mark signal.

However, the peak levels of the FCM signal and the address mark signal vary depending on the difference between the magneto-optical disks and the characteristics of the optical pickup. Therefore, the detected FCM signal and address mark signal as they are may not be able to properly determine the FCM signal and address mark signal.

Therefore, each VGA (Variable Gai) to which the FCM signal or the address mark signal is input
n Amplifier) is applied with a gain control voltage to amplify the FCM signal or the address mark signal so that the peak level is always constant.

That is, depending on the gain control voltage, F
The peak levels of the CM signal and the address mark signal are determined. Conventionally, the determination of the gain control signal has been performed as follows. First, two gain control voltages are set to V
It is applied to GA and the peak level of each FCM signal or address mark signal is measured. Next, the measured two points are approximated by a straight line. Then, the desired gain control voltage is obtained by substituting the desired peak level into this linear expression.

[0006]

By the way, the conventional VG
A has, for example, a gain setting range of -4 dB to +4 dB. However, in this gain setting range, F due to the difference in the reflectance of the magneto-optical disk and the difference in the laser power
It was not sufficient to absorb the variation in the peak level of the CM signal and the address mark signal. Therefore, a VGA having a wider gain setting range than that of the related art, such as −10 dB to +10 dB, has come to be used.

However, in a VGA having a wide gain setting range, the peak levels of the FCM signal and the address mark signal change exponentially with respect to the gain control voltage. Therefore, if the characteristic of the VGA that changes exponentially is approximated by a straight line as in the conventional case, there arises a problem that the error becomes large.

Therefore, a main object of the present invention is to provide a disc device capable of appropriately discriminating a signal reproduced from a disc even when the peak level fluctuates.

[0009]

According to a first aspect of the present invention, in a signal processing device for subjecting an amplified signal amplified by an amplifying means to which a control voltage is applied to a predetermined signal processing, a peak level of the amplified signal exceeds a threshold value. Specifying means for specifying at least two control voltages; estimating means for estimating a quadratic function indicating the amplification characteristic of the amplifying means based on the control voltage specified by the specifying means and the peak level corresponding to the control voltage; It is a signal processing device comprising a calculating means for calculating an optimum control voltage at which a peak level of an amplified signal becomes an optimum level based on a quadratic function.

According to a second aspect of the present invention, in a signal processing device for subjecting an amplified signal amplified by an amplifying means to which a control voltage is applied to a predetermined signal processing, a memory means for storing a reference amplification characteristic and a reference control voltage are applied. Measuring means for measuring the first peak level of the amplified signal amplified by the amplifying means, detecting means for detecting the second peak level corresponding to the reference control voltage by referring to the reference amplification characteristic, and first detecting means for the second peak level. It is a signal processing device comprising: multiplication means for multiplying a ratio to a peak level by a target peak level; and identification means for identifying a control voltage corresponding to a multiplication value of the multiplication means with reference to a reference amplification characteristic as an optimum control voltage.

[0011]

In the first aspect of the present invention, the specifying means specifies at least two control voltages in which the peak level of the amplified signal exceeds the threshold value. The estimating means estimates the quadratic function indicating the amplification characteristic of the amplifying means based on the control voltage specified by the specifying means and the peak level corresponding to the control voltage. Based on the quadratic function, the calculating means calculates the optimum control voltage at which the peak level of the amplified signal becomes the optimum level. Then, the optimum control voltage is applied to the amplification means, and the amplification means amplifies the signal to the optimum level.

In the second invention, the reference amplification characteristic of the amplification means is stored in the memory means. The first amplified signal amplified by the amplifying means to which the reference control voltage is applied.
The peak level is measured by the measuring means. The second peak level corresponding to the reference control voltage is detected by the detection means with reference to the reference amplification characteristic. The ratio of the second peak level to the first peak level is multiplied by the target peak level by the multiplication means. By referring to the reference amplification characteristic, the control voltage corresponding to the multiplication value by the multiplication means is specified as the optimum control voltage by the specifying means. And
The optimum control voltage is applied to the amplifying means, and the amplifying means amplifies the signal to the optimum level.

[0013]

According to these inventions, the optimum control voltage for the amplifying means is determined based on the quadratic function approximating the output characteristic of the amplifying means, or the output characteristic serving as the reference of the amplifying means is utilized. Since the optimum control voltage is determined by using such a method, a stricter optimum control voltage can be obtained. Therefore, since the predetermined mark signal can be amplified to the optimum level, the predetermined mark signal can be properly discriminated even when the peak level changes due to the difference in the magneto-optical disk and the characteristic in the optical pickup.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, an optical disk device 10 as a signal processing device of this embodiment includes an optical pickup 12 provided with an optical lens 14. The optical lens 14 is
The laser diode 2 is supported by the tracking actuator 16 and the focus actuator 18.
The laser light emitted from 0 is such an optical lens 1
It is converged at 4 and irradiated onto the recording surface of the magneto-optical disk 50 such as ASMO. As a result, desired data is recorded on the magneto-optical disk 50 or the magneto-optical disk 5 is recorded.
Played from 0.

As shown in FIG. 2, the surface of the magneto-optical disk 50 has one land track and one groove track.
It is formed alternately every other track, and each track has an FCM
And address marks are formed at predetermined intervals by embossing. Specifically, the land track is formed in a convex shape, and the FCM on the land track is formed in a concave shape. On the other hand, the groove track is formed in a concave shape, and the FCM on the groove track is formed in a convex shape. Further, the address mark is formed so as to undulate (wobble) on the boundary line between two adjacent tracks,
The swing width of this wave corresponds to 1/2 of each track width. Therefore, the address mark is formed in a concave shape on the land track and is formed in a convex shape on the groove track. Note that, in FIG. 2, the hatched portion is a concave portion, and the white portion is a convex portion.

Returning to FIG. 1, the reflected light from the recording surface passes through the optical lens 14 and is applied to the photodetector 22. The output of the photodetector 22 is input to the FE signal detection circuit 24, the TE signal detection circuit 26, and the FCM signal detection circuit 28, and the FE (Focus Error) signal and the TE (Track
ing Error) signal and the FCM signal are detected. Photodetector 22, FE signal detection circuit 24, TE signal detection circuit 2
6 and the FCM signal detection circuit 28 are configured as shown in FIG. The photodetector 22 has four detection elements 22a-2.
2d, and the outputs of the detection elements 22a to 22d are
FE signal detection circuit 24, TE signal detection circuit 26 and F
Different calculation is performed in the CM signal detection circuit 28. Specifically, the FE signal detection circuit 24 calculates the number 1, the TE signal detection circuit 26 calculates the number 2, and the FCM signal detection circuit 28 calculates the number 3.

[0018]

[Formula 1] FE = (A + C)-(B + D)

[0019]

[Equation 2] TE = (A + D)-(B + C)

[0020]

[Formula 3] FCM = (A + B) − (C + D) Formula 1
“A” to “D” in the equation 3 are the detection elements 22a, respectively.
Corresponding to the output of ~ 22d. The detection elements 22a and 22d detect the light component of the left half of the laser light in the tracing direction, and the detection elements 22b and 22c detect the light component of the right half of the laser light in the tracing direction.

The FE signal and the TE signal are sent to the DSP (Digital Signal P) via the A / D converters 42a and 42b.
rocessor) 40 respectively. DSP44
Focus servo processing is executed based on the FE signal, and T
Tracking servo and sled servo processing is executed based on the E signal. A focus actuator control signal is generated by the focus servo processing and is output to the focus actuator 18 via the D / A converter 42b. Further, a tracking actuator control signal is generated by the tracking servo processing and output from the D / A converter 42a to the tracking actuator 16. Further, a sled control signal is generated by the sled servo processing, and is output from the D / A converter 42c to the sled motor 48.

As shown in FIG. 2, the deflection width of the address mark occupies ½ of each track width, and the TE signal has a left half laser light component to a right half laser light as can be seen from FIG. It is generated by subtracting the components. Therefore, in the tracking state in which the laser beam traces the center of the track, the level of the TE signal fluctuates as shown in FIG. 4 according to the unevenness of the address mark. This variation is significantly larger than the variation due to tracking deviation,
The fluctuation component caused by such scanning of the address mark is particularly defined as an address mark signal.

The address mark signal is VGA (Voltage).
It is given to the peak hold circuit 32 and the address detection circuit 34 via the controlled amplifier 30. The peak hold circuit 32 detects the peak level of the address mark signal and outputs the peak hold signal indicated by the alternate long and short dash line in FIG. This peak hold signal is input to the DSP 44 via the A / D converter 42c, and the DSP 44
Is a VGA based on the input peak hold signal.
A gain control signal is generated that controls the gain of 30. The generated gain control signal is transferred to the VGA via the D / A converter 46e.
30 and adjusts the level of the address mark signal.

F output from the FCM signal detection circuit 28
The CM signal is supplied to the peak hold circuit 3 via the VGA 36.
8 and the FCM processing circuit 40. The FCM signal is shown in FIG. 5 when the laser beam scans the land track.
It changes as shown in FIG. 5A, and changes as shown in FIG. 5B when the laser beam scans on the groove track.
The peak hold circuit 32 detects the peak level of such an FCM signal and outputs the peak hold signal shown by the alternate long and short dash line in FIG. 5A or 5B. The output peak hold signal is given to the DSP 44 via the A / D converter 42d. The DSP 44 generates a gain control signal for the VGA 36 based on the input peak hold signal, and supplies the generated gain control signal to the VGA 36 via the D / A converter 46d. Therefore, the FCM
The level of the signal is also adjusted based on the gain control signal.

The address detection circuit 34 detects an address value from the address mark signal whose level has been adjusted by the VGA 30, and inputs the detected address value to the signal processing circuit 41. On the other hand, the FCM processing circuit 40 uses the VGA
Based on the FCM signal whose level has been adjusted by 36, processing such as land / groove discrimination is performed, and the processing result is given to the signal processing circuit 41. The signal processing circuit 41 generates a timing signal based on the input address value and the determination result, and the DSP 44 performs processing in response to the generated timing signal. VGA30 and VG
The gain setting range of A36 is -10 dB to +10 dB, which is wider than the conventional one.

The peak level of the address mark signal included in the output from the TE signal detection circuit 26 and the peak level of the FCM signal output from the FCM signal detection circuit 28 are as shown in FIG. Examples of signals) vary depending on the difference in the magneto-optical disk 50 and the difference in the optical pickup 12. Therefore, in order to properly discriminate the FCM signal and the address mark signal and correctly perform the processing using the FCM signal and the address mark signal, the VGA3
It is necessary to properly adjust the gains of 0 and VGA 36 to suppress the peak level variation.

Therefore, in the disk device 10 of this embodiment, the gain control signal is determined as follows. First, F
The peak level of the FCM signal or the address mark signal is actually measured at two points (points A and B) where the peak level of the CM signal or the address mark signal is equal to or higher than a predetermined signal level. Next, the slope between the points A and B is calculated. Then, using the calculated inclination, the straight line connecting the points A and B is approximated by a quadratic curve, and the gain control signal is calculated from this quadratic curve. In the VGA 30 and the VGA 36 in which the gain setting width is wider than in the conventional case, the peak levels of the FCM signal and the address mark signal change exponentially with respect to the gain control voltage. Therefore, by approximating the points A and B with a quadratic curve, the error can be approximated with less error than the linear approximation.

The operation of the DSP 44 will be described below with reference to the flow charts shown in FIGS. In addition, DSP44
Although actually formed by a logic circuit, a flow diagram is used for convenience of description.

First, steps S1, S3 and S5 of FIG.
To execute focus servo, tracking servo and sled servo. That is, the tracking actuator control signal, the focus actuator control signal and the sled control signal are generated based on the FE signal and the TE signal fetched from the A / D converters 42a and 42b, and output from the D / A converters 46a to 46c. Then, in steps S7 and S9, the peak level adjustment of the FCM signal and the peak level adjustment of the address mark signal are respectively executed, and when the peak level adjustment is completed, various types are output based on the outputs of the A / D converters 42e and 42f in step S11. Execute control.

The FCM peak level adjustment processing in step S7 is executed according to the subroutine shown in FIG. First, in step S21, the output to the D / A converter 46d (indicated by "DA" in the flowchart), that is, VGA3
The output to 6 (gain control voltage) is set to 0.5V.

Next, in step S23, it is determined whether or not the output to the D / A converter 46d is 2.3V. When the output to the D / A converter 46d is 2.3 V or higher, as can be seen from FIG. 6, the peak level of the FCM signal cannot be obtained, and the process ends abnormally in step S47. On the other hand, when the output to the D / A converter 46d is not 2.3V, the process proceeds to step S25.

In step S25, the currently set gain control voltage is supplied to the VGA 36 via the D / A converter 46d.
And the peak level of the FCM signal is measured in step S27. Then, the current gain control voltage is stored in the work area Ax, and the peak level of the FCM signal as the measurement result is stored in the work area Ay. When the peak level of the FCM signal has the characteristic of the curve 3 shown in FIG. 6, the coordinates (x, y) = (Ax, Ay) in the graph of FIG. 6 become the first point A. When the work area is simply described as Ax or Ay, it indicates the value stored in the work area Ax or the work area Ay. The same applies to the work areas that appear below.

In step S29, it is determined whether the measured peak level of the FCM signal is lower than 1.0V. If the peak level of the FCM signal is lower than 1.0V, the gain control voltage is set to 0.2 in step S31.
V is increased and the process returns to step S23. Step S2
In step S27, the gain control voltage currently set again is applied to the VGA 36 via the D / A converter 46d, and the step S27 is performed.
At, the peak level of the FCM signal is measured. Then, save the current gain control voltage in the work area Ax,
The peak level of the FCM signal as the measurement result is saved in the work area Ay. In this way, the coordinates of point A are updated.

When the peak level of the FCM signal is lower than 1.0 V, the slope of the graph is gentle as shown in FIG. 6, and the error becomes large when approximated by a quadratic curve. Therefore, the portion where the peak level of the FCM signal is lower than 1.0V is excluded.

On the other hand, when the peak level of the FCM is 1.0 V or higher, the loop composed of steps S23 to S31 is exited. The point A is determined by the values stored in the work areas Ax and Ay when the loop is exited.

Then, the axis of x = Ax becomes a temporary y-axis,
The current peak level (Ay) of the FCM signal is a temporary y
It is the intercept b on the axis. In FIG. 6, in curve 1, x = 0 (dB) is a temporary y-axis, and the intercept b is 1.
It becomes 0. In the curve 2, x = −10 (dB) is the temporary y axis, and the intercept b is 1.25. Then, in the curve 3, x = −6 (dB) becomes the temporary y axis, and the intercept b becomes 1.0.

In step S33, the gain control voltage is set to 0.2.
The voltage is increased by V, and in step S35, the updated gain control voltage is applied to the VGA 36 via the D / A converter 46d. In step S37, the peak level of the FCM signal is measured. The gain control voltage updated in step S33 is stored in the work area Bx, and the peak level measured in step S37 is stored in the work area By. In this way, the coordinates (x, y) = (Bx, By) are determined as point B.

Next, in step S39, points A and B
The slope a of the line segment AB connecting with the point is calculated according to equation 4, and the calculated value of the slope a is stored in the work area a.

[0039]

## EQU00004 ## a = (By-Ay) / (Bx-Ax) Then, in step S41, the line segment A is formed by the quadratic curve shown in Expression 5.
B is approximated, and in step S43, the peak level value of the target FCM signal is substituted into the formula 6 obtained by modifying the formula 5, and the optimum gain control corresponding to the peak level of the target FCM signal is performed. Calculate the voltage. The optimum gain control voltage thus obtained is set to D in step S45.
It is applied to the VGA 36 via the / A converter 46d. As a result, the FCM signal having the target peak level is output from the VGA 36.

[0040]

[Number 5] ^{y = a · c · x 2} + b However, c is a factor that is based on the rule of thumb.

[0041]

[Equation 6]

The address level adjustment processing in step S9 is executed according to a subroutine shown in FIG. 9, and this subroutine includes steps S65 and S.
The application destination of the gain control voltage output in step S75 and step S85 is the VGA 30, and the signal is the same as the subroutine shown in FIG. 8 except that the signal for measuring the peak level in step S67 and step S77 is the address mark signal.

As can be seen from the above description, two different gain control voltages are applied to the VGA 36,
36 is a FCM with a gain according to the applied gain control voltage.
Amplify the signal. The peak level of each amplified FCM signal is detected by the peak hold circuit 38. The DSP 44 sets the characteristics of the VGA 36 to 2 based on each gain control voltage applied to the VGA 36 and each peak level detected by the peak hold circuit 38.
It is approximated by a quadratic curve. Then, the optimum gain control voltage with which the optimum peak level is obtained is calculated based on this quadratic curve. The VGA 36 amplifies the FCM signal based on the calculated optimum gain control voltage. For the address mark signal, the optimum gain control voltage is calculated in the same manner as described above, and the calculated optimum gain control voltage is V
It is applied to GA30.

Since the VGA characteristic is approximated by the quadratic curve as described above, a more strict optimum gain control voltage can be obtained. Therefore, the FCM signal and the address mark signal can be properly discriminated even when the peak level fluctuates due to the difference in the magneto-optical disk and the characteristic in the optical pickup.

In this embodiment, in order to calculate the optimum gain control voltage, the positive peak level of the FCM signal or the address signal is detected, but the negative peak level is detected. It may be. That is, the negative peak level of the FCM signal (or address mark signal) amplified with two different gains is detected by the peak hold circuit, and a predetermined calculation is performed on the above-mentioned two gains and the two peak levels corresponding thereto. The optimum gain control voltage can also be obtained by applying it.

In the following embodiment, the relationship between the standard gain control voltage and the peak level of the FCM signal (VGA characteristic).
Is previously held as a table, the optimum gain control voltage is determined using this table, and the optimum gain control voltage is applied to the VGA 36 to adjust the level of the FCM signal. The same applies to the level adjustment of the address mark signal.

More specifically, referring to FIG. 10, first, the FCM when the gain control voltage is 1.5V (0 dB)
Measure the peak level of the signal. This measurement point (1.5,
Let a) be point A. Next, referring to the table, the peak level of the FCM signal when the gain control voltage is also 1.5 V (0 dB) is acquired. This acquisition point (1.5, b)
Is point B. Then, the ratio r of the peak levels of the FCM signals at the points A and B is calculated, and the target FCM peak level α is divided by the calculated ratio r to correspond to the target FCM peak level α (gain control voltage The FCM peak level β on the table is obtained. Finally, referring to the table, the (optimal) gain control voltage x corresponding to the FCM peak level β is obtained. Then, the optimum gain control voltage x is applied to the VGA 36.

The operation of the DSP 44 will be described below with reference to the flow charts shown in FIGS. In addition, DSP44
Is actually formed by a logic circuit, but for convenience of description, a flow chart is used.

The processing of the main routine shown in FIG. 11 is the same as the operation of FIG. 7 of the previous embodiment except for the processing of steps S107 and S109.

The FCM level adjustment processing in step S107 is executed according to the subroutine shown in FIG. First, in step S121, a gain control voltage of 1.5 V is applied to the VGA 36, and in step S123, the FCM peak level at point A (see FIG. 10) is measured. Assuming that the measurement result at this time is a, the coordinates of the point A are (1.5, a).

Next, in step S125, the FCM peak level when the gain control voltage is 1.5 V is acquired by referring to the table. If the value of the FCM peak level acquired at this time is b and this acquisition point is point B, the coordinates of point B are (1.5, b).

In step S127, the ratio r of the gain control voltage between the actually measured value (point A) and the table value (point B) is calculated according to equation 7.

[0053]

## EQU00007 ## where r = a / b, where the target FCM peak level is .alpha.
The gain control voltage when the M peak level becomes α is x. That is, x is the optimum gain control voltage. The point at this coordinate (α, x) is point C in FIG. 10. And
The FCM peak level corresponding to the gain control voltage x on the table is β. The point of this coordinate (β, x) is shown in FIG.
It is point D at 0. Then, since it is considered that the equation 8 is established, the equations 8 to 9 are further obtained, and the step S
At 129, the equation 9 is calculated.

[0054]

## EQU8 ## a: b = α: β

[0055]

Β = α (b / a) = α / r Then, in step S131, the table is referred to
The gain control voltage x corresponding to the FCM peak level β is acquired. This gain control voltage x is an optimum gain control voltage that can obtain the target FCM peak level α when applied to the VGA 36.

In step S133, the optimum gain control voltage x thus obtained is applied to the VGA 36.

The address level adjustment processing in step S109 is executed according to the subroutine shown in FIG. 13. In this subroutine, the application destination of the gain control voltage output in step S141 and step S153 is V.
This is the same as the subroutine shown in FIG. 12, except that the signal is the GA30 and the signal for measuring the peak level in step S143 is the address mark signal.

As can be seen from the above description, in this embodiment, first, the FCM peak level a is measured at the point where the gain control voltage is 1.5 V, and the gain control voltage is 1. Standard FC at 5V
M peak level b is acquired and FCM peak levels a and b are acquired.
The ratio r of Next, the target FCM peak level α is divided by the ratio r to obtain the FCM peak level β on the corresponding table with the same gain control voltage as the FCM peak level α. Then, referring to the table, the gain control voltage x corresponding to the FCM peak level β is acquired. By applying the optimum gain control voltage x thus obtained to the VGA, the target FCM peak level α can be obtained.

As described above, the gain control voltage corresponding to the target FCM peak level is calculated using the ratio between the value in the standard VGA characteristic held in the table and the actually measured value. The optimum gain control voltage can be obtained. Therefore, the FCM signal and the address mark signal can be properly discriminated even when the peak level of the signal fluctuates due to the difference of the magneto-optical disk and the characteristic of the optical pickup.

[Brief description of drawings]

FIG. 1 is an illustrative view showing the overall configuration of an embodiment of the present invention.

FIG. 2 is an illustrative view for explaining states of FCM and address marks.

FIG. 3 is a circuit diagram showing a photodetector, a TE signal detection circuit, an FE signal detection circuit, and an FCM signal detection circuit.

FIG. 4 is a waveform diagram showing an address mark signal.

FIG. 5A is an FCM detected from a land track.
It is a waveform diagram which shows a signal, (B) is a waveform diagram which shows the FCM signal detected from the groove track.

FIG. 6 is a graph showing signal characteristics of a VGA that amplifies an FCM signal.

FIG. 7 is a flowchart showing a part of the operation of the DSP.

FIG. 8 is a flowchart showing another portion of the operation of the DSP.

FIG. 9 is a flowchart showing another portion of the operation of the DSP.

FIG. 10 is a graph showing how to find an optimum gain control voltage.

FIG. 11 is a flowchart showing a part of the operation of the DSP.

FIG. 12 is a flowchart showing another portion of the operation of the DSP.

FIG. 13 is a flowchart showing another portion of the operation of the DSP.

[Explanation of symbols]

10 ... Disk device 12 ... Optical pickup 30 ... VGA (Variable Gain Amplifier) 32 ... Peak hold circuit 36 ... VGA (Variable Gain Amplifier) 38 ... Peak hold circuit 44 ... DSP (Digital Signal Processor) 50 ... Magneto-optical disk

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoshihiro Aoi             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Koichi Ogawa             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Ichizo Sakamoto             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. F term (reference) 5D044 BC06 CC04 DE38 FG05 FG07                       GK18                 5D075 AA03 CC23                 5D090 AA01 BB10 CC04 CC18 DD03                       EE13 GG26

Claims (4)

[Claims] 1. A signal processing apparatus for subjecting an amplified signal amplified by an amplifying means to which a control voltage is applied to a predetermined signal processing, to specify at least two control voltages whose peak level of the amplified signal exceeds a threshold value. Means, an estimating means for estimating a quadratic function indicating an amplification characteristic of the amplifying means based on the control voltage specified by the specifying means and a peak level corresponding to the control voltage, and the estimating means for estimating the quadratic function based on the quadratic function. A signal processing device, comprising: a calculating unit that calculates an optimum control voltage at which a peak level of an amplified signal becomes an optimum level. 2. The signal processing apparatus according to claim 1, wherein the estimating means sets the lowest peak level exceeding the threshold value as an intercept of the quadratic function. 3. A signal processing device for performing a predetermined signal processing on an amplified signal amplified by an amplifying means to which a control voltage is applied, a memory means for storing a reference amplification characteristic, and the amplifying means to which the reference control voltage is applied. Measuring means for measuring the first peak level of the amplified signal amplified by the means, detecting means for detecting the second peak level corresponding to the reference control voltage by referring to the reference amplification characteristic, and the second peak level. Signal processing comprising: multiplication means for multiplying a target peak level by a ratio to a first peak level; and identification means for identifying a control voltage corresponding to a multiplication value of the multiplication means as an optimum control voltage with reference to the reference amplification characteristic. apparatus. 4. A holding means for detachably holding a disk recording medium having tracks formed on its recording surface and marks formed on said tracks at predetermined intervals, said amplifying means being held by said holding means. 4. The signal processing device according to claim 1, which amplifies a mark signal reproduced from a disc recording medium and related to the mark.