WO2003092040A3 - Verfahren zum bearbeiten eines wafers - Google Patents
Verfahren zum bearbeiten eines wafers Download PDFInfo
- Publication number
- WO2003092040A3 WO2003092040A3 PCT/EP2003/004176 EP0304176W WO03092040A3 WO 2003092040 A3 WO2003092040 A3 WO 2003092040A3 EP 0304176 W EP0304176 W EP 0304176W WO 03092040 A3 WO03092040 A3 WO 03092040A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wafer
- processing
- semi
- predetermined pattern
- defects
- Prior art date
Links
- 239000004020 conductor Substances 0.000 abstract 2
- 230000007547 defect Effects 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Dicing (AREA)
- Weting (AREA)
Abstract
Ein Verfahren zum Bearbeiten eines Wafers (100), der Halbleitermaterial aufweist, umfasst zunächst ein mechanisches Abtragen von Halbleitermaterial des Wafers (100) in einem vorbestimmten Muster, wodurch Defekte (116) an dem Wafer (100) entlang des vorbestimmten Musters entstehen. Abschließend werden die Defekte beseitigt, indem Halbleitermaterial entlang einer durch das mechanische Abtragen gebildeten Oberfläche des vorbestimmten Musters abgetragen wird.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10218099 | 2002-04-23 | ||
DE10218099.7 | 2002-04-23 | ||
DE10229499.2 | 2002-07-01 | ||
DE10229499A DE10229499B4 (de) | 2002-04-23 | 2002-07-01 | Verfahren zum Bearbeiten eines Wafers |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003092040A2 WO2003092040A2 (de) | 2003-11-06 |
WO2003092040A3 true WO2003092040A3 (de) | 2004-03-25 |
Family
ID=29271565
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2003/004176 WO2003092040A2 (de) | 2002-04-23 | 2003-04-22 | Verfahren zum bearbeiten eines wafers |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2003092040A2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113224005A (zh) * | 2021-04-08 | 2021-08-06 | 深圳市德明利光电有限公司 | 一种芯片切割道工艺方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6063696A (en) * | 1997-05-07 | 2000-05-16 | Texas Instruments Incorporated | Method of reducing wafer particles after partial saw using a superhard protective coating |
WO2001003180A1 (de) * | 1999-07-01 | 2001-01-11 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. | Verfahren zum vereinzeln eines wafers |
US6294439B1 (en) * | 1997-07-23 | 2001-09-25 | Kabushiki Kaisha Toshiba | Method of dividing a wafer and method of manufacturing a semiconductor device |
-
2003
- 2003-04-22 WO PCT/EP2003/004176 patent/WO2003092040A2/de not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6063696A (en) * | 1997-05-07 | 2000-05-16 | Texas Instruments Incorporated | Method of reducing wafer particles after partial saw using a superhard protective coating |
US6294439B1 (en) * | 1997-07-23 | 2001-09-25 | Kabushiki Kaisha Toshiba | Method of dividing a wafer and method of manufacturing a semiconductor device |
WO2001003180A1 (de) * | 1999-07-01 | 2001-01-11 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. | Verfahren zum vereinzeln eines wafers |
Also Published As
Publication number | Publication date |
---|---|
WO2003092040A2 (de) | 2003-11-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2001078135A3 (en) | Methods for repairing defects on a semiconductor substrate | |
MY133102A (en) | Method for treating substrates for microelectronics and substrates obtained according to said method | |
WO2007019279A3 (en) | Method and composition for polishing a substrate | |
TW200633050A (en) | Manufacturing method for semiconductor chips | |
DE69732872D1 (de) | Schicht zum Abtrennen von Halbleiterscheiben bzw. zum Kontaktverbinden und Verfahren zum Herstellen eines Halbeiterbauelements | |
EP1469509A4 (de) | Verfahren und einrichtung zum verarbeiten eines substrats und vorrichtung zur herstellung eines halbleiterbauelements | |
WO2003044851A3 (en) | Method and apparatus for utilizing integrated metrology data as feed-forward data | |
EP1024965A4 (de) | Verfahren zum entfernen von rückständen von einem halbleitersubstrat | |
WO2006036368A3 (en) | Composition and process for ashless removal of post-etch photoresist and/or bottom anti-reflective material on a substrate | |
TWI349304B (en) | Method for removing material from semiconductor wafer and apparatus for performing the same | |
DE69934271D1 (de) | Verfahren zur Wiedergewinnung eines abgetrennten Wafers und zur Wiedergewinnung verwendeter Siliziumwafer | |
EP1170088A3 (de) | Verfahren und Vorrichtung zum schleifen von Halbleiterscheiben | |
JP2001345294A5 (de) | ||
AU2769699A (en) | Method and apparatus for removing die from a wafer and conveying die to a pickuplocation | |
WO2003038888A3 (en) | Method and apparatus for cascade control using integrated metrology | |
EP1429375A4 (de) | System und verfahren zum durchführen einer halbleiterverarbeitung an einem gerade verarbeiteten substrat | |
TWI367245B (en) | Method for laser marking the inactive surface of a semiconductor silicon die or wafer | |
SG116411A1 (en) | Method and apparatus for cleaning a semiconductor wafer processing system. | |
WO2001057908A3 (en) | A method and apparatus for implanting semiconductor wafer substrates | |
EP1424723A3 (de) | Reinigung von Ausrichtmarken mit einem Ionenstrahl | |
GB2406713B (en) | Surface treating method for substrate | |
EP1316992A3 (de) | Verfahren zur Bearbeitung einer Halbleiterscheibe und laminiertes Substrat das in diesem Verfahren als Stütze für diese Scheibe verwendet wird | |
WO2003092040A3 (de) | Verfahren zum bearbeiten eines wafers | |
WO2004019403A3 (en) | Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom | |
JP4488590B2 (ja) | 被加工物の分割方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WA | Withdrawal of international application | ||
NENP | Non-entry into the national phase |
Ref country code: JP |