WO2003088138A1 - Single-layered multichip module - Google Patents

Single-layered multichip module Download PDF

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Publication number
WO2003088138A1
WO2003088138A1 PCT/DE2003/000813 DE0300813W WO03088138A1 WO 2003088138 A1 WO2003088138 A1 WO 2003088138A1 DE 0300813 W DE0300813 W DE 0300813W WO 03088138 A1 WO03088138 A1 WO 03088138A1
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WIPO (PCT)
Prior art keywords
carrier
metal surface
semiconductor chips
met
electrical conductors
Prior art date
Application number
PCT/DE2003/000813
Other languages
German (de)
French (fr)
Inventor
Martin Gruber
Andreas Gruendl
Thomas Münch
Original Assignee
Infineon Technologies Ag
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Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2003088138A1 publication Critical patent/WO2003088138A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/072—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising a plurality of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
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    • G06K19/07735—Physical layout of the record carrier the record carrier comprising means for protecting against electrostatic discharge
    • G—PHYSICS
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Definitions

  • the object of the present invention is to provide a multichip module with electrical shielding and / or impedance control of the circuit which can be produced cost-effectively.
  • connection conductor 2 can also be attached to the carrier 1, which has a greater thickness than the overall thickness achieved by the electrical conductors, the metal surface and the insulation layers.
  • the multichip module can therefore be inserted into a housing, a card body or the like without the additional thickness of the
  • the insulation layers are independent of the design and design of the actual carrier and can optionally be added subsequently and selectively. That can e.g. B. also happen that after the application of the first insulation layer 4, the metal surface is applied in the form of a metallized film. The actual plastic layer of the film then forms the further insulation layer 5, while the metallization as the metal surface Met is directly connected to the first insulation layer 4.

Abstract

A metal layer (Met) that is separated from the electric conductors (3a, 3b, 3c, 3d) by means of an insulating layer (4) is disposed on the face of the support (1), which lies across from the semiconductor chips (6) and to which said conductors are applied. Said metal layer electrically shields and/or controls the impedance of the integrated circuits with which the semiconductor chips are provided. The metal layer is connected to an electric conductor (3d) of the support, which applies an electrical potential to the metal surface, said electrical potential being used for shielding.

Description

Beschreibungdescription
Einlagiges Multichip-ModulSingle-layer multichip module
Die vorliegende Erfindung betrifft ein einlagiges Multichip- Modul mit einer Abschirmung gegen^ elektromagnetische Felder und einer Impedanzkontrolle der integrierten Schaltungen.The present invention relates to a single-layer multichip module with a shield against ^ electromagnetic fields and an impedance control of the integrated circuits.
Die elektrische Abschirmung, wie z. B. ein ESD-Schutz (Elec- tro-Static Damage) , und die Impedanzkontrolle von Schaltungsanordnungen auf äußeren Schichtlagen elektronischer Baugruppen sind in der Regel nicht so gut beherrschbar wie auf den inneren Schichtlagen eines Baugruppenträgers. Diesem Tatbestand wird beim Entwurf der Schaltungen so gut wie möglic Rechnung getragen. Falls die Baugruppenträger auf einer PCB- Leiterplatte (Printed Circuit Board) aus einem Kunststoffmaterial mit einer Kupfermetallisierung ausgeführt sind, die nur eine oder zwei Schichtlagen umfasst, ist eine ausreichende Impedanzkontrolle der Schaltungen wegen der fehlenden In- nenlagen nicht gewährleistet. Um dennoch eine gute Impedanzkontrolle und Abschirmung zu erreichen, kann eine Leiterplatte mit mindestens vier Lagen verwendet werden, um über eine SchichtStruktur des Trägers mit so genannten Dummy-Innenlagen zu verfügen. Diese aufwendige Lösung ist jedoch zu teuer.The electrical shield, such as. B. ESD protection (Electro-Static Damage), and the impedance control of circuit arrangements on outer layers of electronic assemblies are usually not as easy to control as on the inner layers of a rack. This fact is taken into account as much as possible in the design of the circuits. If the subracks are made of a plastic material with a copper metallization on a PCB (Printed Circuit Board), which only comprises one or two layers, an adequate impedance control of the circuits cannot be guaranteed due to the missing inner layers. In order to achieve good impedance control and shielding nevertheless, a printed circuit board with at least four layers can be used in order to have a layer structure of the carrier with so-called dummy inner layers. However, this complex solution is too expensive.
In der EP 1 102 316 AI ist eine Multi-Chip- IC-Karte mit Bus- Struktur beschrieben, bei der ein Multi-Chip-Modul mit zwei nebeneinander auf einem Träger angeordneten Chips vorhanden ist. Diese Chips werden auf einer Seite eines Trägerbandes, das als Träger vorgesehen ist, angebracht, wobei die Anschlüsse der Chips mit entsprechend vorgesehenen Kontakten auf dem Trägerband verbunden werden. Die Verdrahtung der Anschlüsse zum Zweck einer Parallelschaltung der Chips befindet sich auf der gegenüberliegenden Unterseite des Trägerbandes. Dort sind strukturierte Leiterbahnen aufgebracht. Die JP 11054696 A beschreibt eine Anordnung zweier IC-Chips auf einem für Hochfrequenzanwendungen vorgesehenen mehrlagigen Substrat. Das Substrat umfasst eine keramische Schicht und eine darauf aufgebrachte Schicht niedriger Dielektrizi- tätszahl, zwischen denen eine Verdrahtungsebene vorhanden ist. Auf der .von den IC-Chips abgewandten Seite des Substrates befindet sich eine ganzflächige Erdungselektrode.EP 1 102 316 AI describes a multi-chip IC card with a bus structure, in which a multi-chip module with two chips arranged next to one another on a carrier is present. These chips are attached to one side of a carrier tape which is provided as a carrier, the connections of the chips being connected to correspondingly provided contacts on the carrier tape. The wiring of the connections for the purpose of parallel connection of the chips is located on the opposite underside of the carrier tape. Structured conductor tracks are applied there. JP 11054696 A describes an arrangement of two IC chips on a multi-layer substrate provided for high-frequency applications. The substrate comprises a ceramic layer and a layer of low dielectric constant applied thereon, between which a wiring level is present. On the side of the substrate facing away from the IC chips, there is a full-surface grounding electrode.
Die DE 43 35 822 AI und die DE 44 23 575 AI beschreiben An- Ordnungen von Chips auf einem Träger, durch den hindurch rückseitig aufgebrachte Leiter mittels Bonddrähten mit den Kontaktflächen der Chips verbunden sind.DE 43 35 822 AI and DE 44 23 575 AI describe arrangements of chips on a carrier through which conductors applied on the back are connected to the contact surfaces of the chips by means of bonding wires.
Aufgabe der vorliegenden Erfindung ist es, ein kostengünstig herstellbares Multichip-Modul mit elektrischer Abschirmung und/oder Impedanzkontrolle der Schaltung anzugeben.The object of the present invention is to provide a multichip module with electrical shielding and / or impedance control of the circuit which can be produced cost-effectively.
Diese Aufgabe wird mit dem einlagigen Multichip-Modul mit den Merkmalen des Anspruches 1 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.This object is achieved with the single-layer multichip module with the features of claim 1. Refinements result from the dependent claims.
Bei dem Multichip-Modul ist ein Träger mit einer Lage aus Glasfaser, Epoxidharz oder einem anderen der für PCBs verwendbaren Materialien vorhanden, auf deren einer Seite zwei oder mehr Halbleiterchips angebracht sind und auf deren gegenüberliegenden Seite eine Struktur elektrischer Leiter für die Verdrahtung dieser Halbleiterchips vorhanden ist. Auf der von den Halbleiterchips abgewandten Seite des Trägers, auf der die elektrischen Leiter angebracht sind, ist eine von den Leitern durch eine Isolationsschicht getrennte Metallfläche angeordnet, die zur elektrischen Abschirmung und/oder zur Impedanzkontrolle der in den Halbleiterchips vorhandenen integrierten Schaltungen vorgesehen ist. Diese Metallfläche ist mit einem elektrischen Leiter des Trägers verbunden, der da- für vorgesehen ist, ein für die Abschirmung vorgesehenes elektrisches Potential an die Metallfläche anzulegen.. Die von der Isolationsschicht abgewandte Oberfläche der Metallfläche kann mit einer weiteren Isolationsschicht bedeckt sein. Insbesondere können die Metallfläche und diese weitere Isolationsschicht aus einer metallisierten Folie gebildet sein, die mit der Metallisierung auf der ersten Isolationsschicht angebracht ist.The multichip module has a carrier with a layer of glass fiber, epoxy resin or another of the materials that can be used for PCBs, on one side of which two or more semiconductor chips are attached and on the opposite side there is a structure of electrical conductors for the wiring of these semiconductor chips is. On the side of the carrier facing away from the semiconductor chips, on which the electrical conductors are attached, there is a metal surface separated from the conductors by an insulation layer, which is provided for electrical shielding and / or for impedance control of the integrated circuits present in the semiconductor chips. This metal surface is connected to an electrical conductor of the carrier, which is provided for applying an electrical potential provided for the shielding to the metal surface. The surface of the metal surface facing away from the insulation layer can be covered with another layer of insulation. In particular, the metal surface and this further insulation layer can be formed from a metallized film which is attached to the first insulation layer with the metallization.
Es folgt eine genauere Beschreibung eines typischen Beispiels des Multichip-Moduls anhand der beigefügten Figur, die ein Ausführungsbeispiel im Querschnitt zeigt .The following is a more detailed description of a typical example of the multichip module with reference to the attached figure, which shows an exemplary embodiment in cross section.
In der Figur ist ein Träger 1 im Querschnitt dargestellt, der aus einem der üblichen für PCB-Leiterplatten geeigneten Materialien ausgebildet sein kann. Der Träger ist hier mit einer Mehrzahl von Kontaktlöchern 10 (vias) versehen. Mindestens zwei Halbleiterchips 6 sind auf einer Oberseite des Trägers 1 angebracht . Auf der von den Halbleiterchips 6 abgewandten Oberseite des Trägers 1 ist eine Struktur elektrischer Leiter 3a, 3b, 3c, 3d angebracht, von denen ein Teil über elektrisch leitende Verbindungen 7, 7b, 7c mit Anschlusskontakten der integrierten Schaltungen der Chips verbunden ist. Diese elektrisch leitenden Verbindungen sind in dem dargestellten Beispiel so genannte Bonddrähte. Ein Teil der Bonddrähte 7, 7c verbindet einen Anschlusskontakt des Chips mit einem Leiter des Trägers, ein anderer Teil der Bonddrähte 7b verbindet die Anschlusskontakte der Chips untereinander.In the figure, a carrier 1 is shown in cross section, which can be formed from one of the usual materials suitable for PCB circuit boards. The carrier is here provided with a plurality of contact holes 10 (vias). At least two semiconductor chips 6 are attached to an upper side of the carrier 1. On the upper side of the carrier 1 facing away from the semiconductor chips 6, a structure of electrical conductors 3a, 3b, 3c, 3d is attached, a part of which is connected to terminal contacts of the integrated circuits of the chips via electrically conductive connections 7, 7b, 7c. In the example shown, these electrically conductive connections are so-called bond wires. A part of the bonding wires 7, 7c connects a connection contact of the chip to a conductor of the carrier, another part of the bonding wires 7b connects the connection contacts of the chips to one another.
Die Halbleiterchips 6 und die Bonddrähte sind in eine schützende Vergussmasse 9a eingespritzt. In dem dargestellten Beispiel ist noch ein passiver Schaltungsteil 8 vorhanden,- der außer elektrisch leitenden Verbindungen passive Komponenten wie z. B. Widerstände, Kondensatoren und Induktivitäten umfassen kann. Auch dieser passive Schaltungsteil 8 ist hier mit einem Anteil der Vergussmasse 9b geschützt.The semiconductor chips 6 and the bond wires are injected into a protective casting compound 9a. In the example shown, a passive circuit part 8 is also present, which, in addition to electrically conductive connections, has passive components such as B. may include resistors, capacitors and inductors. This passive circuit part 8 is also protected here with a portion of the sealing compound 9b.
Auf der von den Halbleiterchips 6 abgewandten' Seite der elektrischen Leiter 3a, 3b, 3c, 3d befindet sich eine Metallfläche Met, die von den elektrischen Leitern durch eine Isolati- onsschicht 4 elektrisch isoliert ist. Diese Metallfläche Met ist mit einem der Leiter 3d kontaktiert, so dass über diesen Leiter ein vorgesehenes abschirmendes Potential an die- Metallfläche angelegt werden kann. In dem dargestellten Ausfüh- rungsbeispiel befindet sich auf der von der Isolationsschicht 4 abgewandten Seite der Metallfläche Met eine weitere Isolationsschicht 5. Auf diese Weise ist die' Metallschicht allseits elektrisch isoliert.On the side remote from the semiconductor chip 6 'side of the electrical conductors 3a, 3b, 3c, 3d is a metal surface Met, which from the electrical conductors by a Isolati- onsschicht 4 is electrically insulated. This metal surface Met is contacted with one of the conductors 3d, so that an intended shielding potential can be applied to the metal surface via this conductor. In the exemplary embodiment shown, there is a further insulation layer 5 on the side of the metal surface Met facing away from the insulation layer 4. In this way, the metal layer is electrically insulated on all sides.
Es kann auf dem Träger 1 noch ein Anschlussleiter 2 angebracht sein, der eine größere Dicke aufweist als die durch die elektrischen Leiter, die Metallfläche und die Isolationsschichten insgesamt erreichte Dicke. Das Multichip-Modul kann daher in ein Gehäuse, einen Kartenkörper oder dergleichen eingesetzt werden, ohne dass sich die zusätzliche Dicke derA connection conductor 2 can also be attached to the carrier 1, which has a greater thickness than the overall thickness achieved by the electrical conductors, the metal surface and the insulation layers. The multichip module can therefore be inserted into a housing, a card body or the like without the additional thickness of the
Metallfläche und der Isolationsschichten nachteilig bemerkbar macht. Die Isolationsschichten sind unabhängig vom Design und der Ausführung des eigentlichen Trägers und können wahlweise nachträglich und selektiv angebracht werden. Das kann z. B. auch dadurch geschehen, dass nach dem Aufbringen der ersten Isolationsschicht 4 die Metallfläche in Form einer metallisierten Folie angebracht wird. Die eigentliche Kunststoffläge der Folie bildet dann die weitere Isolationsschicht 5, während die Metallisierung als Metallfläche Met unmittelbar mit der ersten Isolationsschicht 4 verbunden ist. Metal surface and the insulation layers disadvantageously noticeable. The insulation layers are independent of the design and design of the actual carrier and can optionally be added subsequently and selectively. That can e.g. B. also happen that after the application of the first insulation layer 4, the metal surface is applied in the form of a metallized film. The actual plastic layer of the film then forms the further insulation layer 5, while the metallization as the metal surface Met is directly connected to the first insulation layer 4.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
1 Träger1 carrier
2 Anschlussleiter 3a elektrischer Leiter 3b elektrischer Leiter 3c elektrischer Leiter 3d elektrischer Leiter 4 Isolationsschicht 5 weitere Isolationsschicht2 connecting conductors 3a electrical conductors 3b electrical conductors 3c electrical conductors 3d electrical conductors 4 insulation layer 5 further insulation layer
6 Halbleiterchip6 semiconductor chip
7 elektrisch leitende Verbindung 7b elektrisch leitende Verbindung 7c elektrisch leitende Verbindung 8 passiver Schaltungsteil 9a Vergussmasse 9b Vergussmasse 10 Kontaktloch 7 electrically conductive connection 7b electrically conductive connection 7c electrically conductive connection 8 passive circuit part 9a casting compound 9b casting compound 10 contact hole

Claims

Patentansprüche claims
1. Einlagiges Multichip-Modul mit1. Single-layer multichip module with
- einem Träger (1) , auf dem zwei oder mehr Halbleiterchips (6) angebracht sind,- a carrier (1) on which two or more semiconductor chips (6) are attached,
- einer auf dem Träger (1) angebrachten Struktur elektrischer Leiter (3a, 3b, 3c, 3d) und- A structure on the carrier (1) attached electrical conductors (3a, 3b, 3c, 3d) and
- leitenden Verbindungen (7, 7b, 7c) zwischen Anschlüssen der Halbleiterchips (6) und den elektrischen Leitern (3a, 3b, 3c, 3d) des Trägers, wobei die Halbleiterchips (6) auf derselben Seite des Trägers (1) angeordnet sind und die Struktur elektrischer Leiter (3a, 3b, 3c, 3d) auf der gegenüberliegenden Seite des Trägers angeordnet ist, d a d u r c h g e k e n n z e i c h n e t , dass auf der von den Halbleiterchips (6) abgewandten Seite des Trägers (1) eine von den elektrischen Leitern (3a, 3b, 3c, 3d) durch eine Isolationsschicht (4) getrennte Metallfläche (Met) angeordnet ist und diese Metallfläche (Met) mit einem elektrischen Leiter (3d) des Trägers (1) verbunden ist, der zum Anlegen eines abschirmenden elektrischen Potentials an die Metallfläche (Met) vorgesehen ist.- Conductive connections (7, 7b, 7c) between connections of the semiconductor chips (6) and the electrical conductors (3a, 3b, 3c, 3d) of the carrier, the semiconductor chips (6) being arranged on the same side of the carrier (1) and the structure of electrical conductors (3a, 3b, 3c, 3d) is arranged on the opposite side of the carrier, characterized in that on the side of the carrier (1) facing away from the semiconductor chips (6) one of the electrical conductors (3a, 3b, 3c, 3d) is arranged by an insulation layer (4) separated metal surface (Met) and this metal surface (Met) is connected to an electrical conductor (3d) of the carrier (1) which is used to apply a shielding electrical potential to the metal surface (Met ) is provided.
2. Modul nach Anspruch 1, bei dem auf der von dem Träger (1) abgewandten Seite der Metallfläche (Met) eine weitere Isolationsschicht (5) vorhanden ist.2. Module according to claim 1, in which a further insulation layer (5) is present on the side of the metal surface (Met) facing away from the carrier (1).
3. Modul nach Anspruch 2 , bei dem die Metallfläche (Met) und die weitere Isolationsschicht (5) eine metallisierte Folie sind. 3. Module according to claim 2, wherein the metal surface (Met) and the further insulation layer (5) are a metallized film.
PCT/DE2003/000813 2002-04-16 2003-03-13 Single-layered multichip module WO2003088138A1 (en)

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