DE4335822A1 - Electronic module with IC - Google Patents
Electronic module with ICInfo
- Publication number
- DE4335822A1 DE4335822A1 DE4335822A DE4335822A DE4335822A1 DE 4335822 A1 DE4335822 A1 DE 4335822A1 DE 4335822 A DE4335822 A DE 4335822A DE 4335822 A DE4335822 A DE 4335822A DE 4335822 A1 DE4335822 A1 DE 4335822A1
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- substrate
- connections
- bonding
- electronics module
- elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
Abstract
Description
Die Erfindung betrifft eine Elektronikbaugruppe mit einem IC-Element gemäß dem Oberbegriff des Anspruchs 1.The invention relates to an electronic assembly with a IC element according to the preamble of claim 1.
Elektronikbaugruppen mit IC′s bzw. integrierten Schaltkreisen finden vielfältig Anwendung. Wenn die Baugröße der Elektronikgruppe keine große Rolle spielt, werden üblicherweise die fertig in Gehäuse, z. B. DIL- oder DIP- Gehäuse, verpackten IC′s auf die Platine aufgelötet bzw. in einen speziellen IC-Sockel eingesetzt. Bei Anwendungen, bei denen die Baugröße sehr kritisch ist, z. B. bei sogenannten Chip-Karten bzw. elektronische Scheckkarten, Kleinstcompu tern, Handtelefonen etc., ist es jedoch notwendig, das IC- Element bzw. den Halbleiterkristall unmittelbar in die "Schaltungsplatine" zu integrieren. Die "Platine" ist hier bei häufig nicht eine herkömmliche Platine sondern z. B. eine flexible Polyimidfolie oder ein anderes Kunststoffsub strat. Das IC-Element wird hierbei auf das Substrat auf ge klebt und mittels Drahtbondverbindungen wird das IC-Element elektrisch mit Leiterbahnanschlüssen auf dem Substrat ver bunden.Electronic assemblies with IC's or integrated Circuits are used in many ways. If the size the electronics group does not play a major role usually the finished in housing, e.g. B. DIL or DIP Housing, packaged IC's soldered onto the board or in used a special IC socket. In applications, in which the size is very critical, e.g. B. in so-called Chip cards or electronic check cards, microcomp ters, hand-held telephones etc., it is necessary to Element or the semiconductor crystal directly in the Integrate "circuit board". The "circuit board" is here often not a conventional circuit board but e.g. B. a flexible polyimide film or another plastic sub strat. The IC element is ge on the substrate sticks and by means of wire bond connections the IC element electrically with conductor connections on the substrate bound.
Da auf IC-Elementen immer mehr Funktionen integriert werden, werden diese Elemente auch immer größer und häufig sind die Bondanschlüsse bzw. Bondflächen nicht mehr oder nicht mehr nur am Rande des IC-Elements positioniert. Damit werden je doch auch die Entfernungen zwischen den Bondanschlüssen auf dem IC-Element und den Leiterbahnanschlüssen auf dem Sub strat bzw. der Platine immer größer. Drahtbondverbindungen sind bogenförmig und die Scheitelhöhe des Bogens ist um so größer je größer die mit der Drahtbondverbindung zu überwin dende Distanz ist. Bei großen IC-Elementen bzw. großen Halb leiterkristallen erhöht sich damit die Bauhöhe. Darüber hinaus verringert sich die Stabilität und Zuverlässigkeit von Drahtbondverbindungen, wenn die Bonddistanz größer wird.As more and more functions are integrated on IC elements, these elements are getting bigger and more common Bond connections or bond areas no longer or no longer positioned only on the edge of the IC element. With that, ever but also the distances between the bond connections the IC element and the trace connections on the sub strat or the board always bigger. Wire bond connections are arched and the vertex height of the arch is all the more greater the greater that to overcome with the wire bond distance is. With large IC elements or large half conductor crystals increases the overall height. About it in addition, the stability and reliability decrease wire bond connections when the bond distance increases.
Es ist daher Aufgabe der vorliegenden Erfindung eine IC- Elektronikbaugruppe gemäß dem Oberbegriff des Anspruch 1 der art weiterzubilden, daß auch großflächigere IC-Elemente mit geringer Bauhöhe integriert werden können.It is therefore an object of the present invention to provide an IC Electronic assembly according to the preamble of claim 1 Art to further develop that even larger IC elements with low height can be integrated.
Die Lösung dieser Aufgabe erfolgt durch die Merkmale des An spruch 1.This task is solved by the characteristics of the contractor saying 1.
Dadurch, daß die Bonddrähte bzw. Drahtbondverbindungen durch einen Durchbruch in dem flächigen Substrat geführt werden, verkürzt sich der durch die Drahtbondverbindungen zu über windende Abstand zwischen den Bondflächen auf dem IC-Element und den Leiterbahnanschlüssen auf dem Substrat und folglich auch die Bauhöhe. Durch das Bonden durch den Durchbruch kann die gesamte Dicke des Substrats zur Unterbringung der Draht bondverbindung genutzt werden.The fact that the bond wires or wire bond connections through make a breakthrough in the flat substrate, that is shortened by the wire bond connections winding distance between the bond areas on the IC element and the conductor connections on the substrate and consequently also the height. By bonding through the breakthrough the entire thickness of the substrate to accommodate the wire bond connection can be used.
Je nach Layout der Platine bzw. des Substrats und in Abhän gigkeit von der Lage der Bondflächen auf dem IC-Element kön nen auch mehrere Durchbrüche vorteilhaft sein.Depending on the layout of the circuit board or the substrate and depending depending on the position of the bond pads on the IC element NEN several breakthroughs can be advantageous.
Durch das Vorsehen einer Vertiefung in der das IC-Element eingeklebt ist, können die Drahtbondverbindungen gegebenen falls vollständig im Inneren des Substrats eingebettet wer den.By providing a recess in the IC element is glued, the wire bond connections can be given if completely embedded inside the substrate the.
Die Größe des bzw. der Durchbrüche ist so gewählt, daß noch Substratfläche verbleibt auf der das bzw. die IC-Elemente gefestigt werden können.The size of the or breakthroughs is chosen so that still The substrate surface remains on the one or more IC elements can be consolidated.
Weitere Einzelheiten, Merkmale und Vorteile der Erfindung ergeben sich aus der nachfolgenden Beschreibung in bevorzug ten Ausführungsformen anhand der Zeichnung.Further details, features and advantages of the invention are preferred from the following description Embodiments based on the drawing.
Es zeigt:It shows:
Fig. 1a eine Aufsicht auf dem IC-Element, bei dem die Bond-Anschlüsse am Rand des Elements angeordnet sind, FIG. 1a is a plan view of the IC element in which the bond connections are arranged at the edge of the element,
Fig. 1b ein IC-Element, bei dem die Bond-Anschlüsse mit tig in Längsrichtung des Elements angeordnet sind, FIG. 1b, an IC element in which the bonding terminals are arranged with tig in the longitudinal direction of the element,
Fig. 1c ein IC-Element, bei dem die Bond-Anschlüsse mit tig in Richtung der Breite des Elements angeord net sind, FIG. 1c, an IC element in which the bonding terminals to the element are angeord net tig in the width direction,
Fig. 2 zeigt in verschiedenen Ansichten und Schnittdar stellungen eine erste Ausführungsform der erfin dungsgemäßen IC-Elektronik-Baugruppe, Fig. 2 shows in different views and positions Schnittdar a first embodiment of to the invention OF INVENTION IC electronics assembly,
Fig. 2a zeigt eine Aufsicht-auf die Elektronik-Baugruppe bzw. auf zweite Hauptfläche des Substrats, Fig. 2a shows a top-to the electronics module or on second major surface of the substrate,
Fig. 2b zeigt einen Schnitt durch die Darstellung gemäß Fig. 2 in Richtung der Linie B-B in Fig. 2a, FIG. 2b shows a section through the representation according to Fig. 2 in the direction of line BB in Fig. 2a,
Fig. 2c zeigt einen Schnitt entlang der Linie C-C in Fig. 2a, Fig. 2c shows a section along the line CC in Fig. 2a,
Fig. 2d zeigt einen Schnitt entlang der Linie D-D in Fig. 2a, Fig. 2d shows a section along the line DD in Fig. 2a,
Fig. 2e zeigt einen Schnitt entlang der Linie E-E in Fig. 2a, Fig. 2e shows a section along the line EE in Fig. 2a,
Fig. 2f zeigt eine Fig. 2a entsprechende Ansicht und der ersten Hauptfläche auf der die IC-Elemente ange ordnet sind, Fig. 2f shows a Fig. 2a and view corresponding to the first main surface on which the IC elements are arranged,
Fig. 3 zeigt eine den Fig. 2b, 2c, 2d und 2e entspre chende Schnittdarstellung einer weiteren Ausfüh rungsform der Erfindung. Fig. 3 shows a Fig. 2b, 2c, 2d and 2e corre sponding sectional view of another embodiment of the invention.
Die Fig. 1a, 1b und 1c zeigen unterschiedliche Varianten der Anordnung von Bond-Anschlüssen bzw. Bondflächen auf IC- Elementen bzw. IC-Halbleiterkristallen. In einem in Fig. Ia dargestellten IC-Element 2 sind Bondflächen 8 am Rand des IC-Elements 2 in Längsrichtung angeordnet. Diese Art der Po sitionierung der Bondflächen 8 auf dem IC-Element ist häufig bei "kleinen" bzw. "kleinflächigeren" IC-Elementen vorzufin den. Bei einem in Fig. 1b gezeigten IC-Element 4 sind die Bondflächen 8 mittig in Längsrichtung des IC-Elements 4 an geordnet. In einem in Fig. 1c gezeigten IC-Element 6 sind die Bondflächen 8 mittig in Richtung der Breite des IC-Ele ments 6 bzw. in Richtung der kürzeren Seite des IC-Elements 6 angeordnet. Die Positionierung der Bondflächen 8 gemäß den Fig. 1b und 1c ist häufig bei großflächigen IC-Elementen zu finden und insbesondere beispielsweise bei 16-MB-Speicher- IC-Elementen. FIGS. 1a, 1b and 1c show different variants of the arrangement of bonding terminals or bond pads on IC elements or IC semiconductor crystals. In an IC element 2 shown in FIG. 1 a , bonding areas 8 are arranged on the edge of the IC element 2 in the longitudinal direction. This type of po sitioning of the bonding surfaces 8 on the IC element is often vorzufin the "small" or "small-area" IC elements. In an IC element 4 shown in FIG. 1b, the bonding surfaces 8 are arranged centrally in the longitudinal direction of the IC element 4 . In an IC element 6 shown in FIG. 1c, the bonding surfaces 8 are arranged centrally in the direction of the width of the IC element 6 or in the direction of the shorter side of the IC element 6 . The positioning of the bond areas 8 according to FIGS . 1b and 1c can often be found with large-area IC elements and in particular, for example, with 16 MB memory IC elements.
Fig. 2 zeigt eine erste Ausführungsform der erfindungsge mäßen IC-Elektronikbaugruppe. Die IC-Elemente 2, 4 und 8 ge mäß Fig. 1 mit entsprechender Positionierung der Bondflächen 8 sind auf einer ersten Hauptfläche 10 eines flächigen Sub strats 12 in Vertiefungen 14, 15 bzw. 16 eingeklebt. Die Vertiefungen 14, 15 und 16 sind vorzugsweise in das Substrat 12 eingefräst. Die Tiefe Tv der Vertiefungen 14, 15 und 16 ist in der beispielhaften Ausführungsform gemäß Fig. 2 so gewählt, daß die darin befindlichen IC-Elemente 2, 4 und 6 nicht aus der Hauptfläche 10 des Substrats 12 herausragen. Fig. 2 shows a first embodiment of the IC electronic assembly according to the invention. The IC elements 2 , 4 and 8 ge according to FIG. 1 with appropriate positioning of the bonding surfaces 8 are glued to a first main surface 10 of a flat substrate 12 in recesses 14 , 15 and 16 respectively. The depressions 14 , 15 and 16 are preferably milled into the substrate 12 . The depth T v of the depressions 14 , 15 and 16 is selected in the exemplary embodiment according to FIG. 2 such that the IC elements 2 , 4 and 6 located therein do not protrude from the main surface 10 of the substrate 12 .
Aus Stabilitätsgründen, in Abhängigkeit von der Substratdicke etc. kann das IC-Element auch aus der Vertiefung herausragen. In den Vertiefungen 14, 15 und 16 sind Durchbrüche 18, 19, 20 und 21 vorgesehen. Die Längskanten des in die Vertiefung 14 eingeklebten IC- Elements 2 ragen in die Durchbrüche 18 und 19 hinein, so daß die Bondflächen 8 von der zweiten Hauptfläche 11 des flächigen Substrats 12 her zugänglich sind. Die in den Vertiefungen 15 und 16 sitzenden IC-Elemente 4 bzw. 6 über decken die Durchbrüche 20 und 21 vollständig und sind dabei derart positioniert, daß die Bondflächen 8 ebenfalls von der zweiten Hauptfläche 11 her durch die Durchbrüche 20 bzw. 21 zugänglich sind. Die Größenverhältnisse zwischen IC-Element 4 bzw. 6 und den Durchbrüchen 20 bzw. 21 können natürlich auch so sein, daß die Durchbrüche nicht vollständig von den IC-Elementen überdeckt werden. Wie aus Fig. 2f zu ersehen ist, erstrecken sich zwischen den Bondflächen 8 der IC- Elemente 2, 4 und 6 und auf dem flächigen Substrat 12 vorgesehenen Leiterbahnanschlüssen 22 Drahtbondverbindungen 24. Da die Drahtbondverbindungen 24 durch die Durchbrüche 18, 19, 20 bzw. 21 geführt werden, bedingen die Drahtbondverbindungen 24 keine zusätzliche bzw. nur eine geringe zusätzliche Bauhöhe.For reasons of stability, depending on the substrate thickness, etc., the IC element can also protrude from the recess. Openings 18 , 19 , 20 and 21 are provided in the depressions 14 , 15 and 16 . The longitudinal edges of the IC element 2 glued into the recess 14 protrude into the openings 18 and 19 , so that the bonding surfaces 8 are accessible from the second main surface 11 of the flat substrate 12 . The IC elements 4 and 6 seated in the recesses 15 and 16 cover the openings 20 and 21 completely and are positioned in such a way that the bonding surfaces 8 are also accessible from the second main surface 11 through the openings 20 and 21 . The proportions between the IC element 4 or 6 and the openings 20 or 21 can of course also be such that the openings are not completely covered by the IC elements. As can be seen from Fig. 2f of the IC elements 2, 4 and 6 and provided on the flat substrate 12 track terminals extend between the bond pads 22 8 wire bond connections 24. Since the wire bond connections 24 are guided through the openings 18 , 19 , 20 and 21 , the wire bond connections 24 require no additional or only a small additional height.
In Fig. 3 ist eine zweite Ausführungsform der Erfindung im Schnitt dargestellt. Die Ausführungsform gemäß Fig. 3 weist ein Substrat bzw. eine Multi-Layer-Platine 30 auf. In einer auf einer ersten Hauptfläche 32 angebrachten Vertiefung 34 mit einer Bodenfläche 35 ist ein IC-Element 36 eingeklebt. Die Bodenfläche 35 durchsetzend ist ein Durchbruch 38 vorge sehen, der sich bis zur zweiten Hauptfläche 33 des flächigen Substrats 30 bzw. der Multi-Layer-Platine 30 erstreckt. Der Durchbruch 38 weist einen stufenförmigen Querschnitt auf, so daß durch Stufenflächen 40, 41 und 42 unterschiedliche Schichten der Multi-Layer-Platine zugänglich sind. Die Bond flächen auf dem IC-Element 36 (in Fig. 3 nicht zu sehen) sind entsprechend den IC-Elementen 4 und 6 aus der vorste hend beschriebenen Ausführungsform mittig angeordnet. Bond drahtverbindungen 44 verbinden die Bondflächen auf dem IC- Element 36 mit nicht näher dargestellten Leiterbahnanschlüs sen auf den Stufenflächen 42, 40 bzw. 41. In der Ausfüh rungsform gemäß Fig. 3 sind die Stufenflächen 40 und 41 in einer Ebene gezeigt, d. h. sie bestehen aus einer zusammen hängenden Fläche. Die Stufenfläche 41 kann auch auf einer anderen Ebene liegen, so daß dann alle drei Stufenflächen 42, 40 und 41 jeweils unterschiedliche Schichten der Multi layerplatine freigeben und die Drahtbondverbindungen 44 folglich Leiterbahnanschlüsse in diesen unterschiedlichen Schichten kontaktieren.In Fig. 3, a second embodiment of the invention is shown in section. The embodiment according to FIG. 3 has a substrate or a multi-layer circuit board 30 . An IC element 36 is glued into a recess 34 with a bottom surface 35 on a first main surface 32 . Passing through the bottom surface 35 is an opening 38 which extends to the second main surface 33 of the flat substrate 30 or the multi-layer circuit board 30 . The opening 38 has a step-shaped cross section, so that different layers of the multi-layer board are accessible through step surfaces 40 , 41 and 42 . The bond areas on the IC element 36 (not shown in FIG. 3) are arranged in the center corresponding to the IC elements 4 and 6 from the embodiment described above. Bond wire connections 44 connect the bond areas on the IC element 36 to conductor track connections (not shown) on the step areas 42 , 40 and 41 . In the approximate shape exporting according to Fig. 3, the step surfaces 40 and 41 are shown in a plane, ie they consist of a contiguous surface. The step surface 41 can also be on a different level, so that then all three step surfaces 42 , 40 and 41 each release different layers of the multi-layer board and the wire bond connections 44 consequently contact conductor connections in these different layers.
Die Größe der Durchbrüche 18, 19, 20, 21 und 38 bzw. genauer deren Querschnittsfläche wird lediglich so groß gewählt, daß die Drahtbondverbindungen ohne Schwierigkeiten hergestellt werden können. In jedem Fall muß gewährleistet sein, daß eine genügend große Substratfläche verbleibt auf der das je weilige IC-Element befestigt werden kann. In der Regel wird daher die Fläche der Durchbrüche nur nur einen Bruchteil der Fläche der IC-Elemente umfassen.The size of the openings 18 , 19 , 20 , 21 and 38 or, more precisely, their cross-sectional area is selected only so large that the wire bond connections can be made without difficulty. In any case, it must be ensured that a sufficiently large substrate area remains on which the respective IC element can be attached. As a rule, the area of the openings will therefore only comprise a fraction of the area of the IC elements.
BezugszeichenlisteReference list
2, 4,
6 IC-Elemente
8 Bondflächen
10 erste Hauptfläche des Substrats 12
11 zweite Hauptfläche des Substrats 12
12 Substrat
14, 15,
16 Vertiefungen im Substrat 12
18, 19,
20, 21 Durchbrüche im Substrat 12
22 Leiterbahnanschlüsse
24 Bonddrahtverbindungen
30 Multilayer-Platine
32 erste Hauptfläche von 30
33 zweite Hauptfläche von 30
34 Vertiefung in 30
35 Bodenfläche in 34
36 IC-Element
38 Durchbruch in 30
40, 41′
42 Stufenflächen in 34
44 Bonddrahtverbindungen 2 , 4 ,
6 IC elements
8 bond areas
10 first main surface of the substrate 12
11 second main surface of the substrate 12
12 substrate
14 , 15 ,
16 wells in the substrate 12
18 , 19 ,
20 , 21 openings in the substrate 12
22 trace connections
24 bond wire connections
30 multilayer board
32 first major area of 30
33 second main area of 30
34 deepening in 30
35 floor space in 34
36 IC element
38 breakthrough in 30
40 , 41 ′
42 step surfaces in 34
44 bond wire connections
Claims (8)
einem flächigen Substrat (12; 30),
einem IC-Element (2, 4, 6; 36) mit Bondflächen (8), das auf bzw. in dem Substrat (12; 30) angeordnet und fest mit dem Substrat verbunden ist, und Bonddrahtverbindungen (24; 44) zwischen den
Bondflächen (8) auf dem IC-Element (2, 4, 6; 36) und Leiterbahnanschlüssen (22) des Substrats (12; 30), dadurch gekennzeichnet,
daß das flächige Substrat (12; 30) einen Durchbruch (18, 19, 20, 21; 38) aufweist,
daß das IC-Element (2, 4, 6; 36) derart auf dem Substrat (12; 30) befestigt ist, daß die Bondflächen (8) des IC-Elements dem Substrat zugewandt sind und unter bzw. über dem Durchbruch zu liegen kommen,
daß sich wenigstens ein Teil der Bonddrahtverbin dungen (24) zwischen den Bondflächen auf dem IC-Element und den Leiterbahnanschlüssen (22) durch den Durchbruch (18, 19, 20, 21; 38) erstrecken.1. IC electronics module with
a flat substrate ( 12 ; 30 ),
an IC element ( 2 , 4 , 6 ; 36 ) with bonding areas ( 8 ) which is arranged on or in the substrate ( 12 ; 30 ) and is fixedly connected to the substrate, and bonding wire connections ( 24 ; 44 ) between the
Bonding areas ( 8 ) on the IC element ( 2 , 4 , 6 ; 36 ) and interconnect connections ( 22 ) of the substrate ( 12 ; 30 ), characterized in that
that the flat substrate ( 12 ; 30 ) has an opening ( 18 , 19 , 20 , 21 ; 38 ),
that the IC element ( 2 , 4 , 6 ; 36 ) is fastened to the substrate ( 12 ; 30 ) such that the bonding surfaces ( 8 ) of the IC element face the substrate and come to lie below or above the opening ,
that at least a portion of the bond wire connections ( 24 ) between the bond areas on the IC element and the conductor connections ( 22 ) through the opening ( 18 , 19 , 20 , 21 ; 38 ) extend.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4335822A DE4335822A1 (en) | 1993-10-20 | 1993-10-20 | Electronic module with IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4335822A DE4335822A1 (en) | 1993-10-20 | 1993-10-20 | Electronic module with IC |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE4335822A1 true DE4335822A1 (en) | 1995-04-27 |
Family
ID=6500613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE4335822A Withdrawn DE4335822A1 (en) | 1993-10-20 | 1993-10-20 | Electronic module with IC |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE4335822A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10216841A1 (en) * | 2002-04-16 | 2003-11-13 | Infineon Technologies Ag | Single-layer multichip module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3911711A1 (en) * | 1989-04-10 | 1990-10-11 | Ibm | MODULE STRUCTURE WITH INTEGRATED SEMICONDUCTOR CHIP AND CHIP CARRIER |
| DE9210198U1 (en) * | 1992-07-30 | 1992-10-15 | Meyerhoff, Dieter, 4010 Hilden | Chip module |
-
1993
- 1993-10-20 DE DE4335822A patent/DE4335822A1/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3911711A1 (en) * | 1989-04-10 | 1990-10-11 | Ibm | MODULE STRUCTURE WITH INTEGRATED SEMICONDUCTOR CHIP AND CHIP CARRIER |
| DE9210198U1 (en) * | 1992-07-30 | 1992-10-15 | Meyerhoff, Dieter, 4010 Hilden | Chip module |
Non-Patent Citations (3)
| Title |
|---|
| 3- 12957 A., E-1050, March 27,1991,Vol.15,No.125 * |
| 61- 59860 A., E- 425, Aug. 5,1986,Vol.10,No.224 * |
| JP Patents Abstracts of Japan: 3-201472 A., E-1138, Nov. 26,1991,Vol.15,No.465 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10216841A1 (en) * | 2002-04-16 | 2003-11-13 | Infineon Technologies Ag | Single-layer multichip module |
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| Date | Code | Title | Description |
|---|---|---|---|
| OM8 | Search report available as to paragraph 43 lit. 1 sentence 1 patent law | ||
| 8141 | Disposal/no request for examination |