DE9210198U1 - Chip module - Google Patents

Chip module

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Publication number
DE9210198U1
DE9210198U1 DE9210198U DE9210198U DE9210198U1 DE 9210198 U1 DE9210198 U1 DE 9210198U1 DE 9210198 U DE9210198 U DE 9210198U DE 9210198 U DE9210198 U DE 9210198U DE 9210198 U1 DE9210198 U1 DE 9210198U1
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Germany
Prior art keywords
chip
circuit board
chip module
module according
innovation
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Expired - Lifetime
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DE9210198U
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German (de)
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MEYERHOFF DIETER 4010 HILDEN DE
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MEYERHOFF DIETER 4010 HILDEN DE
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Priority to DE9210198U priority Critical patent/DE9210198U1/en
Publication of DE9210198U1 publication Critical patent/DE9210198U1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

Chip-Modul
15Chip module
15

Die Neuerung bezieht sich auf ein Chip-Modul, bei dem mindestens ein Chip, vorzugsweise ein Speicher oder ein Prozessor, auf einer Leiterplatte angeordnet ist.The innovation relates to a chip module in which at least one chip, preferably a memory or a processor, is arranged on a circuit board.

Nach dem Stand der Technik sind verschiedene Bauformen bekannt, Halbleiterbauelemente auf Leiterplatten oder in speziellen Gehäuseformen anzuordnen. Bei der Anordnung der Chips auf Leiterplatten ist es üblich, daß an den Seitenrändern der Chips Bondinseln angebracht sind, an denen Bonddrähte zur Herstellung der elektrischen Verbindung mit den Leiterbahnen der Leiterplatte angeschlossen werden.According to the state of the art, various designs are known for arranging semiconductor components on circuit boards or in special housing shapes. When arranging the chips on circuit boards it is usual for bonding islands to be attached to the side edges of the chips, to which bonding wires are connected in order to establish the electrical connection with the conductor tracks of the circuit board.

Den bekannten Bauformen haftet der Nachteil an, daß bei Verwendung von Chips mit Bondinseln außerhalb des Randes beim Bondvorgang ein Kantenschluß anThe known designs have the disadvantage that when using chips with bonding islands outside the edge, an edge connection to

den Rändern des Chips auftreten kann, was zur Funktionsuntüchtigkeit des Moduls führt.the edges of the chip, causing the module to become inoperable.

Der Neuerung liegt deshalb die Aufgabe zugrunde, ein Chip-Modul der eingangs genannten Art anzugeben, das weitgehend einen Kantenschluß am Chip vermeidet.The innovation is therefore based on the task of specifying a chip module of the type mentioned above, which largely avoids edge contact on the chip.

Neuerungsgemäß gelingt die Lösung der Aufgabe dadurch , daß sich auf dem Chip außerhalb des Randbereiches Bondinseln (sogenannte Center-point-bondpads) befinden, die durch Bonddrähte mit Leiterbahnen der Leiterplatte verbunden sind.According to the innovation, the task is solved by having bonding islands (so-called center-point bond pads) on the chip outside the edge area, which are connected to conductor tracks on the circuit board by bonding wires.

Zweckmäßigerweise wird dabei die Oberfläche in bekannter Weise passiviert. Es ist auch möglich, die neuerungsgemäße Anordnung mehrfach auf einer Leiterplatte, vorzugsweise in einer Reihe als Mehrfach-Chip-Anordnung auszubilden.The surface is expediently passivated in a known manner. It is also possible to form the arrangement according to the innovation several times on a circuit board, preferably in a row as a multiple chip arrangement.

Eine vorteilhafte Ausgestaltung der Neuerung sieht vor, daß sich in der Leiterplatte mindestens ein Durchbruch oder eine Ausfräsung befindet und daß das Chip versenkt in dem Durchbruch oder der Ausfräsung angeordnet ist.An advantageous embodiment of the innovation provides that there is at least one opening or milled recess in the circuit board and that the chip is arranged countersunk in the opening or milled recess.

Eine weitere Ausführung der Neuerung besteht darin, daß auf der Leiterplatte um das Chip Schutzstreifen, vorzugsweise in Form eines Kunststoff-0 rahmens, angeordnet sind. Dabei kann das Chip auch ohne daß sich in der Leiterplatte eine Ausfräsung oder ein Durchbruch befindet, auf die Leiterplatte aufgesetzt werden.Another version of the innovation consists in the fact that protective strips, preferably in the form of a plastic frame, are arranged around the chip on the circuit board. The chip can also be placed on the circuit board without there being a cutout or opening in the circuit board.

Ferner ist es möglich, daß die Bonddrähte bogenförmig angeordnet sind.It is also possible for the bonding wires to be arranged in an arc shape.

Eine weitere Ausführungsform der Neuerung sieht vor, daß als Bonddrähte Aluminiumdrähte verwendet werden.Another embodiment of the innovation provides for the use of aluminum wires as bonding wires.

Bei einer vorteilhaften Weiterbildung der Neuerung ist vorgesehen, daß das Chip ein DRAM mit einer Speicherkapazität von 3 Mb oder ein ganzzahliges Vielfaches davon enthält.In an advantageous further development of the innovation, the chip contains a DRAM with a storage capacity of 3 Mb or an integer multiple thereof.

Ferner ist es möglich, daß das Chip mindesten ein DRAM mit einer Speicherkapazität 4 Mb oder ein ganzzahliges Vielfaches davon enthält, das in gleiche Bereiche aufgeteilt ist, von denen einige mit der Leiterplatte verbunden sind. Auf diese Weise gelingt es, auch Chips einzusetzen, die ursprünglieh für andere Einsatzzwecke vorgesehen waren und beispielsweise aus fertigungstechnischen Gründen nicht die volle Kapazität erreichen.It is also possible for the chip to contain at least one DRAM with a storage capacity of 4 Mb or an integer multiple of this, which is divided into equal areas, some of which are connected to the circuit board. In this way, it is possible to use chips that were originally intended for other purposes and, for example, do not reach full capacity for manufacturing reasons.

Eine zweckmäßige Ausführungsform des neuerungsgemäßen Chip-Moduls entsteht dadurch, daß auf dem Chip die PQ- und PD-Signale sowie die PCAS- und CAS-Signale miteinander verbunden sind.A practical embodiment of the chip module according to the innovation is created by connecting the PQ and PD signals as well as the PCAS and CAS signals on the chip.

Von besonderem Vorteil bei der Neuerung ist, daß durch die neuerungsgemäße Anordnung der Bonddrähte ein Kantenschluß zwischen Chip und Leiterplatte vermieden wird.A particular advantage of the innovation is that the innovative arrangement of the bonding wires prevents edge contact between the chip and the circuit board.

Durch die Möglichkeit der Versenkung der Chips in der Leiterplatte ist außerdem ein geringer Platzbedarf gewährleistet, wodurch eine große Packungsdichte erzielt wird. Weiterhin ergeben sich günstige Möglichkeiten für die Wärmeabfuhr und geringe Leiterzugwege. Dadurch werden wiederum geringe Taktzeiten und eine geringe kapazitive Belastung erreicht.The possibility of sinking the chips into the circuit board also ensures that little space is required, which results in a high packing density. Furthermore, there are favorable options for heat dissipation and short conductor paths. This in turn results in short cycle times and a low capacitive load.

Die Neuerung soll im folgenden anhand eines Ausführungsbeispieles näher erläutert werden. In der zugehörigen Zeichnung zeigen:The innovation will be explained in more detail below using an example. The accompanying drawing shows:

Figur 1 Eine Schnittdarstellung des neuerungsgemäßen Chip-Moduls in Mehrfachanordnung.Figure 1 A sectional view of the new chip module in multiple arrangement.

Figur 2 Die Draufsicht auf ein neuerungsgemäßesFigure 2 The top view of a new

Chip-Modul, auf dem sich unterschiedliche
Formen von Schutzstreifen befinden.
20Chip module on which different
forms of protective strips.
20

Figur 3 Ein Schaltungsbeispiel für die Anwendung
der Neuerung bei einem SIMM mit 3 Mb-Drams. Figure 3 A circuit example for the application
the innovation in a SIMM with 3 Mb DRAMs.

5 Wie aus Figur 1 ersichtlich ist, ist das neuerungsgemäße Modul auf einer Leiterplatte 1 angeordnet. In der Leiterplatte 1 sind in diesem Beispiel drei Ausfräsungen eingebracht, in denen die Chips 2.1 bis 2.3 angeordnet sind. Die Chips sind über 0 Bonddrähte 4 mit den auf der Leiterplatte 1 angeordneten Leiterbahnen 3 verbunden. Die Bonddrähte 4 sind in diesem Beispiel bogenförmig angeordnet.5 As can be seen from Figure 1, the module according to the innovation is arranged on a circuit board 1. In this example, three cutouts are made in the circuit board 1, in which the chips 2.1 to 2.3 are arranged. The chips are connected via 0 bond wires 4 to the conductor tracks 3 arranged on the circuit board 1. The bond wires 4 are arranged in an arc shape in this example.

Bei der in Figur 2 dargestellten Anordnung ist das Chip 2 auf eine Leiterplatte 1 aufgesetzt, die nicht mit einer Ausfräsung oder einem Durchbruch versehen ist. Um das Chip 2 herum sind Schutzstreifen 5 angebracht. Die Schutzstreifen 5 können in vielfältigen Formen ausgebildet sein, beispielsweise in Form von Längsstreifen oder als Kunststoffrahmen 5.1.In the arrangement shown in Figure 2, the chip 2 is placed on a circuit board 1 which is not provided with a milled-out section or an opening. Protective strips 5 are attached around the chip 2. The protective strips 5 can be designed in a variety of forms, for example in the form of longitudinal strips or as a plastic frame 5.1.

Eine bevorzugte Anwendungsmöglichkeit der Neuerung besteht in der Verwendung als SIMM (Singel Inline Memory Modul) für Speicher in PCs. Die nach dem Stand der Technik bekannten SIMMs haben eine Datenstruktur von 9, 18 oder 36 Bit. Eine vorteilhafte Ausgestaltung des neuerungsgemäßen SIMM hat, wie in Figur 3 dargestellt, Leitungen für die Signale PCAS und CAS sowie PQ und PT zusammengefaßt. Diese sogenannte Security-Circiut-Schaltung hat den Vorteil, daß bei schlechter Kontaktierung oder Störungen von den PCAS-, PQ- oder PT - Signalen trotzdem fehlerfreies Arbeiten möglich ist.A preferred application of the innovation is its use as a SIMM (Single Inline Memory Module) for memory in PCs. The SIMMs known from the state of the art have a data structure of 9, 18 or 36 bits. An advantageous design of the SIMM according to the innovation has, as shown in Figure 3, combined lines for the signals PCAS and CAS as well as PQ and PT. This so-called security circuit has the advantage that, even if the contact is poor or there are interferences with the PCAS, PQ or PT signals, error-free operation is still possible.

Claims (7)

SCHUTZANSPRUCHEPROTECTION CLAIMS l. Chip-Modul, bei dem mindestens ein Chip, vorzugsweise ein Speicher oder ein Prozessor, auf einer Leiterplatte angeordnet ist, dadurch gekenn zeichnet, daß sich auf dem Chip (2) außerhalb des Randes Bondinseln befinden, die durch Bonddrähtel. Chip module in which at least one chip, preferably a memory or a processor, is arranged on a printed circuit board, characterized in that bonding islands are located on the chip (2) outside the edge, which are connected by bonding wires (4) mit Leiterbahnen (3) der Leiterplatte (1) verbunden sind.(4) are connected to conductor tracks (3) of the circuit board (1). 2. Chip-Modul nach Anspruch 1, dadurch gekennzeichnet, daß sich in der Leiterplatte (1) mindestens ein Durchbruch oder eine Ausfräsung befindet und das Chip (2) versenkt in dem Durchbruch oder der Ausfräsung angeordnet ist.2. Chip module according to claim 1, characterized in that there is at least one opening or milled recess in the circuit board (1) and the chip (2) is arranged countersunk in the opening or milled recess. 2. Chip-Modul nach Anspruch 1, dadurch gekennzeichnet, daß auf der Leiterplatte (1) um das Chip (2) Schutzstreifen (5), vorzugsweise in Form eines Kunststoffrahmens (5.1), angeordnet sind.2. Chip module according to claim 1, characterized in that protective strips (5), preferably in the form of a plastic frame (5.1), are arranged on the circuit board (1) around the chip (2). 3. Chip-Modul nach Anspruch 1, dadurch gekennzeichnet, daß die Bonddrähte (4) bogenförmig angeordnet sind.3. Chip module according to claim 1, characterized in that the bonding wires (4) are arranged in an arc shape. 4. Chip-Modul nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß als Bonddrähte (4) Aluminiumdrähte verwendet werden.4. Chip module according to one of claims 1 to 3, characterized in that aluminum wires are used as bonding wires (4). 5. Chip-Modul nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß das Chip (2) ein DRAM mit einer Speicherkapazität von 3 Mb oder ein ganzzahliges Vielfaches davon enthält.5. Chip module according to one of claims 1 to 4, characterized in that the chip (2) contains a DRAM with a storage capacity of 3 Mb or an integer multiple thereof. 6. Chip-Modul nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß das Chip (2) mindesten ein DRAM mit einer Speicherkapazität 4 Mb oder ein ganzzahliges Vielfaches davon enthält, das in gleiche Bereiche aufgeteilt ist, von denen einige mit der Leiterplatte (1) verbunden sind.6. Chip module according to one of claims 1 to 4, characterized in that the chip (2) contains at least one DRAM with a storage capacity of 4 Mb or an integer multiple thereof, which is divided into equal areas, some of which are connected to the circuit board (1). 7. Chip-Modul nach Anspruch 5 oder 6, dadurch gekennzeichnet, daß auf dem Chip die PQ- und PD-Signale sowie die PCAS- und CAS-Signale miteinander verbunden sind.7. Chip module according to claim 5 or 6, characterized in that the PQ and PD signals as well as the PCAS and CAS signals are connected to one another on the chip.
DE9210198U 1992-07-30 1992-07-30 Chip module Expired - Lifetime DE9210198U1 (en)

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DE9210198U DE9210198U1 (en) 1992-07-30 1992-07-30 Chip module

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DE9210198U DE9210198U1 (en) 1992-07-30 1992-07-30 Chip module

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DE9210198U Expired - Lifetime DE9210198U1 (en) 1992-07-30 1992-07-30 Chip module

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4335822A1 (en) * 1993-10-20 1995-04-27 Teltron Elektronik Gmbh Electronic module with IC
DE4342767A1 (en) * 1993-12-15 1995-06-22 Ant Nachrichtentech Method for producing a cuboid recess for receiving a component in a carrier plate
DE29515521U1 (en) * 1995-09-28 1996-01-18 TELBUS Gesellschaft für elektronische Kommunikations-Systeme mbH, 85391 Allershausen Multi-chip module
DE19642488A1 (en) * 1996-10-15 1998-04-16 Bernd Klose Thin-layer circuit board for e.g. chip card

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4335822A1 (en) * 1993-10-20 1995-04-27 Teltron Elektronik Gmbh Electronic module with IC
DE4342767A1 (en) * 1993-12-15 1995-06-22 Ant Nachrichtentech Method for producing a cuboid recess for receiving a component in a carrier plate
DE29515521U1 (en) * 1995-09-28 1996-01-18 TELBUS Gesellschaft für elektronische Kommunikations-Systeme mbH, 85391 Allershausen Multi-chip module
DE19642488A1 (en) * 1996-10-15 1998-04-16 Bernd Klose Thin-layer circuit board for e.g. chip card

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