WO2003085829A1 - Circuit integre a application specifique pour dispositif de filtrage passe-bas destine au decouplage des voies xdsl - Google Patents
Circuit integre a application specifique pour dispositif de filtrage passe-bas destine au decouplage des voies xdsl Download PDFInfo
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- WO2003085829A1 WO2003085829A1 PCT/EP2003/050093 EP0350093W WO03085829A1 WO 2003085829 A1 WO2003085829 A1 WO 2003085829A1 EP 0350093 W EP0350093 W EP 0350093W WO 03085829 A1 WO03085829 A1 WO 03085829A1
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- asic
- filtering device
- circuit
- low frequency
- admittance
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0002—Modulated-carrier systems analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/34—Networks for connecting several sources or loads working on different frequencies or frequency bands, to a common load or source
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
Definitions
- the present invention relates to an integrated circuit for specific application, or ASIC (Application Specifies Integrated Circuit in English) for a low-pass filtering device intended for decoupling xDSL channels. It is in particular intended to be incorporated into a device for separating voice-data signals for transmission over xDSL channels. It offers a specific architecture of an integrated circuit with a specific application, making it possible in particular to improve the selectivity of the filtering device in which it is arranged.
- ASIC Application Specifies Integrated Circuit in English
- the field of the invention is, in general, that of so-called xDSL technologies.
- ADSL technology for Asymmetric Digital Subscriber Line, in English, for digital subscriber line with asymmetric speed
- VDSL technology for Very-high-data rate Digital Subscriber Line, for d line 'very high speed digital subscriber
- HDSL or SDSL technologies for example ADSL technology (for Asymmetric Digital Subscriber Line, in English, for digital subscriber line with asymmetric speed), VDSL technology (for Very-high-data rate Digital Subscriber Line, for d line 'very high speed digital subscriber), or HDSL or SDSL technologies.
- the invention will be more particularly described, by way of example, in the context of ADSL. However, it can also be used with other xDSL technologies.
- These technologies are mainly implemented on local loops of existing telephone networks, the local loop being constituted by the network intermediaries between a telephone exchange and a subscriber station.
- One of the essential objectives of these technologies is to make possible, on the local loops of the old telephone networks, the simultaneous transmission of different types of signals: on the one hand, the signals relating to the usual telephone conversations between two subscribers, these first signals comprising signals relating to voice and signaling signals, and secondly, signals relating to data, typically information exchanged between a subscriber and a site accessible via the Internet.
- the pair of copper wires which arrives at the subscriber's, and which has long constituted the telephone line, or subscriber loop, to which the various telephone handsets, also designated as narrowband terminals, user of analog networks traditional so-called POTS (for Plain Old Telephone System) or traditional digital networks called ISDN (or ISDN - integrated service digital network).
- POTS Plain Old Telephone System
- ISDN ISDN - integrated service digital network
- Analog baseband signals typically have a frequency of 0 to 4 kHz, or 0 to 16 kHz if signal signals are taken into account.
- the digital baseband signals are in frequencies from 0 to 94 KHz. In practice, the baseband is intended for transmission in circuit mode;
- the high band extends from the top of the telephone base band to around 1 MHz.
- the high frequency band is spread from 26 KHz to 1.1 MHz if the pair of copper wires is used as baseband for an analog POTS transmission, and from 138 KHz to 1.1 MHz if it is used for a transmission.
- digital It is normally intended for permanent transmission, mainly in packet mode, ie permanent communication is established between the subscriber and the telephone exchange.
- connection with dial-up access is a method of temporary connection to a computer network consisting of using a modem, connection software and the switched telephone network as a means of setting up. communication from your own computer and from another computer on the network.
- the baseband can be used, in particular with preferably digital modems, to transmit data
- the high frequency band can be used to ensure phonic communications within the framework of communications called telephone communications on the Internet
- the baseband is used for the transmission of a first type of signals, essentially speech, corresponding to phonic communications
- the high frequency band is used for the transmission of a second type of signals, essentially data, relating in particular to the consultation of Internet sites.
- the baseband is only capable of low speed (currently 56 Kbits / s for analog modems and 64 Kbits / s for digital modems) while the high frequency band is likely to have a high speed (possibly around 10 Mbits / s).
- Figure 1 illustrates the operation of the frequency band in ADSL distribution.
- the ordinate axis 100 scales the power of the signals transmitted, and the abscissa axis 101 gives the frequency scale.
- the powers emitted are represented equally for the purpose of simplification.
- the spectrum 103 is divided into two main parts: a first frequency band 104 corresponding to the spectrum used for the uplink data (from the subscriber to the central office) and a second frequency band 105 corresponding to the spectrum used for the downlink data (from the central to the subscriber).
- the second frequency band 105 is wider than the first frequency band 104 because the uplink data, which most often correspond to requests sent by a subscriber, are most often less numerous than the downlink data, which can correspond to the download. large files, such as images.
- FIG. 2 schematically illustrates these separations at the level of a local communication loop.
- a conventional telephone line 200, or subscriber loop is shown, composed of two copper wires, which provides the link between a subscriber 201, which has a private installation, and a telephone exchange 202.
- the telephone exchange 202 provides the connection to a conventional telephone network 203 and to an Internet type network 204.
- a first device 205 for separating voice-data signals also called a switch filter or splitter.
- a splitter is an electronic device associated with an ADSL modem which makes it possible to separate the voice signals from the data signals and to route them on two different channels.
- the splitter 205 will be designated subsequently as the central splitter.
- the central splitter 205 is most often incorporated into a splitter card, this card being able to include up to a few tens of central splitters. Its function is to separate the data signals, which are oriented towards the Internet network 204, and the voice signals, which are oriented towards the conventional telephone networks 203. Another function of the central splitter 205 is to multiplex the signals of voice, emitted by conventional telephone networks 203, and signals emitted by an access multiplexer 206 subsequently detailed, in order to route them on the same twisted pair 200. In theory, there is in the central splitter 205 a low frequency filter and a high frequency filter, which pass the phonic signals and the ADSL signals respectively.
- the design of the central splitter 205 must be such that the conventional telephone services of the POTS and / or ISDN networks are not disturbed by the presence of the ADSL signals, and that the data flow of the ADSL signals is not affected by certain observable conventional operations. on these networks, in particular off-hook / on-hook operations.
- DSLAM Digital Subscriber Line Access Multiplexer
- a DSLAM is a multiplexer of access, specially designed for DSL equipment, usually located on the premises of telephone exchanges, which transmits signals over the Internet using a time division multiplex technique.
- the splitter 207 On the subscriber's side 201, there is also a splitter 207 connected to the telephone line 200.
- the splitter 207 is called the master splitter.
- the master splitter 207 also has the function of separating the signals from data, which are directed to a personal computer 208 associated with an ADSL modem, and voice signals, which are directed to conventional telephone handsets 209.
- the master splitter 207 there is also in the master splitter 207 a low frequency filter and a filter high frequency, which pass phonic signals and ADSL signals respectively.
- the design of the master splitter 207 must be such that, as for the central splitter 205, it must be able to avoid any interference or alteration phenomenon, for each type of signal, which could be caused by the other type of signal.
- the low frequency splitter filter and the high frequency filter are separate and distinct. In the figure, these filters are shown only on the subscriber side.
- the high frequency filter 210 that is to say the filter which lets the data signals pass and only these, is placed between the telephone line 200 and the DSLAM 206 (telephone exchange side) and between the telephone line 200 and l personal computer 208 (subscriber side).
- the high frequency filter 210 can be incorporated, partially or totally, in an ADSL modem.
- the low frequency filter 211 is, for its part, disposed between the telephone line 200 and the conventional telephone network 203 (telephone exchange side) and between the telephone line 200 and the conventional telephone handsets 209 (subscriber side).
- Each filter is used to isolate the installation that it connects signals intended for the other installation.
- the low frequency filter 211 serves to prevent the phonic signals from being disturbed by the data signals.
- such low frequency filters are also called “splitters” insofar as the high-pass filter necessary for the modem is integrated in this same modem.
- Such filters often called microfilters, are incorporated in filtering devices which are the subject of the invention.
- ILF Insertion Loss Factor in English
- ILF Insertion Loss Factor in English
- this factor measures the loss of transmission caused in the circuit by the installation of a filter, between a situation where the filter is not present and a situation where it is installed; according to the various standards in force, when the characteristic impedance is purely resistive, the loss must be less than 0.3 dB; for complex impedances, the insertion loss must be less than 1 dB.
- RLF Return Loss in English
- RLF 20 log 10 abs (((Zin (w) + Zc (w)) / ((Zin (w) -Zc (w))), where Zin (w) measures the input impedance of the device whose wants to measure the RLF, and where Zc (w) is the impedance of a reference load.
- Zin (w) measures the input impedance of the device whose wants to measure the RLF
- Zc (w) is the impedance of a reference load.
- the structure of elliptical filters is made up of non-dissipative passive components.
- the complex nature of the characteristic line impedances, the imaginary part of which is no longer negligible with xDSL technologies requires, in order to obtain an optimal filter, to introduce correctors made up of some negative resistances and / or capacities. Such correctors must therefore use active components which are not provided in these filters;
- each splitter Due to the large number of coils used in the filters of the prior art, the space occupied by each splitter is of the order of 15 to 20 cm 2 . This space is not negligible, essentially on the telephone exchange side where many splitters are mounted together on the same card.
- the performance of passive filters can vary significantly from one filter to another due to the tolerance of the inductors used, which is of the order of plus or minus 7%.
- ASIC Application Specifies Integrated Circuit in English type for integrated circuit with specific application
- the two ASICs have a similar structure, this structure being an object of the present invention.
- Some passive elements are still present in the low frequency filtering device incorporating the ASICs.
- the device 300 is described in the case where it is placed on the subscriber side A of the line. It could however be placed on the telephone exchange side.
- a conventional telephone line Li composed of a first transmission line 301, called strand A or TIP line, and a second transmission line 302, called strand B or RING line.
- These two inductors have, for reasons of symmetry of the telephone line, the same value. Typically, this value is of the order of 17.5 mH (milliHenry).
- On each transmission line there is then, in series with the inductor 303, respectively 304, an active component of type ASIC 305, respectively 306.
- the two ASICs 305 and 306 must have, for reasons of symmetry of the telephone line Li, identical structures.
- the ASICs constituting the active part are associated with a passive part.
- This passive part notably includes inductors 303 and 304. It can also include:
- a first capacity 310 which connects the two transmission lines 301 and 302 at connection points 312 and 314, situated respectively between the coil 303 and the ASIC 305, and between the coil 304 and the ASIC 306.
- This first capacity 310 essentially makes it possible to supplement the passive part of the device according to the invention, which, associated with inductors 303 and 304, then constitutes a passive filter of order 2.
- the value of this first capacity 310 is typically 27 nF.
- a second capacity 311 which connects the two transmission lines 301 and 302 at connection points 313 and 315 located respectively on the first transmission line 301 and on the second transmission line 302, at the outlet of the filter 300, on the side of subscriber A.
- the second capacity 311 essentially serves to filter a high frequency noise signal which could be generated by each ASIC. It also contributes to the filtering of the high frequency signals transmitted according to the xDSL technologies.
- the value of this second capacitance 311 is typically 56 nF.
- ASICs must be supplied with energy. They are therefore assigned an external energy source suitable for their operation. However, the installation of a filtering device then becomes expensive and restrictive.
- the filtering device makes it possible in particular to solve this problem.
- a particular architecture is proposed for the ASICs presented in FIG. 3.
- One of the essential constraints in the design of an architecture for these ASICs lies in the fact that one no longer wishes to add sources of external energy necessary for the operation of ASICs.
- the proposed architecture therefore offers a solution notably so that the power supply for the ASICs is directly supplied by continuous signals circulating on the telephone line.
- the invention therefore essentially relates to a low-frequency filtering device installed on a telephone line composed of a first transmission line and a second transmission line, said device comprising in particular an active part comprising in particular a first integrated circuit for specific application , or ASIC, and a second identical ASIC, the first ASIC being arranged in series on the first transmission line between a first connection point, connected to a first connection pin of the first ASIC, and a second connection point, connected to a second connection pin of the first ASIC, of the first transmission line, the second ASIC being arranged in series on the second transmission line between a third connection point, connected to the first connection pin of the second ASIC, and a fourth connection point, connected to the second connection pin of the second ASIC, of the second transmission line, characterized in that each ASIC comprises an active rectifier circuit, arranged in series between the first connection pin and the second connection pin of the ASIC in which it is included, to apply a potential difference , whose sign is independent of the direction of a current flowing in the transmission lines, at
- the active admittance performed is a fourth order admittance.
- each ASIC comprises a hook / on-hook detection circuit, disposed in parallel with the active rectifier circuit, for short-circuiting the electronic circuit realizing active admittance when the telephone line is in the on-hook state.
- Each ASIC has a third connection pin which can then be used to connect, via a resistor, the on-hook / on-hook detection circuits of each ASIC.
- each ASIC includes an impedance matching circuit, connected to the first connection pin, to perform an input impedance matching of the low frequency filtering device to the telephone line.
- Each ASIC has a fourth connection pin which can then be used to connect, via a resistor and a capacitor arranged in series, the two impedance matching circuits which are arranged in each ASIC.
- the electronic circuit carrying out active admittance comprises operational amplifiers, characterized by a transconductance, which are directly supplied by the transmission line on which the ASIC to which they belong is arranged. It can also include a voltage drop device so that the voltage applied to the terminals of each operational amplifier characterized by a transconductance is less than the supply voltage of these amplifiers.
- FIG. 3 already described, a block diagram of a low frequency filtering device 300, in which one can incorporate an integrated circuit with specific application of the type of which the structure is the object of the invention;
- FIG. 4 a block diagram showing the main circuits of the architecture of an ASIC used in the low frequency device of the invention
- FIG. 4 schematically illustrates the main electronic circuits which operate within each ASIC incorporated in the low frequency filtering device which is the subject of the invention.
- the ASIC represented is ASIC 305 in FIG. 3, which is also identical to ASIC 306.
- Five of the eight pins, or terminals, for connecting ASIC 305 are represented in this figure: A1, B1, C1, L1 and P1, the latter two corresponding to connection points 312 and 313 shown in Figure 3.
- ASIC 305 which is arranged in series on the first transmission line _
- Pins L1 and P1 are directly connected to two separate electronic circuits of the ASIC 305: a so-called active rectifier circuit 401 and a circuit for detecting off-hook / on-hook operations 404. These two circuits are therefore mounted in parallel, within ASIC 305, on the first transmission line 301.
- a third electronic circuit which is an impedance matching circuit 403, is connected to pin L1.
- a fourth separate electronic circuit 402 within the ASIC 305 is a circuit realizing an active admittance which, in the exposed case, is a fourth order admittance 402. By active admittance, one designates an admittance whose value depends on the frequency signals received by the electronic circuit 402.
- the fourth circuit 402 is directly connected to the active rectifier 401 by means of a first link 405 and a second link 406.
- Pins A1 and B1 are connected to the impedance matching circuit 403; pin C1 is connected to the on-hook / on-hook detection circuit 404.
- FIG. 5 illustrates the arrangement of ASICs 305 and 306 on the transmission lines 301 and 302, as well as the interconnections between these two ASICs.
- the references of the pins of ASIC 305 are terminated by the index 1, while those of the pins of the ASIC 306 are terminated by the index 2.
- This figure essentially illustrates the fact that the pins A1 and A2 are connected by a link comprising a capacitor 501.
- the pins B1 and B2 are connected by a link comprising a resistor 502 connected in series with a capacitor 503.
- the pins C1 and C2 are connected by a link comprising a resistor 504. The role of these passive components will be specified later on in the description of other figures in which they appear.
- the active rectifier circuit 401 when the telephone line is in the off-hook state (or "off hook"), a direct current DC flows on the telephone line L, but in a direction which is a priori unknown: we do not know , for example for ASIC 305, if the DC current enters via terminal L1 and exits via terminal P1 or if it is the opposite.
- the electronic circuit 402 carrying out the admittance of the fourth order comprises in particular amplifiers which must be supplied correctly.
- the role of the active rectifier circuit 401 is therefore to create two potentials V + and V- independently of the direction of the current at the terminals L1 and P1.
- this circuit makes it possible to obtain, between the terminals L and P of each ASIC, an admittance Y (p) of the form:
- the so-called fourth order admittance circuit includes a voltage drop element ensuring that the operational amplifiers of circuit 402 carrying out the fourth order admittance will always be supplied by a potential V + and a potential V-, which are always, in absolute value, greater than the amplitude of the voltages applied to them.
- this circuit makes it possible to change the input resistance of the low-pass filtering device 300 described in FIG. 3.
- this circuit makes it possible to show, as a function of the frequencies of the different signals transmitted to the ASICs, a negative impedance between the terminals L1 and L2 of the ASICs 305 and 306.
- the on-hook / on-hook detection circuit 404 when the line is on-hook (on hook), this circuit makes it possible to obtain a low resistance value, of the order of 50 ohms, between the terminals L and P of each ASIC. The fourth order admittance is then short-circuited. As soon as the line is off hook (off hook in English), a current greater than a predetermined threshold value appears on the telephone line, and the on-hook / on-hook detection circuit 404 makes it possible to obtain an impedance of very high value.
- FIG. 6 An exemplary embodiment of the active rectifier circuit 401 is represented in FIG. 6.
- the circuit 401 comprises four field effect transistors (FET), two with N channel, N61 and N62, and two with P channel, P61 and P62.
- Terminal L is directly connected to the source of FET P61, to the drain of FET N61, and to the gates of FET P62 and N62.
- Terminal P is directly connected to the source of FET P62, to the drain of FET N62, and to the gates of FET P61 and N61.
- the circuit 401 has two ends which are referenced 601 and 602; it makes it possible to obtain at point 601 a potential V + and at point 602 a potential V- lower than the potential V +, and this independently of the relative values of the potentials V (L) and V (P). Between the ends 601 and 602, an impedance 603 of value Z can be arranged. In the realization of the ASIC intervening in the object of the invention, it is the admittance of the fourth order which is arranged between the ends 601 and 602.
- the circuit 402 providing fourth order admittance is a voltage controlled current source.
- the voltage which controls this current source is the potential difference between terminal L and terminal P of each ASIC, which is found between the ends 601 and 602 of circuit 401.
- Active elements are used in this circuit: this are OTA (for Operational Transconductance Amplifier in English), i.e. operational amplifiers characterized by their transconductance.
- the circuit 700 has an input 711 brought to the potential V + and an output 712 brought to the potential V-.
- An OTA 701 is characterized by a transconductance g1. It has a first input 702 and a second input 703 whose potential is lower than the potential of the first input 702.
- a conductive link 704, which is connected to input 711, is connected on the one hand to the first input 702 of OTA 701, at a capacitor C11 and at the source of a P-channel field effect transistor 706.
- the drain of this FET 206 is connected via a resistor R0 to a conductive link 705 which is connected to the output 712.
- the conductive link 705 is also connected to a capacitor C12, which is itself connected to the capacitor C11.
- the output of the OTA 701 is connected to a connection point 707 located on a link connecting the two capacitors C11 and C12.
- a positive input 708 of an operational amplifier 709 is also connected to the connection point 707.
- the negative input 710 of the operational amplifier 709 is connected to a link connecting the second input 703 of the OTA 701 to a connection point 717 located between the drain of FET 706 and the resistance R0.
- the output of the operational amplifier 709 is connected to the gate of the FET 706.
- the operational amplifier 709 has a very high gain.
- two dotted lines 713 and 714 define in the space separating them, a basic cell 715. It comprises in particular the OTA 701 and the two capacitors C11 and C12.
- the part of the circuit 700 located to the right of the dotted line 714 constitutes a cell 716 called termination.
- the termination cell 716 notably comprises the operational amplifier 709, the FET 706 and the resistor R0.
- the circuit 402 performing fourth order admittance is shown in FIG. 8. This circuit is in fact made up of the juxtaposition of four base cells 715, then of the termination cell 716.
- Each basic cell therefore comprises an OTA 80X characterized by a transconductance gX, corresponding to the OTA 701 in FIG. 7, a first capacity CX1, corresponding to the capacity C11 in FIG. 7, a second capacity CX2, corresponding to the capacity C 2 in FIG. 7, and a connection point 81 X corresponding to the connection point 707 in FIG. 7, where X, which varies from 1 to 4, denotes the number of the basic cell to which an element belongs.
- the first basic cell differs slightly from the following three in that it has a voltage drop element 820 intended to lower the voltage of the alternating signals which are applied between input 711 and output 712 of circuit 402.
- Each OTA is directly connected, at its positive and respectively negative supply terminal, to the link 704 brought to the potential V +, respectively to the link 705 brought to the potential V-.
- Such values make it possible to obtain an active impedance, inverse to the active admittance, as represented on the curve of FIG. 14.
- the impedance is almost zero for frequencies close to 0 and for frequencies above 200 kHz, and that it presents, in absolute value, a maximum for frequency values close to 30 kHz.
- the rejection level will thus be maximum for frequencies close to 30 kHz, the separation of low frequency and high frequency signals can thus be ensured.
- the maximum value of the impedance is close to 10 kiloOhms
- FIG. 9 illustrates an exemplary embodiment of the OTA 801 associated with the voltage drop element 820.
- the positive input in + of amplifier 801 is directly connected to the gate of a P-channel field effect transistor, P901, the source of this FET being connected to the negative input of amplifier 801.
- the drain of FET P901 constitutes the output of the amplifier 801, that is to say that it leads to the connection point 811.
- the voltage drop element 820 here combines the voltage across the resistor 900 and the gate-source voltage of the transistor P901.
- the transconductance g1 is, as a first approximation, inversely proportional to the value of the resistance 900.
- FIG. 10 illustrates an exemplary embodiment of the OTAs 802, 803 and 804, which are identical.
- the positive input in + of the amplifier 80X is directly connected to the gate of a first P-channel field effect transistor, P101
- the negative input in- of the amplifier 80X is directly connected to the gate of a second P-channel FET, P102.
- the sources of these two FETs are connected to a conductive link 1000 brought to the potential V +.
- the drain of the FET P102 is connected to the drain of an N-channel FET, N102.
- the grid of this FET N102 is connected on the one hand to the grid of another N-channel FET, N101, and to the drains of the FETs P101 and N101.
- the sources of the FETs N101 and N102 are connected to a link which is brought to the potential V-.
- the current source 902 notably includes an internal resistance not shown, which is a clone of the internal resistance Rin in FIG. 9, which makes it possible to define the current output, and thus to adjust the transconductance of each OTA.
- the transconductance g x is also dependent on the characteristics of the transistors.
- FIG. 11 is an exemplary embodiment of the off-hook / on-hook detection circuit 404.
- the elements intervening for a case of polarization of the circuit have been represented, which corresponds to a determined direction of the current in the transmission lines. 301 and 302.
- the Figure 11 is composed of a first elementary block 1101, present in ASIC 305, and a second elementary block 1102, present in ASIC 306.
- the first elementary block 1101 comprises five P-channel field effect transistors.
- the terminal L1 is directly connected to the source of a FET P112, of a FET P114, of a FET P113 and to the gate of a FET. P111.
- Terminal P1 is directly connected to the source of FET P111, of a FET P115, to the drain of FET P113 and to the gate of FET P112.
- the drains of the FETs P111 and P112 are connected to a connection point 1103 which is moreover connected to a connection point 1104.
- the connection point 1104 is moreover connected to the grid of the FETs P113, P114 and P115, as well as at terminal C1.
- terminal C1 is directly connected to the drains of FET P114 and P115.
- the first elementary block is, in practice, doubled: an additional elementary block, not shown, belonging to the same ASIC, is mounted in parallel with block 1101 between the terminals L1 and P1.
- This complementary block occurs when the direction of the current, in the transmission lines 301 and 302, is reversed with respect to that which has been determined above.
- These two blocks are identical, with the difference that all the P-channel FETs of block 1 101 are replaced by N-channel FETs.
- the combination of these two blocks constitutes the on-hook / on-hook detection circuit shown in FIG. 4 .
- Terminal C1 is connected to terminal C2 via resistor 504, typically with a value of 4.7 megaOhms.
- Block 1 102 has a symmetrical structure to that of block 1101 with respect to the resistor 504 separating them, with the difference that all the P-channel FETs have been replaced by N-channel FETs.
- block 1102 is completed, in order to constitute the off-hook / on-hook detection circuit of the ASIC 306, by another complementary block, not shown, mounted in parallel with the second elementary block 1102 between the terminals L2 and P2, of the same structure as the block 1 102, except that the N-channel FETs have been replaced by P-channel FETs
- FIG. 12 gives an exemplary embodiment of the impedance matching circuit 403.
- This circuit notably comprises five resistors: R101, R102, R103, R104 and R105, an operational amplifier 120 and a P-channel FET, P122.
- Pin L is connected to pin A via resistor R105, to a positive input 123 of amplifier 120 through resistor R101, to a negative input 124 of amplifier 120 through intermediate of resistance R102, and at the source of FET P122.
- the negative input 124 of the amplifier 120 is connected, via the resistor R104 to a link 125 connecting the drain of the FET P122 and the terminal B.
- the positive input 124 of the amplifier 120 is connected, by via resistor R103 at terminal B.
- the output of amplifier 120 is connected to the gate of FET P122.
- Zin (p) Z ((R1 + R3) .C.p + 1 + (R1 + R3) / R5) / ((R3-R4R1 / R2) .Cp + 1 + (R1 + R3) / R5) ( equation 17) where Rx corresponds to R10x, x can vary from 1 to 5, for the sake of simplification of equation 17.
- R101 150 kiloOhms
- R102 100 kiloOhms
- R103 50 kiloOhms
- R104 83 kiloOhms
- the impedance matching circuit 404 behaves like a negative impedance with a gain of -2.68.
- the impedance is simply equal to Z.
- Figure 13 shows the main circuits which have just been described. It also includes an EEPROM 131 type memory module, a _
- the multiplexer 133 is connected to the DATA terminal, the CK terminal makes it possible to send a clock signal to the FIFO memory 132, and the Vpp terminal is connected to the EEPROM memory 131.
- the multiplexer 133 can receive data from the FIFO memory module 132 and communicate data to it in multiplexed form.
- the FIFO memory can exchange data with the EEPROM 131. This system allows 16 bits to be used to control the ASIC programming process.
- a first bit is used to determine whether the variables to be programmed in the ASIC are defined by the content of the FIFO memory 132 or by the content of the EEPROM 131.
- a second bit is used to determine whether the admittance to be achieved corresponds to the European standard or American standard.
- 3 bits are reserved for the parameter setting of the voltage Vdrop, which amounts to adjusting the resistance R900 of figure 9
- 6 bits are reserved for the parameter setting of the various transconductances, which amounts to adjusting the value of the resistors Rin present in the sources current in Figures 9 and 10
- 5 bits are reserved for setting the resistance R0.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Networks Using Active Elements (AREA)
- Interface Circuits In Exchanges (AREA)
- Telephone Function (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03730176A EP1493228B1 (fr) | 2002-04-05 | 2003-04-07 | Circuit integre a application specifique pour dispositif de filtrage passe-bas destine au decouplage des voies xdsl |
AU2003240763A AU2003240763A1 (en) | 2002-04-05 | 2003-04-07 | Application-specific integrated circuit for a low-pass filtering device used for decoupling xdsl channels |
DE60323956T DE60323956D1 (de) | 2002-04-05 | 2003-04-07 | Anwendungsspezifische integrierte schaltung für eine zum entkoppeln von xdsl-kanälen verwendete tiefpassfiltereinrichtung |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR02/04295 | 2002-04-05 | ||
FR0204295A FR2838255B1 (fr) | 2002-04-05 | 2002-04-05 | Circuit integre a application specifique pour dispositif de filtrage passe-bas destine au decouplage des voies xdsl |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003085829A1 true WO2003085829A1 (fr) | 2003-10-16 |
Family
ID=28052159
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2003/050093 WO2003085829A1 (fr) | 2002-04-05 | 2003-04-07 | Circuit integre a application specifique pour dispositif de filtrage passe-bas destine au decouplage des voies xdsl |
Country Status (8)
Country | Link |
---|---|
EP (1) | EP1493228B1 (fr) |
CN (1) | CN100449941C (fr) |
AT (1) | ATE410825T1 (fr) |
AU (1) | AU2003240763A1 (fr) |
DE (1) | DE60323956D1 (fr) |
ES (1) | ES2315499T3 (fr) |
FR (1) | FR2838255B1 (fr) |
WO (1) | WO2003085829A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1903674A1 (fr) * | 2006-09-22 | 2008-03-26 | Alcatel Lucent | Filtre pass-bas d'ordre élevé pour dispositif séparateur xDSL |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0942578A2 (fr) * | 1998-03-12 | 1999-09-15 | Westell Technologies, Inc. | Filtre à deux modes pour LNAA |
EP1005209A2 (fr) * | 1998-11-25 | 2000-05-31 | Westell Technologies, Inc. | Procédé de signalisation pour appeler un mode de test dans un dispositif d'interface de réseau |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5623543A (en) * | 1994-02-01 | 1997-04-22 | British Telecommunications Public Limited Company | Two port signalling voltages filter arrangement |
US5699421A (en) * | 1995-05-31 | 1997-12-16 | Casio Phonemate, Inc. | Telephone answering device with low cost dual tone multi-frequency detector |
DE69836263T2 (de) * | 1998-06-26 | 2007-05-31 | Alcatel | Filteranordnung anwendbar auf ADSL-teiler |
US6549616B1 (en) * | 2000-03-20 | 2003-04-15 | Serconet Ltd. | Telephone outlet for implementing a local area network over telephone lines and a local area network using such outlets |
-
2002
- 2002-04-05 FR FR0204295A patent/FR2838255B1/fr not_active Expired - Fee Related
-
2003
- 2003-04-07 EP EP03730176A patent/EP1493228B1/fr not_active Expired - Lifetime
- 2003-04-07 WO PCT/EP2003/050093 patent/WO2003085829A1/fr not_active Application Discontinuation
- 2003-04-07 AU AU2003240763A patent/AU2003240763A1/en not_active Abandoned
- 2003-04-07 ES ES03730176T patent/ES2315499T3/es not_active Expired - Lifetime
- 2003-04-07 CN CNB038126141A patent/CN100449941C/zh not_active Expired - Fee Related
- 2003-04-07 AT AT03730176T patent/ATE410825T1/de not_active IP Right Cessation
- 2003-04-07 DE DE60323956T patent/DE60323956D1/de not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0942578A2 (fr) * | 1998-03-12 | 1999-09-15 | Westell Technologies, Inc. | Filtre à deux modes pour LNAA |
EP1005209A2 (fr) * | 1998-11-25 | 2000-05-31 | Westell Technologies, Inc. | Procédé de signalisation pour appeler un mode de test dans un dispositif d'interface de réseau |
Also Published As
Publication number | Publication date |
---|---|
EP1493228A1 (fr) | 2005-01-05 |
AU2003240763A1 (en) | 2003-10-20 |
FR2838255A1 (fr) | 2003-10-10 |
ES2315499T3 (es) | 2009-04-01 |
DE60323956D1 (de) | 2008-11-20 |
EP1493228B1 (fr) | 2008-10-08 |
FR2838255B1 (fr) | 2004-06-18 |
CN100449941C (zh) | 2009-01-07 |
ATE410825T1 (de) | 2008-10-15 |
CN1659781A (zh) | 2005-08-24 |
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