WO2003083696A1 - Logical calculation architecture comprising several configuration modes - Google Patents

Logical calculation architecture comprising several configuration modes Download PDF

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Publication number
WO2003083696A1
WO2003083696A1 PCT/FR2003/001050 FR0301050W WO03083696A1 WO 2003083696 A1 WO2003083696 A1 WO 2003083696A1 FR 0301050 W FR0301050 W FR 0301050W WO 03083696 A1 WO03083696 A1 WO 03083696A1
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calculation
architecture
components
configuration
logical
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PCT/FR2003/001050
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French (fr)
Inventor
Lionel Torres
Gaston Cambon
Michel Robert
Gilles Sassatelli
Jerôme GALY
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Centre National De La Recherche Scientifique - Cnrs -
Universite De Montpellier Ii Sciences Et Techniques Du Languedoc
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Priority to JP2003581051A priority Critical patent/JP2005521949A/en
Priority to AU2003258853A priority patent/AU2003258853A1/en
Priority to EP03740562A priority patent/EP1490787A1/en
Publication of WO2003083696A1 publication Critical patent/WO2003083696A1/en
Priority to US10/956,314 priority patent/US20050131980A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Definitions

  • the present invention relates to the field of programmable electronics.
  • One of the main challenges in this area is to make the most efficient use of the time and space available.
  • developments have sought to provide dynamically reconfigurable solutions, that is to say without stopping the calculations.
  • the simplest idea is to configure a part of the architecture when another independent part is currently calculating.
  • the present invention relates more particularly to the design of multi-level configuration modes, that is to say, in an architecture comprising a large number of programmable components the coexistence of two modes of configuration of said components: a global mode for configure the whole architecture and a local mode to configure a small subset of components.
  • the present invention is of the type described above and it is remarkable, in its broadest sense, in that it relates to a logic calculation architecture comprising: - a plurality of configurable calculation components; a plurality of interconnection components; a first set of signals intended to configure the architecture, that is to say the connections between said computation components and said interconnection components; a processor which generates said first set of configuration signals; characterized in that it further comprises: a plurality of configurable control components, each control component being connected to one of said calculation components and said control components being capable of generating at least one calculation instruction intended for said components of calculation; a second set of signals intended to configure said control components.
  • said calculation components perform calculations on sets of data, each set comprising a plurality of bits.
  • control components are connected to said processor.
  • FIG. 1 illustrates a “calculation unit - control unit” assembly
  • FIG. 2 illustrates a logical calculation unit
  • a configurable logical calculation architecture comprises two layers: an operational layer comprising a network of calculation and routing units, which performs the logical calculations on data supplied by an external element; a configuration layer making it possible, on the one hand, to arrange said calculation and routing units in order to organize the direction of data flow and, on the other hand, to configure said calculation units so that they perform a predefined calculation.
  • the configuration layer sends configuration information directly to the components of the computing units. If this architecture includes a large number of calculation and routing units, the configuration of the operational layer can be long.
  • the architecture according to the invention makes it possible to reconfigure the elements of the operational layer according to several modes: a so-called “global” mode, a so-called mode
  • the architecture implemented for the “global” mode comprises an operational layer, a configuration layer and a processor specific to the configuration operations called “configuration controller”.
  • the configuration and operational layers are divided into groups, a group of the operational layer being configured by a group of the configuration layer.
  • Each group of the operational layer includes a plurality of configurable logic elements.
  • An entire group of the operational layer is reconfigurable at each clock cycle. While a calculation is carried out by a first group of the operational layer, the configuration controller modifies the configuration of a group of the configuration layer corresponding to a second group of the operational layer. At the next clock stroke, the second group of the operational layer is reconfigured according to the group of the corresponding configuration layer.
  • the presence of a processor dedicated to configuration management allows management of the conditional configuration: the results calculated by the elements of the operational layer can influence the configuration of the architecture. For this, the architecture sets up a communication bus between the operational layer and the configuration controller.
  • control units include a sequencer of at least one instruction (and preferably 8) and a finite state machine which makes it possible to know the state of the control unit at any time.
  • the configuration layer sends information to the control unit comprising the control instructions for the calculation unit. All of these instructions form a firmware. Then, the sequencer orders the sending of the firmware to the computing unit.
  • the calculation unit thus carries out a series of instructions requiring different configurations without calling on the configuration controller.
  • the calculation unit (1) is connected to at least one input data stream (3) and to at least one output data stream (4). It is also connected to the control unit (2) by the link (5).
  • the control unit (2) is composed of a demultiplexer (21), a mode controller (22), a loading module (23), a set of registers (24) and an output module (25).
  • the mode controller (22) orders the demultiplexer (21) to route the incoming configuration signal: in global mode, that is to say where the calculation unit (1 ) is directly configured by the configuration layer, the signal is transferred directly from the demultiplexer (21) to the output module (25) by the link (26).
  • the output module (25) transmits the configuration information to the calculation unit (1) by the link (5); in local mode, that is to say where the calculation unit (1) is configured by the control unit (2), the demultiplexer (21) transmits the configuration information to the loading module (23) which then downloads the firmware into the set of registers (24). Once loaded and under the command of an instruction specifying it, the firmware is executed by the control unit.
  • the execution of the firmware can follow two procedures: the first procedure consists of the execution of the instructions stored in the registers of the control unit only once; the second procedure consists in the execution of the instructions in a loop, that is to say until the execution is stopped by the configuration controller.
  • An additional register is present in the calculation unit, said additional register containing the end address of the firmware.
  • This architecture is preferably carried out with a calculation unit which operates on “words” of bits, that is to say sets of bits.
  • the calculations are more difficult to program in the calculation unit but a greater number of bits are processed with each clock stroke, which accelerates the calculation process. If a word-by-word calculation architecture is used, the complexity of the calculations implemented makes the configuration more difficult.
  • the use of an architecture according to the invention makes it possible to reduce the difficulty of configuring the architecture.
  • FIG. 2 A logical calculation unit is illustrated in FIG. 2.
  • the logical calculation unit illustrated in FIG. 2 is a dynamically reconfigurable unit, capable of performing simple arithmetic and logical operations at word level. This component consists of a plurality of registers (preferably 4), a logical and arithmetic unit (ALU: "Arithmetic and Logic Unit”) including a multiplier and a state machine.
  • ALU Arimetic and Logic Unit

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The invention relates to a logical calculation architecture, comprising reconfigurable logical elements for carrying out calculations on collections of bits (bit words). Said reconfigurable elements can be programmed in several modes: by a central processor which manages the global configuration of the architecture, or by a local controller which has received a set of instructions from said central processor and which autonomously reconfigures the logical element to which it is connected according to said set of instructions.

Description

ARCHITECTURE DE CALCUL LOGIQUE COMPRENANT PLUSIEURS MODES LOGICAL CALCULATION ARCHITECTURE COMPRISING SEVERAL MODES
DE CONFIGURATIONCONFIGURATION
La présente invention se rapporte au domaine de l'électronique programmable. L'un des grands enjeux de ce domaine est d'utiliser le plus efficacement possible le temps et la place disponible. Pour cela, les développements ont cherché à fournir des solutions reconfigurables dynamiquement, c'est-à-dire sans arrêter les calculs. Pour cela, l'idée la plus simple est de configurer une partie de l'architecture quand une autre partie indépendante est en train de calculer.The present invention relates to the field of programmable electronics. One of the main challenges in this area is to make the most efficient use of the time and space available. For this, developments have sought to provide dynamically reconfigurable solutions, that is to say without stopping the calculations. For this, the simplest idea is to configure a part of the architecture when another independent part is currently calculating.
La présente invention se rapporte plus particulièrement à la conception de modes de configuration multi-niveaux, c'est-à-dire, dans une architecture comprenant un grand nombre de composants programmables la coexistence de deux modes de configuration desdits composants : un mode global pour configurer toute l'architecture et un mode local pour configurer un petit sous-ensemble de composants.The present invention relates more particularly to the design of multi-level configuration modes, that is to say, in an architecture comprising a large number of programmable components the coexistence of two modes of configuration of said components: a global mode for configure the whole architecture and a local mode to configure a small subset of components.
L'art antérieur connaît déjà par le brevet américain N° US6023742 une architecture de calcul configurable dont les fonctionnalités sont contrôlées par une combinaison de contrôles statiques et dynamiques. Le contrôle statique est une configuration contenue dans une mémoire et les contrôles dynamiques sont des signaux envoyés par un contrôleur et interprétées par un chemin de contrôle qui configure les unités logiques en fonction de ces instructions. Ce document de l'art antérieur propose une architecture supportant deux niveaux de configuration : local et global. Cependant, cette architecture n'est pas configurée pour des éléments logiques travaillant au niveau mot (sur des octets par exemple). La présente invention entend remédier aux inconvénients de l'art antérieur en proposant une architecture de composants logiques configurables comprenant plusieurs modes de configuration et utilisant des composants de calcul logique au niveau mot.The prior art already knows by American patent N ° US6023742 a configurable calculation architecture whose functionalities are controlled by a combination of static and dynamic controls. Static control is a configuration contained in a memory and dynamic controls are signals sent by a controller and interpreted by a control path which configures the logical units according to these instructions. This prior art document proposes an architecture supporting two configuration levels: local and global. However, this architecture is not configured for logical elements working at the word level (on bytes for example). The present invention intends to remedy the drawbacks of the prior art by proposing an architecture of configurable logic components comprising several configuration modes and using logic computation components at word level.
Pour ce faire, la présente invention est du type décrit ci-dessus et elle est remarquable, dans son acception la plus large, en ce qu'elle concerne une architecture de calcul logique comportant : - une pluralité de composants de calcul configurables ; une pluralité de composants d'interconnexion ; un premier ensemble de signaux destinés à configurer l'architecture, c'est-à-dire les connexions entre lesdits composants de calcul et lesdits composants d'interconnexion ; un processeur qui génère ledit premier ensemble de signaux de configuration ; caractérisée en ce qu'elle comprend en outre : une pluralité de composants de contrôle configurables, chaque composant de contrôle étant relié à un desdits composants de calcul et lesdits composants de contrôle étant capables de générer au moins une instruction de calcul à destination desdits composants de calcul ; un deuxième ensemble de signaux destinés à configurer lesdits composants de contrôle.To do this, the present invention is of the type described above and it is remarkable, in its broadest sense, in that it relates to a logic calculation architecture comprising: - a plurality of configurable calculation components; a plurality of interconnection components; a first set of signals intended to configure the architecture, that is to say the connections between said computation components and said interconnection components; a processor which generates said first set of configuration signals; characterized in that it further comprises: a plurality of configurable control components, each control component being connected to one of said calculation components and said control components being capable of generating at least one calculation instruction intended for said components of calculation; a second set of signals intended to configure said control components.
De préférence, lesdits composants de calcul réalisent des calculs sur des ensembles de données, chaque ensemble comprenant une pluralité de bits .Preferably, said calculation components perform calculations on sets of data, each set comprising a plurality of bits.
Avantageusement, lesdits composants de contrôle sont reliés audit processeur.Advantageously, said control components are connected to said processor.
On comprendra mieux l'invention à l'aide de la description, faite ci-après à titre purement explicatif, d'un mode de réalisation de l'invention, en référence aux figures annexées : la figure 1 illustre un ensemble « unité de calcul — unité de contrôle » ; la figure 2 illustre une unité de calcul logique ; Une architecture de calcul logique configurable comprend deux couches : une couche opérative comprenant un réseau d'unités de calcul et de routage, qui réalise les calculs logiques sur des données fournies par un élément extérieur ; une couche de configuration permettant d'une part d'arranger lesdites unités de calcul et de routage afin d'organiser le sens de circulation des données et d'autre part de configurer lesdites unités de calcul pour que celles-ci réalisent un calcul prédéfini.The invention will be better understood with the aid of the description, given below for purely explanatory purposes, of an embodiment of the invention, with reference to the appended figures: FIG. 1 illustrates a “calculation unit - control unit” assembly; FIG. 2 illustrates a logical calculation unit; A configurable logical calculation architecture comprises two layers: an operational layer comprising a network of calculation and routing units, which performs the logical calculations on data supplied by an external element; a configuration layer making it possible, on the one hand, to arrange said calculation and routing units in order to organize the direction of data flow and, on the other hand, to configure said calculation units so that they perform a predefined calculation.
Dans une réalisation de cette architecture, la couche de configuration envoie des informations de configuration directement aux éléments constitutifs des unités de calcul. Si cette architecture comprend un grand nombre d'unités de calcul et de routage, la configuration de la couche opérative peut être longue.In one embodiment of this architecture, the configuration layer sends configuration information directly to the components of the computing units. If this architecture includes a large number of calculation and routing units, the configuration of the operational layer can be long.
L'architecture selon l'invention permet de reconfigurer les éléments de la couche opérative selon plusieurs modes : un mode dit « global », un mode ditThe architecture according to the invention makes it possible to reconfigure the elements of the operational layer according to several modes: a so-called “global” mode, a so-called mode
« local » et un mode dit « hybride » . La reconfiguration selon chaque mode est dynamique."Local" and a mode called "hybrid". The reconfiguration according to each mode is dynamic.
L'architecture mise en œuvre pour le mode « global » comporte une couche opérative, une couche de configuration et un processeur spécifique aux opérations de configuration appelé « contrôleur de configuration » . Les couches de configuration et opérative sont divisées en groupes, un groupe de la couche opérative étant configuré par un groupe de la couche de configuration. Chaque groupe de la couche opérative comprend une pluralité d'éléments logiques configurables. Un groupe entier de la couche opérative est reconfigurable à chaque cycle d'horloge. Pendant qu'un calcul est réalisé par un premier groupe de la couche opérative, le contrôleur de configuration modifie la configuration d'un groupe de la couche de configuration correspondant à un deuxième groupe de la couche opérative. Au coup d'horloge suivant, le deuxième groupe de la couche opérative est reconfiguré en fonction du groupe de la couche de configuration correspondante. De plus, la présence d'un processeur dédié à la gestion de la configuration autorise la gestion de la configuration conditionnelle : les résultats calculés par les éléments de la couche opérative peuvent influer sur la configuration de l'architecture. Pour cela, l'architecture met en place un bus de communication entre la couche opérative et le contrôleur de configuration.The architecture implemented for the “global” mode comprises an operational layer, a configuration layer and a processor specific to the configuration operations called “configuration controller”. The configuration and operational layers are divided into groups, a group of the operational layer being configured by a group of the configuration layer. Each group of the operational layer includes a plurality of configurable logic elements. An entire group of the operational layer is reconfigurable at each clock cycle. While a calculation is carried out by a first group of the operational layer, the configuration controller modifies the configuration of a group of the configuration layer corresponding to a second group of the operational layer. At the next clock stroke, the second group of the operational layer is reconfigured according to the group of the corresponding configuration layer. In addition, the presence of a processor dedicated to configuration management allows management of the conditional configuration: the results calculated by the elements of the operational layer can influence the configuration of the architecture. For this, the architecture sets up a communication bus between the operational layer and the configuration controller.
De plus, l'architecture selon l'invention concerne la mise en œuvre d'un mode de configuration « local ». L'architecture selon l'invention propose d'ajouter des unités dites de contrôle aux unités de calcul. Ces unités de contrôle comprennent un séquenceur d'au moins une instruction (et de préférence 8) et une machine d'état finie qui permet de connaître l'état de l'unité de contrôle à tout instant. La couche de configuration envoie à l'unité de contrôle une information comprenant les instructions de contrôle de l'unité de calcul. L'ensemble de ces instructions forme un microprogramme. Ensuite, le séquenceur commande l'envoi du microprogramme à l'unité de calcul. L'unité de calcul réalise ainsi une suite d'instructions nécessitant des configurations différentes sans faire appel au contrôleur de configuration.In addition, the architecture according to the invention relates to the implementation of a "local" configuration mode. The architecture according to the invention proposes adding so-called control units to the calculation units. These control units include a sequencer of at least one instruction (and preferably 8) and a finite state machine which makes it possible to know the state of the control unit at any time. The configuration layer sends information to the control unit comprising the control instructions for the calculation unit. All of these instructions form a firmware. Then, the sequencer orders the sending of the firmware to the computing unit. The calculation unit thus carries out a series of instructions requiring different configurations without calling on the configuration controller.
Un ensemble « unité de calcul — unité de contrôle » est illustré figure 1. L'unité de calcul (1) est reliée à au moins un flux de données d'entrée (3) et à au moins un flux de données de sortie (4). Elle est de plus reliée à l'unité de contrôle (2) par la liaison (5). L'unité de contrôle (2) est composée d'un démultiplexeur (21), d'un contrôleur de mode (22), d'un module de chargement (23), d'un ensemble de registres (24) et d'un module de sortie (25). Selon le mode de configuration de l'architecture, le contrôleur de mode (22) ordonne au démultiplexeur (21) de router le signal de configuration entrant : en mode global, c'est-à-dire où l'unité de calcul (1) est directement configurée par la couche de configuration, le signal est transféré directement du démultiplexeur (21) au module de sortie (25) par la liaison (26). Le module de sortie (25) transmet l'information de configuration à l'unité de calcul (1) par la liaison (5) ; en mode local, c'est-à-dire où l'unité de calcul (1) est configurée par l'unité de contrôle (2), le démultiplexeur (21) transmet l'information de configuration au module de chargement (23) qui télécharge alors le microprogramme dans l'ensemble de registres (24). Une fois chargé et sous commande d'une instruction le spécifiant, le microprogramme est exécuté par l'unité de contrôle.A “calculation unit - control unit” assembly is illustrated in FIG. 1. The calculation unit (1) is connected to at least one input data stream (3) and to at least one output data stream (4). It is also connected to the control unit (2) by the link (5). The control unit (2) is composed of a demultiplexer (21), a mode controller (22), a loading module (23), a set of registers (24) and an output module (25). According to the configuration mode of the architecture, the mode controller (22) orders the demultiplexer (21) to route the incoming configuration signal: in global mode, that is to say where the calculation unit (1 ) is directly configured by the configuration layer, the signal is transferred directly from the demultiplexer (21) to the output module (25) by the link (26). The output module (25) transmits the configuration information to the calculation unit (1) by the link (5); in local mode, that is to say where the calculation unit (1) is configured by the control unit (2), the demultiplexer (21) transmits the configuration information to the loading module (23) which then downloads the firmware into the set of registers (24). Once loaded and under the command of an instruction specifying it, the firmware is executed by the control unit.
L'exécution du microprogramme peut suivre deux procédures : la première procédure consiste en l'exécution des instructions stockées dans les registres de l'unité de contrôle une seule fois ; la seconde procédure consiste en l'exécution des instructions en boucle, c'est-à-dire jusqu'à l'arrêt de l'exécution par le contrôleur de configuration.The execution of the firmware can follow two procedures: the first procedure consists of the execution of the instructions stored in the registers of the control unit only once; the second procedure consists in the execution of the instructions in a loop, that is to say until the execution is stopped by the configuration controller.
Un registre supplémentaire est présent dans l'unité de calcul, ledit registre supplémentaire contenant l'adresse de fin du microprogramme. Enfin , dans un autre mode de réalisation de l'architecture, certains éléments de calcul logique de l'architecture sont configurés de manière « globale » tandis que d'autres éléments logiques sont configurés de manière « locale » .An additional register is present in the calculation unit, said additional register containing the end address of the firmware. Finally, in another embodiment of the architecture, certain elements of logical calculation of the architecture are configured in a "global" manner while other logical elements are configured in a "local" manner.
Cette architecture est de préférence réalisée avec une unité de calcul qui opère sur des « mots » de bits, c'est-à-dire des ensembles de bits. Les calculs sont plus difficiles à programmer dans l'unité de calcul mais un plus grand nombre de bits sont traités à chaque coup d'horloge, ce qui accélère le processus de calcul. Si on utilise une architecture de calcul par mot, la complexité des calculs mis en œuvre rend la configuration plus difficile. L'utilisation d'une architecture selon l'invention permet de réduire la difficulté de configuration de l'architecture.This architecture is preferably carried out with a calculation unit which operates on “words” of bits, that is to say sets of bits. The calculations are more difficult to program in the calculation unit but a greater number of bits are processed with each clock stroke, which accelerates the calculation process. If a word-by-word calculation architecture is used, the complexity of the calculations implemented makes the configuration more difficult. The use of an architecture according to the invention makes it possible to reduce the difficulty of configuring the architecture.
Une unité de calcul logique est illustrée figure 2. L'unité de calcul logique illustrée figure 2 est unité reconfigurable dynamiquement, apte à effectuer des opérations arithmétiques et logiques simples au niveau mot. Ce composant est constitué d'une pluralité de registres (de préférence 4), d'une unité logique et arithmétique (ALU : « Arithmetic and Logic Unit » ) incluant un multiplieur et d'une machine d'état.A logical calculation unit is illustrated in FIG. 2. The logical calculation unit illustrated in FIG. 2 is a dynamically reconfigurable unit, capable of performing simple arithmetic and logical operations at word level. This component consists of a plurality of registers (preferably 4), a logical and arithmetic unit (ALU: "Arithmetic and Logic Unit") including a multiplier and a state machine.
L'invention est décrite dans ce qui précède à titre d'exemple. Il est entendu que l'homme du métier est à même de réaliser différentes variantes de l'invention sans pour autant sortir du cadre du brevet. The invention is described in the foregoing by way of example. It is understood that a person skilled in the art is able to carry out different variants of the invention without going beyond the scope of the patent.

Claims

REVENDICATIONS
1. Architecture de calcul logique comportant : - une pluralité de composants de calcul configurables ; une pluralité de composants d'interconnexion ; un premier ensemble de signaux destinés à configurer l'architecture, c'est-à-dire les connexions entre lesdits composants de calcul et lesdits composants d'interconnexion ; un processeur qui génère ledit premier ensemble de signaux de configuration ; caractérisée en ce qu'elle comprend en outre : une pluralité de composants de contrôle configurables, chaque composant de contrôle étant relié à un desdits composants de calcul et lesdits composants de contrôle étant capables de générer au moins une instruction de calcul à destination desdits composants de calcul ; un deuxième ensemble de signaux destinés à configurer lesdits composants de contrôle.1. Logical calculation architecture comprising: - a plurality of configurable calculation components; a plurality of interconnection components; a first set of signals intended to configure the architecture, that is to say the connections between said computation components and said interconnection components; a processor which generates said first set of configuration signals; characterized in that it further comprises: a plurality of configurable control components, each control component being connected to one of said calculation components and said control components being capable of generating at least one calculation instruction intended for said components of calculation; a second set of signals intended to configure said control components.
2. Architecture de calcul logique selon la revendication 1, caractérisée en ce que lesdits composants de calcul réalisent des calculs sur des ensembles de données, chaque ensemble comprenant une pluralité de bits.2. Logical calculation architecture according to claim 1, characterized in that said calculation components perform calculations on sets of data, each set comprising a plurality of bits.
3. Architecture de calcul logique selon la revendication 1 ou la revendication 2, caractérisée en ce que lesdits composants de contrôle sont reliés audit processeur. 3. Logical calculation architecture according to claim 1 or claim 2, characterized in that said control components are connected to said processor.
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