WO2003061017A1 - Transistor a effet de champ multicanal ultra-lineaire - Google Patents

Transistor a effet de champ multicanal ultra-lineaire Download PDF

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Publication number
WO2003061017A1
WO2003061017A1 PCT/US2002/000558 US0200558W WO03061017A1 WO 2003061017 A1 WO2003061017 A1 WO 2003061017A1 US 0200558 W US0200558 W US 0200558W WO 03061017 A1 WO03061017 A1 WO 03061017A1
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WO
WIPO (PCT)
Prior art keywords
fet
semiconductor
galnas
layers
substrate
Prior art date
Application number
PCT/US2002/000558
Other languages
English (en)
Inventor
Olaleye A. Aina
Harry Stephen Heir
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Epitaxial Technologies, Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epitaxial Technologies, Llc filed Critical Epitaxial Technologies, Llc
Priority to AU2002237791A priority Critical patent/AU2002237791A1/en
Priority to PCT/US2002/000558 priority patent/WO2003061017A1/fr
Publication of WO2003061017A1 publication Critical patent/WO2003061017A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

Definitions

  • This invention relates to field effect transistors, in particular to a multiple channel, ultra-linear field effect transistors.
  • a field effect transistor normally is a square-law device.
  • I D drain current
  • V GS gate-to-source voltage
  • I D K ⁇ V ⁇ s - Vtf
  • N(x) uniform impurity concentration
  • N(x) uniform impurity concentration
  • equation (1) When the substrate concentration is not uniform, equation (1) must be modified, it was revealed by R.A. Pucel in a paper "Profile design for distortion reduction in microwave field-effect transistors" Electronic Letters, vol.14, P.204, 1978, that the I D can be characterized in terms of the non-linear distortion components as:
  • the transconductance must be constant with varying gate voltage Nos-
  • the transconductance is strongly dependent on the electron distribution in the channel of the FET.
  • the design of a linear transistor demands paying attention to carrier distribution.
  • IMR third order intermodulation ratio
  • IMR oc gm ⁇ 2) I gm ⁇ 0) I ( ⁇ 0 (3)
  • ⁇ (x) is the charge distribution in the channel
  • K is the relative dielectric constant
  • ⁇ o is the permittivity of free space
  • q is electronic charge
  • equation (3) is evaluated at the depletion edge boundary.
  • the requirements for a highly linear device is for IMR to be small (close to 0). Therefore, from equation (3), either x 3 N(x) is constant or x 3 tends to infinity. The former occurs when N(x) varies as l/x 3 . Attempts were made to implement such a doping profile to achieve linearity in GaAs MESFET, using ion implantation and epitaxy.
  • the required doping profile with epitaxial method cannot be achieved in uniform semiconductors due to the diffusion of carriers in the material. Such a charge distribution is not easy to achieve in practice. The latter can be achieved with a doping step, a doping spike near the surface. The required type of doping profile cannot be achieved in uniform semiconductors due to the diffusion of electrons in the material
  • An object of this invention is to increase the dynamic range of a FET. Another object of this invention is to obtain a linear dc I D variation as a function of V GS and a constant transconductance variation in the characteristics of a FET over a wide range of V GS - Still another object of this invention is to obtain a sharp impurity gradient in the channel of a FET.
  • multiple channels for a FET Alternate layers of doped and undoped different kinds of semiconductors form heterojunctions in the multiple channels.
  • the heterojunctions confine the electrons in separate thin spikes.
  • a number of spikes of different electron concentrations can result in a sharp overall electron concentration gradient such as 1/x 3 electron concentration profile.
  • Such an electron concentration gradient can result in a linear variation of drain current with gate voltage to obtain a wide dynamic range.
  • Fig. 1(a) shows the substrate structure of a MESFET with multiple channel but without heterojuction
  • Fig. 1(b) shows the gradual electron concentration distribution of the Fig.1(a) structure .
  • Fig.2(a) shows the substrate structure of a HFET with multiple channels with heterojuctions
  • Fig.2(b) shows the abrupt electron concentration distribution of the structure shown in Fig.2(a).
  • Fig.3 shows three electron concentration spikes to simulate a 1/x 3 electron concentration profile.
  • Fig.4 shows the multiple AlAsSb/GalnAs channel HFET structure of the present invention.
  • FIG. 5 energy band diagram of the multiple channel HFET shown in Fig. 4.
  • Fig.6 shows the structure of a multiple AlInAs/GalnAs channel FET.
  • Fig. 7(a) shows the l D ,gm vs V GS characteristics of a multi-channel AlAsSb/GalnAs HFET;
  • Fig. 7(b) shows the Io .
  • Fig. 8 shows the combination of wide/narrow bandgap sandwich structure.
  • Fig. 1 (a) shows the substrate of a typical substrate of MESFET having three successive layers of 5100A of undoped GalnAs, 200A of 2xl0 18 cm “3 of GalnAs, and 20 ⁇ A of undoped GalnAs.
  • the electron concentration after processing spreads out like a skirt as shown in Fig.l(b).
  • the substrate has a heterojunction structure as shown in Fig.2(a) for a heterojunction FET (HFET) having 5100A, or undoped AsAsSb, 200A, of GalnAs and 20 ⁇ A, of AlAsSb, then the electron concentration is confined without a skirt as shown in Fig. 2(b).
  • HFET heterojunction FET
  • Fig.3 shows the use of three different abrupt electron concentrations Nl, N2, N3 to approximate a 1 / x 3 electron concentration profile as shown by the dotted curve.
  • Fig. 4 shows the energy band diagram.
  • Fig.4 shows the basic structure of a multi-channel heterojunction field effect transistor (HFET) of the present invention.
  • the structure has a InP substrate 10.
  • the multiple channel HFET is formed with alternate undoped layers 12, 14, 16, 18 of a first kind of semiconductor (e.g. AlAsSb) and doped layers 13, 15, 17 of a second kind of semiconductor (e.g. GalnAs).
  • the two kinds of different semiconductor material form heterojunctions in the multiple channel.
  • a lower undoped buffer layer of AlInAs is inserted between the substrate 10 and layer 12.
  • Another two buffer layers of undoped AlInAs layer 19 and undoped GaAs layer 20 to cap the multiple channel.
  • the top undoped layers creates a MODET structure with 2-dimensional electron gas so that the conducting channels are removed from the surface.
  • Over the GaAs 20 cap are the source 21, gate 22 and drain 23.
  • the transverse energy band diagram for the multiple channel HFET is shown in Fig.5.
  • the doped layers 12, 14 16 form quantum wells and the undoped layers 11, 13, 15, 17 form barrier layers and confine the dopants (electrons) within their own doped layers without diffusing into a neighboring doped layers.
  • the dopants electrons
  • sharp spikes of high electron concentration as that shown in Fig. 2(b) can be formed and the desirable sharp 1/x 3 impurity profile can be approached.
  • FIG.6 Another multiple channel FET structure is shown in Fig.6 based on AlInAs/GalnAs undoped layers 31, 33, 35, 37 and doped layers 32, 34, 36 over a InP substrate 30.
  • the structure is capped with an undoped layer of GaAs.
  • the undoped cap serves to produce a MODFET structure as in Fig.4.
  • Fig.7(a) shows the I D and gin vs V GS characteristic of the AlAsSb/GalnAs HFET shown in Fig.4.
  • Fig. 7(b) shows the I D and gm vs V GS characteristic of the AlInAs/GalnAs multi-channel HET shown in Fig.6.
  • the I D varies linearly with V GS over a wide range of V GS and the gm is constant over a wide range of
  • the FET structure can be designed to give optimum noise figure parameters, peak gm at 10% Iosat. By proper selection of charge density, peak in gm close to pinch-off can be realized in multi-channel FET.
  • the combination of wide/narrow bandgap sandwich structure of the channel can be extended to other semiconductor.
  • the doped narrow bandgap layer be n or p-type.
  • the doping can be uniform or delta/spike doped.
  • the narrow bandgap can be quantum dot, e.g. InAs quantum dot I n GalnAs channel.
  • the substrate can be Si, GaAs, GaN, SiCInP or other substrates on which the FET heterostructure is transferred by bonding,/lift-off/growth.
  • the combination of the wide/narrow bandgaps are: GaAs/AlGaAs, GaAs/GalnP, GaAS/AlAs, GalnAs/AlGaAs (AlAs, GalnP); GalnAs/AlInAs, GalnAs/AlGaAsSb, GalnAs/AlAsSb, GaAsSb/AlGaAsSb, GalnAs/AlInAsSb, InAs/AlGaAsSb(AlSb, AlAsSb, AlGaSb), InAs/AlGalnSb, InSb/AlInSb, GaN/AlGaN, GalnN/AlGaN, etc.
  • Ultra-linear FET can be extended to IV-IV semiconductor (Si, Ge, Sn, C), II- VI semiconductors (ZnSe, ZnS, CdTe, CdS, etc) or combinations of III-V and IV-/IV (e.g. GaPSi) or IV-IV and II- VI (e.g. ZnS/Si).
  • the layer under the metal gate can be wide bandgap semiconductor or SiO 2 , Si 3 N 4 , Al 2 O 3 , AIN etc.
  • Fig. 4 shows three doped layers and four undoped layers, the number of doped and undoped layer and their distribution (variation) with depth are not limited to these numbers of layers. While the preferred embodiments of the invention have been described, it will be apparent to those skilled in the art that various modifications may be made in the embodiments without departing from the spirit of the present invention. Such modifications are all within the scope of this invention.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

Des couches alternées de différents types de semi-conducteurs dopés et non dopés sont utilisées pour former des canaux multiples dans un TEC. Les différents types de semi-conducteurs forment des hétérojonctions permettant de confiner les électrons dans des pointes fines séparées. Un certain nombre de pointes présentant différentes concentrations d'électrons peuvent donner lieu à un gradient de concentration d'électrons global marqué, tel qu'un profil de concentration d'électrons de 1/x3. Un tel gradient de concentration d'électrons peut donner lieu à une variation linéaire de courant débité avec une tension de grille permettant d'obtenir une large dynamique de mesure.
PCT/US2002/000558 2002-01-11 2002-01-11 Transistor a effet de champ multicanal ultra-lineaire WO2003061017A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2002237791A AU2002237791A1 (en) 2002-01-11 2002-01-11 Ultra-linear multi-channel field effect transistor
PCT/US2002/000558 WO2003061017A1 (fr) 2002-01-11 2002-01-11 Transistor a effet de champ multicanal ultra-lineaire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2002/000558 WO2003061017A1 (fr) 2002-01-11 2002-01-11 Transistor a effet de champ multicanal ultra-lineaire

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633516A (en) * 1994-07-25 1997-05-27 Hitachi, Ltd. Lattice-mismatched crystal structures and semiconductor device using the same
US5663583A (en) * 1995-06-06 1997-09-02 Hughes Aircraft Company Low-noise and power ALGaPSb/GaInAs HEMTs and pseudomorpohic HEMTs on GaAs substrate
US5767539A (en) * 1996-04-05 1998-06-16 Nec Corporation Heterojunction field effect transistor having a InAlAs Schottky barrier layer formed upon an n-InP donor layer
US5856685A (en) * 1995-02-22 1999-01-05 Nec Corporation Heterojunction field effect transistor
US6049097A (en) * 1994-07-25 2000-04-11 Nec Corporation Reliable HEMT with small parasitic resistance
US6121641A (en) * 1996-09-30 2000-09-19 Nec Corporation Compound semiconductor field-effect transistor with improved current flow characteristic

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633516A (en) * 1994-07-25 1997-05-27 Hitachi, Ltd. Lattice-mismatched crystal structures and semiconductor device using the same
US6049097A (en) * 1994-07-25 2000-04-11 Nec Corporation Reliable HEMT with small parasitic resistance
US5856685A (en) * 1995-02-22 1999-01-05 Nec Corporation Heterojunction field effect transistor
US5663583A (en) * 1995-06-06 1997-09-02 Hughes Aircraft Company Low-noise and power ALGaPSb/GaInAs HEMTs and pseudomorpohic HEMTs on GaAs substrate
US5767539A (en) * 1996-04-05 1998-06-16 Nec Corporation Heterojunction field effect transistor having a InAlAs Schottky barrier layer formed upon an n-InP donor layer
US6121641A (en) * 1996-09-30 2000-09-19 Nec Corporation Compound semiconductor field-effect transistor with improved current flow characteristic

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Publication number Publication date
AU2002237791A1 (en) 2003-07-30

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