WO2003060693A3 - Device and method for multiplying or dividing a first operand by a second operand - Google Patents

Device and method for multiplying or dividing a first operand by a second operand Download PDF

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Publication number
WO2003060693A3
WO2003060693A3 PCT/EP2003/000182 EP0300182W WO03060693A3 WO 2003060693 A3 WO2003060693 A3 WO 2003060693A3 EP 0300182 W EP0300182 W EP 0300182W WO 03060693 A3 WO03060693 A3 WO 03060693A3
Authority
WO
WIPO (PCT)
Prior art keywords
operand
coded
multiplying
dividing
algorithm
Prior art date
Application number
PCT/EP2003/000182
Other languages
German (de)
French (fr)
Other versions
WO2003060693A2 (en
Inventor
Berndt Gammel
Franz Klug
Oliver Kniffler
Original Assignee
Infineon Technologies Ag
Berndt Gammel
Franz Klug
Oliver Kniffler
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Berndt Gammel, Franz Klug, Oliver Kniffler filed Critical Infineon Technologies Ag
Priority to AU2003235626A priority Critical patent/AU2003235626A1/en
Publication of WO2003060693A2 publication Critical patent/WO2003060693A2/en
Publication of WO2003060693A3 publication Critical patent/WO2003060693A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G06F2207/7223—Randomisation as countermeasure against side channel attacks
    • G06F2207/7233—Masking, e.g. (A**e)+r mod n
    • G06F2207/7238—Operand masking, i.e. message blinding, e.g. (A+r)**e mod n; k.(P+R)

Abstract

Disclosed are a device and a method for multiplying or dividing a first operand by a second operand. Secure arithmetic units used for dividing and multiplying are provided with a control unit (18) which carries out the bit analyses required for the radix-2 multiplication algorithm, booth-recoding multiplication algorithm, restoring division algorithm, and non-restoring division algorithm in the cryptographic area, using coded bits and coding parameters for coding said bits. Registers (16, 22, 24, 30) in which coded operands are stored and an adder (10) using coded operands to add and producing a coded result can also be used. Such a multiplier/divider operates in the cryptographic area and is less prone to physical and/or indirect attacks.
PCT/EP2003/000182 2002-01-16 2003-01-10 Device and method for multiplying or dividing a first operand by a second operand WO2003060693A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003235626A AU2003235626A1 (en) 2002-01-16 2003-01-10 Device and method for multiplying or dividing a first operand by a second operand

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2002101442 DE10201442C1 (en) 2002-01-16 2002-01-16 Device and method for multiplying or dividing a first operand by or by a second operand
DE10201442.6 2002-01-16

Publications (2)

Publication Number Publication Date
WO2003060693A2 WO2003060693A2 (en) 2003-07-24
WO2003060693A3 true WO2003060693A3 (en) 2004-01-15

Family

ID=7712269

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2003/000182 WO2003060693A2 (en) 2002-01-16 2003-01-10 Device and method for multiplying or dividing a first operand by a second operand

Country Status (4)

Country Link
AU (1) AU2003235626A1 (en)
DE (1) DE10201442C1 (en)
TW (1) TW200302430A (en)
WO (1) WO2003060693A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5479512A (en) * 1991-06-07 1995-12-26 Security Dynamics Technologies, Inc. Method and apparatus for performing concryption
WO2001040950A2 (en) * 1999-12-02 2001-06-07 Infineon Technologies Ag Microprocessor arrangement having an encoding function
EP1118941A1 (en) * 2000-01-18 2001-07-25 Infineon Technologies AG Microprocessor system and arrangement in order to operate a microprocessor system
WO2001054083A1 (en) * 2000-01-18 2001-07-26 Infineon Technologies Ag Microprocessor system with encoding

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3276444B2 (en) * 1993-03-22 2002-04-22 三菱電機株式会社 Division circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5479512A (en) * 1991-06-07 1995-12-26 Security Dynamics Technologies, Inc. Method and apparatus for performing concryption
WO2001040950A2 (en) * 1999-12-02 2001-06-07 Infineon Technologies Ag Microprocessor arrangement having an encoding function
EP1118941A1 (en) * 2000-01-18 2001-07-25 Infineon Technologies AG Microprocessor system and arrangement in order to operate a microprocessor system
WO2001054083A1 (en) * 2000-01-18 2001-07-26 Infineon Technologies Ag Microprocessor system with encoding

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BEHROOZ PARHAMI: "Computer Arithmetic", 2000, OXFORD UNIVERSITY PRESS, NEW YORK OXFORD, XP002247738 *
BEHROOZ PARHAMI: "Computer Arithmetic", 2000, OXFORD UNIVERSITY PRESS, NEW YORK OXFORD, XP002247739 *
WWW.ARCHIVE.ORG, 4 December 2000 (2000-12-04), pages 1 - 8, XP002247737, Retrieved from the Internet <URL:www.logosec.de/frame.htm> [retrieved on 20030715] *

Also Published As

Publication number Publication date
AU2003235626A1 (en) 2003-07-30
AU2003235626A8 (en) 2003-07-30
WO2003060693A2 (en) 2003-07-24
TW200302430A (en) 2003-08-01
DE10201442C1 (en) 2003-07-31

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