WO2003049520A1 - Acheminement de signaux et attribution de blindage utilisant un blindage preferentiel - Google Patents

Acheminement de signaux et attribution de blindage utilisant un blindage preferentiel Download PDF

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Publication number
WO2003049520A1
WO2003049520A1 PCT/US2002/037889 US0237889W WO03049520A1 WO 2003049520 A1 WO2003049520 A1 WO 2003049520A1 US 0237889 W US0237889 W US 0237889W WO 03049520 A1 WO03049520 A1 WO 03049520A1
Authority
WO
WIPO (PCT)
Prior art keywords
potential
signal
probability
value
shields
Prior art date
Application number
PCT/US2002/037889
Other languages
English (en)
Inventor
Sudhakar Bobba
Tyler J. Thorp
Original Assignee
Sun Microsystems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/997,435 external-priority patent/US6721936B2/en
Priority claimed from US09/997,918 external-priority patent/US6629306B2/en
Application filed by Sun Microsystems, Inc. filed Critical Sun Microsystems, Inc.
Priority to GB0411813A priority Critical patent/GB2399914B/en
Priority to AU2002365836A priority patent/AU2002365836A1/en
Publication of WO2003049520A1 publication Critical patent/WO2003049520A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0039—Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing

Definitions

  • Implicit decoupling capacitance is provided to the circuit through the use of decoupling capacitors as discussed above.
  • Implicit decoupling capacitance also known in the art as “parasitic capacitance” or “inherent capacitance” is capacitance that is inherent in a circuit. Implicit decoupling capacitance results from the electromagnetic effects between current-carrying wires. Further, implicit decoupling capacitance is a function of the distance between two such wires. Also, the ability to help supplement an attenuating voltage using explicit decoupling capacitors or implicit decoupling capacitance is a function of the potential applied to the decaps.
  • Figure 6 is a multilevel routing channel in accordance with an embodiment of the present invention.
  • an exemplary circuit (140) is also provided with a two-input NAND gate (168) that receives power from the power supply bus (144) and from the ground bus (146) via power supply line (152) and ground line (154).
  • the two-input NAND gate (168) outputs a signal on a signal line, or signal path, (170).
  • the implicit decoupling capacitance is equal to the implicit decoupling capacitance (172) between the signal line (170) and the ground line (150), acting as a first shield, plus the implicit decoupling capacitance (174) between the signal line (170) and the ground line (154), acting as a second shield, while the signal line (170) is high.
  • the implicit decoupling capacitance is essentially zero while the signal line (170) is low. This relationship may be represented as shown in Equation 3:
  • combinational logic (820) and a combinational logic circuit (830) display the location of the combinational logic, but do not show any details about the logic elements within the combinational logic (820) and the combinational logic circuit (830).
  • the combinational logic (820) has three combinational logic outputs (822, 824, 826), and the combinational logic (830) has two combinational logic outputs (832, 834).
  • the combinational logic outputs (822, 824, 826, 832, 834) are routed in the same layer as the layer used to route the power supply bus (844) and the power supply (846).

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Cette invention concerne un procédé de blindage préférentiel d'un signal permettant d'accroître la capacité de découplage implicite. Le signal subit un blindage préférentiel sur la base de l'hypothèse que le signal présente une valeur spécifique pour que le lieux d'acheminement du signal soit déterminé. En outre, le signal subit un blindage préférentiel sur la base de l'hypothèse que le signal présente une valeur spécifique pour que le potentiel de tension auquel le potentiel de blindage va être attribué soit déterminé.
PCT/US2002/037889 2001-11-30 2002-11-27 Acheminement de signaux et attribution de blindage utilisant un blindage preferentiel WO2003049520A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB0411813A GB2399914B (en) 2001-11-30 2002-11-27 Signal routing and shield assignment using preferential shielding
AU2002365836A AU2002365836A1 (en) 2001-11-30 2002-11-27 Signal routing and shield assignment using preferential shielding

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/997,435 US6721936B2 (en) 2001-11-30 2001-11-30 Shield assignment using preferential shields
US09/997,435 2001-11-30
US09/997,918 2001-11-30
US09/997,918 US6629306B2 (en) 2001-11-30 2001-11-30 Signal routing based approach for increasing decoupling capacitance using preferential shielding

Publications (1)

Publication Number Publication Date
WO2003049520A1 true WO2003049520A1 (fr) 2003-06-12

Family

ID=27130674

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/037889 WO2003049520A1 (fr) 2001-11-30 2002-11-27 Acheminement de signaux et attribution de blindage utilisant un blindage preferentiel

Country Status (3)

Country Link
AU (1) AU2002365836A1 (fr)
GB (1) GB2399914B (fr)
WO (1) WO2003049520A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027321A (en) * 1989-11-21 1991-06-25 Intel Corporation Apparatus and method for improved reading/programming of virtual ground EPROM arrays
EP0575892A1 (fr) * 1992-06-17 1993-12-29 Mitsubishi Denki Kabushiki Kaisha Module semi-conducteur de puissance
US6229095B1 (en) * 1998-10-01 2001-05-08 Nec Corporation Multilayer wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027321A (en) * 1989-11-21 1991-06-25 Intel Corporation Apparatus and method for improved reading/programming of virtual ground EPROM arrays
EP0575892A1 (fr) * 1992-06-17 1993-12-29 Mitsubishi Denki Kabushiki Kaisha Module semi-conducteur de puissance
US6229095B1 (en) * 1998-10-01 2001-05-08 Nec Corporation Multilayer wiring board

Also Published As

Publication number Publication date
GB0411813D0 (en) 2004-06-30
GB2399914B (en) 2005-03-02
AU2002365836A1 (en) 2003-06-17
GB2399914A (en) 2004-09-29

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