WO2003042836A1 - Computer and memory control method - Google Patents

Computer and memory control method Download PDF

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Publication number
WO2003042836A1
WO2003042836A1 PCT/JP2001/010035 JP0110035W WO03042836A1 WO 2003042836 A1 WO2003042836 A1 WO 2003042836A1 JP 0110035 W JP0110035 W JP 0110035W WO 03042836 A1 WO03042836 A1 WO 03042836A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
bank conflict
memory bank
computer
control method
Prior art date
Application number
PCT/JP2001/010035
Other languages
French (fr)
Japanese (ja)
Inventor
Satoshi Onodera
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2001/010035 priority Critical patent/WO2003042836A1/en
Publication of WO2003042836A1 publication Critical patent/WO2003042836A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Multi Processors (AREA)

Abstract

When a memory bank conflict where the same bank is accessed continuously is detected by a memory bank conflict decision unit, a memory controller sequentially accesses different banks in unused areas of a main memory and copies data that has caused the memory bank conflict. For second and subsequent accesses detected by a unit for detecting a plurality of times of references of data, the memory controller controls the operation to access copied areas thus avoiding memory bank conflict.
PCT/JP2001/010035 2001-11-16 2001-11-16 Computer and memory control method WO2003042836A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/010035 WO2003042836A1 (en) 2001-11-16 2001-11-16 Computer and memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/010035 WO2003042836A1 (en) 2001-11-16 2001-11-16 Computer and memory control method

Publications (1)

Publication Number Publication Date
WO2003042836A1 true WO2003042836A1 (en) 2003-05-22

Family

ID=11737944

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2001/010035 WO2003042836A1 (en) 2001-11-16 2001-11-16 Computer and memory control method

Country Status (1)

Country Link
WO (1) WO2003042836A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2388216A (en) * 2001-12-21 2003-11-05 Agere Systems Inc Multi-bank scheduling to improve performance on tree access in a dram based RAM subsystem
WO2005008674A2 (en) * 2003-07-16 2005-01-27 Infineon Technologies Ag Semiconductor memory having a short effective word-line cycle time and data readout method for said semi-conductor memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188762A (en) * 1983-04-08 1984-10-26 Mitsubishi Electric Corp Interleave storage controller
JPS62120552A (en) * 1985-11-20 1987-06-01 Fujitsu Ltd High-speed access system for main memory
JPH04293135A (en) * 1991-03-20 1992-10-16 Yokogawa Hewlett Packard Ltd Memory access system
WO1998018084A1 (en) * 1996-10-18 1998-04-30 Fujitsu Limited Device and method for accelerating memory access speed

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188762A (en) * 1983-04-08 1984-10-26 Mitsubishi Electric Corp Interleave storage controller
JPS62120552A (en) * 1985-11-20 1987-06-01 Fujitsu Ltd High-speed access system for main memory
JPH04293135A (en) * 1991-03-20 1992-10-16 Yokogawa Hewlett Packard Ltd Memory access system
WO1998018084A1 (en) * 1996-10-18 1998-04-30 Fujitsu Limited Device and method for accelerating memory access speed

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2388216A (en) * 2001-12-21 2003-11-05 Agere Systems Inc Multi-bank scheduling to improve performance on tree access in a dram based RAM subsystem
US6839797B2 (en) 2001-12-21 2005-01-04 Agere Systems, Inc. Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem
GB2388216B (en) * 2001-12-21 2005-04-20 Agere Systems Inc Multi-bank scheduling to improve performance on tree accesses in a dram based random access memory subsystem
WO2005008674A2 (en) * 2003-07-16 2005-01-27 Infineon Technologies Ag Semiconductor memory having a short effective word-line cycle time and data readout method for said semi-conductor memory
WO2005008674A3 (en) * 2003-07-16 2005-04-28 Infineon Technologies Ag Semiconductor memory having a short effective word-line cycle time and data readout method for said semi-conductor memory
US8635393B2 (en) 2003-07-16 2014-01-21 Qimonda Ag Semiconductor memory having a short effective word line cycle time and method for reading data from a semiconductor memory of this type

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