WO2003039055A1

WO2003039055A1 - Method and device for representing the initial base of an encoder in the signal space of a qam or psk modulation

Info

Publication number: WO2003039055A1
Application number: PCT/DE2001/004105
Authority: WO
Inventors: Bernhard Raaf; Martin DÖTTLING; Jürgen MICHEL
Original assignee: Siemens Aktiengesellschaft
Priority date: 2001-10-15
Filing date: 2001-10-30
Publication date: 2003-05-08
Also published as: CN101072082A

Abstract

In accordance with the invention, the bits to be transmitted in a communication system are subjected to a channel coding and transformed into systematic bits (S) and into parity bits (P1, P2), then they are represented for transmission on modulation symbols, for example of 16QAM modulator (5). The systematic bits (S) are represented on binary positions of the modulation symbols (13) with high reliability, and, if the number of binary positions having high reliability is not sufficient, they are represented on binary positions of less reliability, while the parity bits (P1, P2) are represented on the remaining binary positions, with less reliability, after corresponding execution of a bit rate adaptation (15, 16; 21, 22) relative to the parity bits (P1, P2).

Description

METHOD AND DEVICE FOR IMAGING THE BASE OF AN ENCODER ON THE SIGNAL SPACE OF A QAM OR PSK MODULATION

description

Method for adapting the bit rate of a bit stream to be transmitted in a communication system and corresponding communication device

The present invention relates to a method for adapting the bit rate of a bit stream to be transmitted in a communication system, in particular a mobile radio system, and a corresponding communication device.

Mobile radio technology is developing rapidly. Work is currently underway to standardize the so-called UMTS mobile radio standards ("Universal Mobile Telecommunications System") for mobile radio devices of the third mobile radio generation.

In this case, a rate adaptation ("rate matching") is provided on the transmitter side in order to adapt the bit rate of the bit stream to be transmitted to the respectively possible transmission rate, wherein bits are either removed from the bit stream or multiplied, in particular doubled, in the bit stream , The removal of bits is referred to as "puncturing" and the multiplication as repetition ("repetition").

A possible structure of the transmission path of a mobile radio transmitter, in which such a bit rate adaptation is provided, is shown by way of example in FIG. 1.

A data stream consisting of several data or transport blocks is first expanded by a device 1 by so-called “tail bits”. The bit stream thus output by the device 1 is fed to a channel encoder 2, where redundant bits are added to the information bits depending on the type of channel coding used in each case, so that in most coding schemes so-called systematic bits on the one hand and parity bits ("parity Depending on the code rate of the channel encoder 2, more or less systematic bits or parity bits arise. In some coding schemes, the parity bits have a lower priority or importance for the decoding of the corresponding message than the systematic bits Channel encoder 2 can be a so-called turbo encoder, for example, in UMTS mobile radio systems, which is usually constructed from interleaved convolutional encoders.

The channel encoder 2 is followed by a bit rate adaptation device 3 which punctures and / or repeats the bits supplied to it in accordance with a specific bit rate adaptation algorithm. Due to the lower importance or priority of the parity bits, the parity bits are conventionally preferably punctured for bit rate adaptation, since these are less important than the systematic bits for successful decoding of the respective message on the receiver side.

The bit stream output by the bit rate adaptation device 3 is scrambled with the aid of an interleaver 4, so that the individual bits are rearranged in time according to a specific interleaving law a. The result of the interleaver 4 is that the priorities of the individual bits are no longer known in the bit stream output by it.

The bits output by the interleaver 4 are fed to a modulator 5 which, depending on the type of modulation used in each case, determines several of these bits

Maps symbols of a multidimensional symbol space and transmits the symbols to a receiver. In QPSK modulation ("Quadrature Phase Shift Keying"), two bits are each divided into four symbols evenly distributed in a two-dimensional symbol space, while in one

8PSK modulation three bits, with 16QAM modulation ("quadrature amplitude modulation") four bits and with a 64QAM Modulation six bits can be assigned to a symbol in a two-dimensional symbol space.

The symbols generated by the modulator 5 are transmitted in the form of a real and imaginary part, which clearly describe the position of the respective symbol in the two-dimensional symbol space. A demultiplexer 7 connected downstream of the modulator 5 distributes the symbols over possibly several channels, where the symbol sequence is coded with different channeling or spreading codes Wi ... W _M , which is shown in FIG. 1 in the form of corresponding multipliers 8. The sum signal of these differently spread symbol sequences is generated and output via a summer 9.

In addition, according to FIG. 1, a control unit 6 is provided with the abbreviation AMCS ("Adaptive Modulation and Coding Scheines"), which controls the modulation alphabet of the modulator 5 to be used as well as the coding schemes and code rates of the channel encoder 2 and the division into the individual channelization codes sets the demultiplexer 7.

The transmission path structure shown in FIG. 1 corresponds, for example, to the structure of the physical layer provided for a so-called HSDPA connection ("High Speed Downlink Packet Access") in UMTS mobile radio systems. This is a packet-switched connection type, and what is known as an ARQ process ("Automatic Repeat Request") can also be used, the receiver (for example a mobile station) of a data packet, if this data packet is incorrectly received, from retransmitting it Sender (for example a base station) requests, whereupon the transmitter sends a repetition of the originally sent data packet to the receiver. One problem with the function of the modulator 5 shown in FIG. 1 is that, due to the type of modulation chosen in each case, not all bits supplied to the modulator 5 can be transmitted with equal certainty, ie the reliability of the individual bits fluctuates, for example, depending on the position of the Symbols in the symbol space, on which the individual bits are mapped.

This will be explained in more detail below with reference to FIG. 3A, the signal constellation or the two-dimensional symbol space 12 for 16QAM modulation being shown by way of example in FIG. 3A. In this case, four bits ii, qi, i ₂ and q ₂ are each assigned to a symbol 13 of the two-dimensional symbol space 12 shown in FIG. 3A, the type of mapping of the individual bits onto the symbols 13 being referred to as "gray mapping" , In FIG. 3A, those columns or rows of symbols are marked with a dash which correspond to a bit ii or i ₂ or qi or q ₂ with the value "1". 3A shows that, for example, the symbols with i ₂ = "1" each have eight neighbors with the value i ₂ = "0", while, for example, symbols with ii = "1" only have four potential neighbors with ii = "0" and therefore only four direct decision thresholds. As a result, the symbols with bits ii = "1" are better protected against incorrect transmission than the symbols with i ₂ = "1". The same also applies, for example, to the symbols qi = "1", which have greater reliability than symbols with q ₂ = "1". Basically, it can thus be said that in the signal constellation shown in FIG. 3A, bits ii and qi have greater reliability with regard to an error-free determination of the information content than bits i ₂ and q, respectively.

In FIG. 3B, the signal constellation or the two-dimensional symbol space 12 for 64QAM modulation is shown by way of example. There are six bits each ii, qi i- ₂ <32, i ₃ and q _{4 are assigned} in the order given to a symbol 13 of the two-dimensional symbol space 12 shown in FIG. 3A. In the case of 64QAM modulation, the individual symbols 13 can be assigned to three different reliability classes for the reasons explained above. All symbols with ii = "1" or qi = "1" have a high degree of reliability during transmission. All symbols with i ₂ = "1" or q ₂ = "1", on the other hand, have medium reliability and all symbols with i ₃ = "1" or q ₃ = "1" have low reliability.

The problem thus arises in the transmission path structure shown in FIG. 1 that, on the one hand, bits with different priority or importance are provided for decoding the respective message and, on the other hand, the modulator 5 cannot transmit all bits equally securely or map them to equally reliable symbols, which are then transmitted in the form of their real part Re or their in-phase component and their imaginary part Im or their quadrature component, so that bits with high priority are possibly mapped and transmitted on symbols or bit positions of the symbols with low reliability , which affects data transmission security and data transmission quality.

In this regard, it has already been proposed to carry out a specific assignment of the bits to the symbols 13 of the symbol space 12 for each transmission attempt of a data block, so that the reliability of the individual bits can be harmonized if a clever allocation rule is used after several transmissions. However, this only applies if a data block is repeated several times. The transmission security during the first transmission of a data block is not improved by this proposal.

A further proposal is shown in FIG. 2, whereby after the channel encoder or turbo encoder 2, which outputs the bits separately according to systematic bits S and parity bits P, separate processing of the systematic bits and parity bits is performed. Therefore, in particular, two separate interleavers 4a and 4b are provided, with a device 10 having a parallel / serial conversion to only one bit stream in such a way that the most intelligent possible assignment of the bits with different priorities or importance to the bit positions with different reliability can be done within the individual symbols. The bits with the highest priority, ie the systematic bits S, are preferably distributed to the bit positions with the highest reliability and the bits with the lowest priority, ie the parity bits, to the bit positions with the lowest reliability.

With turbo coding with a code rate of 1/2, for example, and when using 1βQAM modulation, the mapping of the systematic bits and parity bits to be transmitted per coded data block works out exactly, since the number of positions to be filled is highly reliable and of low reliability is the same size as the two-dimensional symbol space. Since there are often more bits with the highest priority than bit positions with the highest reliability, an optimal solution is usually not possible. In particular, a solution is desirable in which the code rate (taking into account the channel coding and rate adaptation carried out) can assume different values.

The present invention is therefore based on the object of providing a method for adapting the bit rate of a bit stream to be transmitted in a communication system and a communication device, the data transmission quality and data transmission security being able to be improved with as little effort as possible regardless of the code rate selected in each case. This object is achieved according to the invention by a method with the features of claim 1 or a communication device with the features of claim 20. The subclaims each define preferred and advantageous embodiments of the present invention.

According to the invention, the systematic bits are mapped to bit positions of the modulation symbols with a high degree of reliability and, if the number of bit positions with the high degree of reliability is not sufficient, to bit positions with a lower degree of reliability. The parity bits, on the other hand, are mapped to the remaining bit positions with the lower reliability after a corresponding bit rate adjustment has been carried out. The bit positions with the lower

Systematic bits to be mapped, preferably selected as uniformly as possible from all systematic bits to be transmitted.

The principle described above can also be applied to more than two different reliabilities, such as occur with 64QAM modulation, for example. The systematic bits can be mapped, for example, to the bit positions with a high reliability and, if the number of bit positions with the high reliability is not sufficient, to the bit positions with a medium reliability, while the parity bits to the bit positions with a low reliability and the remaining bit positions are mapped with the average reliability. Likewise, the reliabilities can be divided into a first group of reliabilities and a second group of reliabilities, the reliabilities contained in the first group being higher than the reliabilities contained in the second group, so that the method described above applies accordingly to the two groups assigned bit positions can be applied. In order to implement the invention, corresponding exemplary embodiments of the rate adaptation device according to the invention, which processes systematic bits and parity bits of the channel encoder in accordance with the previously described method, are proposed for different effective code rates.

The bits to be mapped to the bit positions with the high reliability and the bit positions with the low or lower reliability are fed to separate interleavers, which are preferably designed differently in order to achieve the best possible distribution of the bits to be transmitted. Corresponding exemplary embodiments are also described in detail in this regard. It is expressly pointed out that the various configurations of the interleaver are in principle independent of the previously described inventive concept and can of course also be used in communication devices in which the above inventive concept has not been implemented.

The present invention is preferably suitable for use in mobile radio systems, in particular for use in UMTS mobile radio systems. Of course, however, the present invention is not limited to this preferred area of application, but can generally be used in any communication system where systematic bits and parity bits are to be transmitted. In addition, not only the transmitter side, but also the receiver side is affected by the present invention, since on the receiver side a received signal processed according to the invention must be evaluated.

The present invention is explained in more detail below with reference to the accompanying drawing using preferred exemplary embodiments. FIG. 1 shows a simplified block diagram of a conventional transmission path structure of a mobile radio transmitter,

FIG. 2 shows a simplified block diagram of a further conventional transmission path structure of a mobile radio transmitter,

FIG. 3A and FIG. 3B show the signal constellation for a 16QAM modulation and a 64QAM modulation,

FIG. 4 shows a simplified block diagram of the transmission path structure of a mobile radio transmitter according to a first exemplary embodiment of the present invention,

FIG. 5 shows a simplified block diagram of the transmission path structure of a mobile radio transmitter according to a second exemplary embodiment of the present invention,

FIG. 6 shows a simplified block diagram of the transmission path structure of a mobile radio transmitter according to a third exemplary embodiment of the present invention,

FIG. 7 shows an illustration to clarify the writing of bits into the interleaver shown in FIGS. 4 through 6 according to an embodiment of the present invention

FIG. 8 shows an illustration to illustrate a shift in the writing of bits into the interleaver shown in FIGS. 4 through 6 and a shift in the reading out of the bits therefrom according to a further exemplary embodiment of the present invention,

FIG. 9 shows a representation to explain a procedure for determining optimized column swapping algorithms for the interleaver shown in FIGS. 4 through 6. FIG. 10 shows a block diagram for a rate adjustment algorithm.

FIGS. 11 to 13 show diagrams to illustrate different variants of a rate adjustment algorithm, and

Figure 14 shows a block diagram for a rate adjustment algorithm.

With the help of the present invention, a solution is proposed as to how the systematic bits and parity bits supplied by the respective channel encoder for any code rates on the bit positions of the symbols of the respective modulator, which have different reliabilities, for example a 16QAM, 64QAM or 8PSK modulator, etc. ., are to be reproduced in order to achieve the lowest possible bit error rate based on the information bits to be transmitted. The procedure is as follows:

(a) If possible, all systematic bits are mapped onto symbols or bit positions with high or higher reliability.

(b) If the available bit positions with high reliability are not sufficient for all systematic bits, the remaining systematic bits are mapped to bit positions with low or lower reliability, the systematic bits concerned being distributed as evenly or equally as possible from all to be transmitted systematic bits can be selected.

(c) The parity bits are mapped to symbols with low or lower reliability, the number of parity bits to be mapped being adapted to the symbols available according to steps (a) and (b) by rate adaptation. In the case of 16QAM modulation, as already explained with reference to FIG. 3A, only bit positions or symbols with two different transmission reliabilities, namely with high reliability (H) and low reliability (L), are distinguished. However, the principle described above can of course also be applied to other types of modulation, in particular of higher value, with more than two different reliabilities. 64QAM modulation is of particular interest for the UMTS-HSDPA transmission standard.

As already explained with reference to FIG. 3B, the 64QAM modulation has symbols or bit positions with three different reliabilities, namely with high, medium and low reliability. To apply the method described above, the systematic bits can first be mapped to bit positions of the modulation symbols with high reliability and the parity bits to bit positions with low reliability. The remaining systematic bits and parity bits are then mapped evenly to the bit positions with medium reliability (preference being given to the systematic bits if in doubt). Another possibility is to group the different reliabilities in such a way that there are only two classes of bits to which steps (a) - (c) above can be applied. It makes sense to combine the bit positions with high and medium reliability in one class, while the other class corresponds to the bit positions with low reliability. With 64QAM modulation, the first class then contains twice as many symbols and bits as the second class. Alternatively, half of the bits with medium reliability can be added to the bit class with high and low reliability. In this case, two classes with the same number of bits are created and the implementation of the method can be carried out completely analogously to the 16QAM. With the 8PSK modulation, as with the 16QAM modulation, there are only two different reliabilities, so that the above steps (a) - (c) can, in principle, also be transferred to the 8PSK modulation. However, with 8PSK modulation, the number of bit positions with high reliability is twice as high as the number of bit positions with low reliability, which must be taken into account accordingly in the rate adjustment.

The method described above should preferably be designed in such a way that "related" bits are also output together. This means that systematic bits whose positions differ only slightly in the output bit stream of the channel encoder also follow similar positions in the bit stream

Perform rate adjustment, but before interleaving. It may well happen that neighboring systematic bits have to be distributed over different output bit streams, although the position numbers of these originally neighboring systematic bits are then also similar. This measure ensures that bits belonging together are distributed to positions far apart from one another by the subsequent interleaver, which ensures better transmission properties, particularly in the case of fading.

This principle can be applied both to adjacent systematic bits and to adjacent parity bits and also to adjacent systematic bits and parity bits. In these cases, too, this measure can be used to achieve a wide separation of adjacent bits after interleaving. This is relevant, since every second half iteration of the channel decoding systematic bits are used together with the associated parity bits of the corresponding bit stream with a similar position in the output bit stream of the channel encoder. The more of these bits were poorly transmitted in the local environment, the more likely it is to be incorrectly detected, which which is more likely if these bits were sent over the respective transmission channel at similar times, since the channel properties are typically correlated over relatively short periods of time.

Various exemplary embodiments for realizing the above-described principles for the example of 16QAM modulation and turbo coding with code rate 1/3 are explained below, wherein - as already mentioned - the invention can of course also be applied to other types of modulation. Furthermore, it is assumed below that the bits of the channel encoder provided in each case are divided into a bit stream with systematic bits and two bit streams with parity bits, but the invention is not restricted to this. Finally, it is also assumed below that only parity bits are punctured, although in principle the present invention can also be applied to exemplary embodiments in which the systematic bits are punctured alternatively or additionally.

The following abbreviations are used in the exemplary embodiments described below, the TTI interval (“Transmission Time Interval”) denoting the time period in which a data block coded together is transmitted:

N number of channel-coded bits per TTI interval

X number of tail bits per TTT interval N / 3-X number of information bits per TTI interval

A Number of symbols on the physical channel

B Time length of the TTI interval

M Number of different modulation symbols

According to the current state of UMTS standardization, X = 4. In the case of 16QAM modulation, M = 16 also applies. This results in:

Number of bits per TTI interval: A / B * log ₂ (M)

Number of systematic bits: N / 3 Number of parity bits No. 1: N / 3

Number of parity bits no.2: N / 3

Number of bits with high reliability per TTI interval: ZH = 0.5 * A / B * log ₂ (M)

Number of bits with low reliability per TTI interval: ZL = 0.5 * A / B * log ₂ (M)

Effective code rate: Ce = (N / 3-X) / (ZH + ZL)

In the case of 16QAM modulation, Z = Zh = ZL, i.e. the values for ZH and ZL are identical, since there are the same number of bit positions of the modulation symbols with high and low reliability. With other types of modulation, however, the values for ZH and ZL can - as already described - differ from one another.

4 shows an exemplary embodiment for the transmission path of a mobile radio transmitter according to the present invention for an effective code rate Ce> 0.5.

The bit stream output by the channel encoder 2 becomes with

Using a demultiplexer 11 divided into a bit stream with systematic bits Ξ, a bit stream with first parity bits P1 and a bit stream with second parity bits P2. The function of the bit rate adaptation device 3 shown in FIG. 1 is performed by a mapping device 14, rate adaptation devices 15 and 16, and a multiplexer 17 and a device 18 which describe the previously described Prepare the above steps (a) - (c) in order to be able to map the systematic bits S and the parity bits P1, P2 in the best possible way according to the rules described above to the bit positions with high or low reliability of the symbols of the modulator 5.

The mapping device 14 executes the following mapping algorithm:

(100) S — ai

(101) m = 1

(102) do while m≤Xi

(103) e — ee _m inus

(104) if e <0 then

(105) Dot bit yim

(106) Set bit y2 _m to X_n

(108) ice

(109) Set bit yim to X

(110) Set bit y2 _m to δ end if

(111) m = m + l end do

The parameters used in the mapping algorithm above are assigned as follows:

Xi = N / 3

e _p ι _us = a * Xi

The parameter b indicates whether the bits to be processed are systematic bits S (b = 1), first parity bits Pl (b = 2) or second parity bits P2 (b = 3). The parameter a is selected as a function of b with, for example, a = 2 for b = 2 and a = l for b = 3. The ABS function creates an absolute value.

This mapping algorithm is based on calculating an error value e, which is a measure for the deviation between the instantaneous puncturing rate and the desired puncture, two update parameter e _m inus and e _p ι _us are used to with the aid of the error value either e _m i _{nus is} reduced or increased by e _p ι _us . By evaluating the error value e updated in this way, it is judged whether the respective input bit x _{m is} to be transmitted or not.

In particular, in step 100 the error value e is initially set to an initial value ei _n i, which represents the error between the instantaneous and the desired puncturing rate at the beginning of the method. The index of the currently viewed bit is then set to 1 in a step 101. The sequence embedded in a WHILE loop 102 is then carried out for all Xi bits of the respective data packet no. I. In this case is updated in a step 103 for bit x _m of the error value e, for which purpose the difference is calculated between the instantaneous error value and the updated parameter e _m i _nus. If the result is e≤O (step 104), the corresponding output bit yl _{m of} the upper output bit stream of the device 14 is punctured (step 105), while the corresponding output bit y2 _{m of} the lower output bit stream of the device 14 is set to the value of the input bit x _m (Step 106). The corresponding error value e is then increased by the update parameter e _P ι _us (step 107). However, if e> 0 (step 108), the output bit yl _{m is set} to the value of the input bit x _m and the output bit y2 _m to a fill value δ (steps 109, 110).

The fill value δ identifies bits to be punctured in the second output bit stream y2 and is used to determine the bit order initially unchanged. The second (lower) output bit stream y2 output by the mapping device is combined with the bit streams output by the rate adaptation devices 15 and 16 by a multiplexer 17 to form a common bit stream. All bits which have the fill value δ in this bit stream are then removed from the bit stream by a device 18 connected downstream of the multiplexer 17 and thus punctured.

At the end of the mapping algorithm, the index m of the bit to be processed is incremented (step 111).

The mapping algorithm described above is based on a conventional puncturing algorithm in which a certain number of input bits are mapped to a smaller number of output bits by removing corresponding bits from the input bit stream as evenly as possible. Due to the expansion of this algorithm to two output bit streams explained above, this algorithm is not only suitable for rate adaptation, but also for demultiplexing bits onto the second output bit stream, with which the bits removed from the primary bit stream are transmitted. It is crucial for the performance of the transmission system that the selected bits are correlated as little as possible with regard to their information content, which is achieved by choosing the distance between two punctured bits or between two bit streams y1 and bitstream y2 as evenly as possible Bits is reached.

The function of the mapping device 14, to which the systematic bits S are supplied, was previously described using the mapping algorithm. The first parity bits P1 and the second parity bits P2 are each subjected to a rate adjustment algorithm by the rate adjustment devices 15 and 16, which is similar to the mapping algorithm described above, but with the exception that that in each case the corresponding input bit stream is mapped onto only one output bit stream by removing or puncturing bits as uniformly as possible. That is, the rate adjustment algorithm corresponds to the above mapping algorithm without steps 106 and 110, wherein in addition in step 105 the corresponding bit is preferably not punctured immediately, but is first set to the fill value δ.

The puncturing device 15 executes the rate adjustment algorithm with respect to the first parity bits P1 with the following parameters:

Xi = N / 3

e _p ι _us = a * Xi e _minus = a * ABS (dNl) with dNl = N / 3-FLOOR (Z / 2) + FLOOR (0, 5 * (N / 3-Z))

The FLOOR function rounds off the argument in parentheses to the next smaller integer value.

The above parameters apply with the exception of the value for e _m inus and for the respect of the puncturing device 16 of the second parity bits P2 Ratenanpas- Sung-algorithm performed, with the proviso here:

e _m inus = a * ABS (dN2) with dN2 = N / 3-CEIL (Z / 2) + CEIL (0, 5 * (N / 3-Z))

The CEIL function rounds the argument in brackets up to the next larger integer value.

As has already been briefly mentioned, the multiplexer 17 combines the second output bit stream y2 of the mapping device 14 and the output bit streams of the puncturing devices 15, 16 into a common bit stream, in which the device 18 then removes all the bits to which the fill value δ has previously been assigned.

The first (upper) output bit stream y1 output by the mapping device 14 is fed to a first interleaver 4a which, according to a certain scheme, maps the corresponding bits to high-reliability bit positions (hereinafter also referred to as H-bit positions) of the 16QAM modulator 5 reorders. The bits output by the device 18, on the other hand, are to be mapped to bit positions with low reliability of the modulator 5 (hereinafter also referred to as L-bit positions), so that a separate interleaver 4b is provided for these bits, which carries out a desired rearrangement.

FIG. 5 shows a further exemplary embodiment of the present invention for an effective code rate Ce in the range 1/3 <Ce <0.5.

In contrast to FIG. 4, two mapping devices 19, 20 are provided. The mapping device 19, to which the first parity bits P1 are fed, executes the mapping algorithm explained above with the following parameters:

Xi = N / 3

e _minus = a * ABS (dN3) with dN3 = FLOOR (0, 5 * (ZN / 3))

In contrast, the mapping device 20, to which the second parity bits P2 are supplied, executes the mapping algorithm explained above with the following parameters:

Xi = N / 3 e _ini = b

eminus = a * ABS (dN4) with dN4 = CEIL (0, 5 * (ZN / 3)) The two mapping devices 19, 20 each deliver two output bit streams yl, y2, as described above, the first output bit stream yl being supplied to the mapping device 19 of a rate adjustment device 21 which supplies the corresponding bits to the rate adjustment algorithm described above with the following parameters subjects:

Xi = N / 3-FLOOR (0.5 * (ZN / 3)) e _ini = be _P ι _us = a * Xi e _minus = a * ABS (dNl) with dNl = N / 3-FLOOR (0.5 * (ZN / 3)) -FLOOR (Z / 2)

The first output bit stream y1 of the mapping device 20, on the other hand, is fed to a rate adjustment device 22, which subjects the corresponding bits to the rate adjustment algorithm with the following parameters:

Xi = N / 3-CEIL (0.5 * (ZN / 3)) e _ini = b

with dN2 = N / 3-CEIL (0, 5 * (ZN / 3)) -CEIL (Z / 2)

The output bits of the two rate adjustment devices 21, 22 are combined by a multiplexer 25 to form a common data stream and fed to the interleaver 4b for reordering and mapping to the bit positions of the modulator 5 with low reliability.

The second output bit streams y2 of the mapping devices 19, 20, on the other hand, are fed together with the systematic bits S to a multiplexer 23, which generates a common data stream therefrom, a device 24 subsequently removing all bits with the fill value δ before the remaining bits the interleaver 4a for temporal rearrangement and mapping to the bit positions with high reliability of the modulator 5 are supplied. FIG. 6 shows a further exemplary embodiment of the present invention for an effective code rate Ce≤l / 3.

This exemplary embodiment largely corresponds to the exemplary embodiment shown in FIG. 5, but an additional rate adjustment device 26 is provided for the systematic bits S, which performs the rate adjustment algorithm with the following parameters:

Xi = N / 3

In contrast to the exemplary embodiments shown in FIGS. 4 and 5, however, the bits selected by the rate adaptation algorithm are not punctured, but repeated.

In contrast to FIG. 5, the two rate adjustment devices 21, 22 also perform bit repetition, the rate adjustment device 21 using the following parameters:

Xι = N / 3-FLOOR (0.5 * (Z / 3)) ei _n i = b

with dNl = FL00R (Z / 2) -N / 3 + FLOOR (0, 5 * Z / 3)

The rate adjustment device 22 uses the following parameters according to FIG. 6:

Xi = N / 3 CEIL (0.5 * Z / 3)

e _p ι _us = a * Xi eminus = a * ABS (dN2) with dN2 = CEIL (Z / 2) -N / 3 + CEIL (0, 5 * Z / 3) The mapping algorithm of the mapping device 19 is carried out with the following parameters:

Xi = N / 3 e _ini = be _p ius = a * Xi e _m i _nus = a * ABS (dN4) with dN4 = FLOOR (0, 5 * Z / 3)

The mapping device 20, on the other hand, executes the mapping algorithm with the following parameters:

Xi = N / 3 i _n i =

e _minus = a * ABS (dN5) with dN5 = CEIL (0, 5 * Z / 3)

Otherwise, with regard to the exemplary embodiment shown in FIG. 6, reference may be made to the statements relating to FIG. 5.

What is common to the exemplary embodiments shown in FIGS. 4 to 6 is that the bits output by the interleaver 4a are mapped to symbols or bit positions of the 16QAM modulator 5 with high reliability, while the bits output by the interleaver 4b to the less well protected bit positions are mapped with low reliability.

The exemplary embodiments shown in FIGS. 5 and 6 can also be modified in such a way that the function blocks 19 and 21 or the function blocks 20 and 22 are interchanged. Integration of the function blocks 21 and 22 into the function blocks 19 and 20 is also possible.

Further exemplary embodiments of the invention are described below. It is characteristic of these exemplary embodiments that this does not involve a so-called block processing. processing is assumed, ie that the individual bits are not supplied in blocks to the various units, for example for carrying out the rate adaptation and mapping algorithms, etc., but rather that essentially one block executes these functions in succession for all supplied bits. As a result, each individual bit is read in at the end, processed, ie punctured or repeated, and output on the appropriate output. As with the exemplary embodiments discussed above, various implementation options come into question for a specific implementation in a transmitting or receiving device, but these are not dealt with in more detail in the context of this description.

In the context of this description it is assumed that the turbo encoder outputs the bits to be output in the sequence S (1), PICL), P2 (1), S (2), Pl (2), P2 (2), ... where S (i) or Pl (i) or P2 (i) denotes the systematic bit no. i or the parity bit no. i of the first or second parity bit stream. An adaptation to other orders is also conceivable.

The process then proceeds in the following steps:

(200) Initialize the parameters used below (depending on the algorithm used, these can in particular be the parameter sets e, eι _n i, e _m i _nu s and e _p ι _us , which are described in more detail below initialize suitable loop counters, which are not discussed in more detail here. Basically, the initialization can be carried out analogously to the above algorithms).

(201) Read a bit from the input and determine its membership in a class, e.g. Systematic bits S and parity bits P1 or P2.

(202) Use the class of the bit to determine the rate adaptation for this bit, ie whether the bit is punctured, whether it is transmitted or even repeated (and if so, how often). (203) Use the class of the bit to determine the output bit stream to which the bit (or, if repeated, the bits) should be output.

(204) Repeat steps 201 to 203 until all bits have been processed.

The rate adjustment algorithm in step 202 can be the same algorithm as described above or in the currently valid specification of UMTS. However, different sets of parameters for the variables e, ei _n i, e _m i _nus and e _p ι _us are used for each class of bits. This can be easily achieved if these parameters are provided with an index that designates the class of the bits currently being processed. This corresponds to the parameter b already introduced.

The mapping algorithm in step 203 can also be the same algorithm as already described above. Here too, different sets of parameters for the variables e, eini, e _m i _nU s and e _p ι _us are used for each class of bits. This can be easily achieved in an analogous manner if these parameters are provided with an index which denotes the class of the bits just processed, which in turn corresponds to the parameter b already introduced. Output bit streams are defined for each class of input bits. If only one output bit stream is assigned to a class, all bits of this class are output to this output bit stream. If two output bit streams are assigned to a class, the bits are divided between the two output bit streams according to the mapping algorithm presented above. However, in this exemplary embodiment it is not necessary to use the value Ö as the “fill value”. Since the bits are processed sequentially, not in blocks, it is ensured a priori that the bits get into the output bit streams in the correct order. The algorithm can also be expanded to more than two output bit streams, for example by using several selection processes. be carried out consecutively. However, this will rarely be necessary (unless there are so many bits in a class that more than two output bit streams must be used).

In the description so far, the exemplary embodiment just described is equivalent to the exemplary embodiments already described. However, it can easily be varied even further, which is also possible in the previous nomenclature, but it may be easier to show here. The following exemplary embodiments should therefore not be regarded as being restricted to this nomenclature.

According to the methods described so far, the rate adjustment process and the mapping process are carried out independently of one another. However, this does not have to be optimal in all cases. Rather, it can be advantageous to carry out the two algorithms as a function of one another. For example, consider the case where a class of bits must both be punctured and split across two different output bit streams. With uncoordinated execution it can happen that in the vicinity of a punctured bit another bit is output on an output bit stream of low reliability. Both bits are thus less well protected than those bits which are output (unpunctured) on the output bitstream with high reliability. It would be more beneficial to ensure that such an unfavorable encounter is avoided.

This can be done in the following three different ways, which can be viewed as three different exemplary embodiments:

1) The mapping algorithm additionally processes information relating to the puncturing that has already been carried out, whereby in the vicinity of a puncturing an assignment to the less reliable output bit current should be avoided if possible.

2) The rate adjustment algorithm additionally processes information relating to the mapping carried out in the environment, puncturing being avoided as far as possible in the vicinity of an assignment to the less reliable output bit stream. However, the influence of the puncturing is often more serious than the influence of the assignment. In these cases, this variant will tend to work less well than variant 1).

3) The rate adjustment algorithm and the mapping algorithm are preferably combined in a single algorithm or several algorithms. This algorithm first selects bits that are "weakened", either by puncturing or by assignment to the less reliable output bit stream. In a second step, a decision is then made as to which of these two alternatives should be carried out. In a further variant, between distinguish between the two types of "weakening", since puncturing is more serious than the assignment to the less reliable output bit stream. After (or before) puncturing, but especially between two successive puncturing, a larger distance is left than after (o- before) an assignment, in particular between two assignments, to the less reliable output bit stream. The importance of the bits in the vicinity of punctured bits is increased in order to avoid that many bits are mapped or badly mapped to bad positions in this area It is thus achieved that bits are assigned to the reliable output or output bitstream are mapped.

An exemplary embodiment of variant 1 is described below. This embodiment is particularly relevant for code rates between 0.33 and 0.5. In this area the parity bits are punctured and some of the parity bits are mapped onto the more reliable output bit stream, but most are output via the less reliable output bit stream. The standard puncturing algorithm is used for puncturing. The mapping algorithm is performed, however, as follows: The error parameter e is not reduced at each bit the value e _m i _n us, but only when a bit is punctured. If e is less than 0 for the following bit, this bit is assigned to the more reliable bit stream and e is increased by e _p ι _us . Otherwise, the bit is assigned to the less reliable bit stream.

Another exemplary embodiment of variant 1 is described below. It is particularly relevant for code rates between 0.5 and 1. In this area, the parity bits are punctured relatively heavily (more than half of the parity bits are punctured) and some of the systematic bits are mapped to the less reliable output bit stream, although most systematic bits are assigned to the more reliable output bit stream. There is a certain influence here on the puncturing pattern of the parity bits Pl and the mapping pattern of the systematic bits S. Both are used in the first, third, fifth ... half-iteration of the turbo decoder, again with no weakening due to punctured parity bits Pl and associated systematic Bits S should accumulate in certain places. Extensive simulations have shown that the following procedure gives good results: the standard puncturing algorithm is used for the puncturing. The mapping algorithm but performed as follows: The error parameter e is not reduced at every systematic bit to the value e _m i _nus, but only if a parity bit Pl, that is, a parity bit of the first parity tätbitstroms Pl, is not punctured. If e is less than 0 in the subsequent systematic bit, this bit is assigned to the less reliable output bit stream and e increased by e _p i _us , otherwise this bit is assigned to the more reliable output bit stream.

The entire algorithm (without the initialization of the parameters) can then be represented as follows:

(300) For i = 1 to 3 do e (i) = e _ini (i) enddo; emap = 0

(301) m = 1

(302) do while m≤Xi (303) set b

(304) e (b) = e (b) -e _minus (b)

(305) if e (b) <0 then

(306) Dot bit no. m

(307) e (b) = e (b) + e _plus (b)

(309) ice

(310) Output bit no. M on the appropriate output bit stream:

(311) if "Class b should be divided into two output bit streams" then

(312) if emap≤O then

(313) Do not output bit no. M on the originally specified output bit stream current (b), but on the other output bit stream stomalt (b)

(314) emap = emap + emap _p ι _us

(315) ice

(316) Output bit no. M on the original given output bit stream Stro (b)

(317) endif

(318) ice

(319) Give bit number m on the originally intended output bit stream

Stro (b) off

(320) endif (321) endif

(322) m = m + l

(323) enddo

The parameter b set in step 303 indicates whether the bits to be processed are systematic bits S (b = 1), first parity bits Pl (b = 2) or second parity bits P2 (b = 3). The (first) output bit stream provided by default or by default for bit mapping is denoted by stream (b), while the alternative (second) output bit stream is denoted by

Stromalt (b) is designated. Mapping parameters emap and emapminus are used in the course of the mapping algorithm, emapminus being used in step 308 to reduce emap.

Depending on the selected code rate, either parts of the systematic bits are output on the less reliable output bit stream or parts of the parity bits are mapped on the more reliable output bit stream. This is achieved by suitable selection of all "e" parameters and by selection of the appropriate bit stream for the respective mapping step.

All of the exemplary embodiments described above have in common that either parts of the systematic bits correspond to the bit stream which is fed to the interleaver 4b and is mapped to bit positions with lower reliability, and / or parts of the parity bits to the bit stream which is fed to the interleaver 4a and with bit positions higher reliability is mapped. With regard to the transmission security, it can be advantageous if the assignment or reordering patterns used for this purpose are not chosen to be constant, but are changed in a data-packet or even bit-specific manner. This can be done by appropriately adapting the parameters in the above algorithms, in particular, for example, the parameters can be ei _n i data frame or changed bitspezifisch or selected.

The invention has so far been described using various concrete selection or rate adjustment algorithms. Furthermore, other rate adjustment algorithms can also be used and combined with the mapping algorithm as already described. However, these rate adjustment algorithms can also be operated without a combination with the mapping algorithm and can therefore be used advantageously by and with a person skilled in the art with and without the use of a mapping algorithm. In particular, two types of rate adjustment algorithms can be distinguished: in the first case, at least all systematic bits are transmitted, and as much parity bits as there is still space in the transmission packet afterwards. This results in a so-called self-decodable redundancy version, i.e. the data sent can be reconstructed (at least if there are not too many transmission errors) from a single such redundancy version. This is particularly relevant for the first transmission in a HARQ method, since this can only be decoded without the aid of further data packets. This is not absolutely necessary for the subsequent transmissions, since it can be decoded with the aid of the first redundancy version (and possibly also more). It turns out that in such cases it can be advantageous not to transmit all systematic bits in the following redundancy versions, but also to puncture the systematic bits and instead to transmit more parity bits. In extreme cases, all systematic bits can also be transmitted puncture, i.e. only transmit parity bits. Such methods can be combined with all of the above-mentioned exemplary embodiments.

Another type of rate adjustment algorithm works as follows (although in the following description no longer differentiates between parity and systematic bits it is applicable for both cases): First, a set of candidates is selected from all bits. In a second step, the bits to be transmitted are then selected from these candidates. This is particularly advantageous if the receiver does not have so much memory that it can store all possible bits (or their received values), but only a smaller number. The number of candidates is then selected according to this number, thus ensuring that even in the sum of several transmissions, no more than this number of different bits can be transmitted. This ensures that the receiver can actually store all of the transmitted bits and thus take them into account.

Such a selection process is shown by way of example in FIG. 10.

The easiest way to select the candidates is to use an algorithm that is structured like one of the rate adjustment algorithms mentioned above, as is to select the redundancy version. However, this selection is not optimal, as can be seen in the following example, see also FIG. 11. Assume that the total number of bits to be transmitted is 24 (top line of FIG. 11), the number of candidates or the memories of the receiver is 6 and in a redundancy version 4 bits should be selected. The 6 candidates can be selected with the same spacing (X in the middle line), but the 4 bits to be transmitted cannot, the rate adjustment algorithm then selects 4 bits that are as equally spaced as possible, resulting in those marked with x in the third line of FIG. 11 bits. This selection of bits is significantly more uneven than would be the case if 4 bits to be transmitted were selected directly from 24, this pattern is shown in the bottom line for comparison. A non-optimal selection of bits is disadvantageous in particular in the first transmission or first redundancy version, since this has to be decoded with the least bit. On the other hand, a correct Especially the right decoding of the first transmission should be aimed for, because then the throughput is maximized. Since the coding rate of the first transmission rate is expediently adapted to the channel properties, significantly more bits are already transmitted by a second or a further redundancy version, so that correct decoding will generally be possible quite often, since more data than is typically required are available stand. A less than optimal coding or selection of the data for the second or a further redundancy version will therefore not be particularly disadvantageous in practice. In particular, the selection algorithm for the first redundancy version must be optimized. It must also be taken into account that the first redundancy version can often only send a small number of parity bits, since all systematic bits must be sent. Since a large proportion of the parity bits must be punctured (typically up to 5/6), it is particularly important to distribute the few remaining parity bits as evenly as possible. In the following redundancy versions, significantly more parity bits can typically be sent, since no systematic bits have to be sent. With these many bits, minor irregularities in the distribution pattern are not as serious.

In order to improve this unsatisfactory situation and still be able to apply the concept of two-stage selection via candidates, one of the following exemplary embodiments can be used:

a) Choose an optimal pattern for the first redundancy version (second line in FIG. 12). The set of candidates then results from this optimal pattern plus additional bits. These bits are expediently selected as evenly as possible in the spaces between the pattern of the first redundancy version (third line in FIG. 12). The following redundancy versions are created from the candidates selected. In a further embodiment, the bits that are not sent in the first redundancy version can be preferred in the second or also in further redundancy versions. This ensures that all available candidates can be transferred as early as possible.

b) Select the number of candidates so that when using a rate adjustment algorithm the selected bits for the first redundancy version are as evenly distributed as possible. This means that the number of candidates is not chosen to be evenly distributed, but rather anticipates the selection pattern of the rate adjustment algorithm and at those points where the rate adjustment algorithm leaves the (slightly) larger distance between two selected bits to select the candidates somewhat more densely. Then these two imbalances compensate for the entire selection for the first redundancy version. This is shown using the example of FIG. 13: Line two shows the candidates that were selected such that an optimal distribution (line 3) results from these candidates when using a rate adjustment algorithm.

c) Variant b can also be generalized to the effect that both the first selection algorithm for the selection of the candidates and therefore also the second selection algorithm are modified. The first selection algorithm expediently selects bits optimized for the first redundancy version and likewise fills the spaces as evenly as possible. The second selection algorithm then selects the bits for a (in particular the first) redundancy version from the candidates. In this case, an algorithm based on the calculation of an error value e can be used, as has already been described above in several variants: The error value e is starting at eini in each case by a predetermined value e _m _. _nus ER- low, if e becomes less than 0, a bit is either punctured or selected and the error value increased by e _p ι _us . This algorithm can be adapted so that e is not reduced by the same value e _m i _nu s for each candidate, but by a value that is proportional to the number of bits in the original bit stream between two candidates. If the selection of the candidates and the selection of a redundancy version are carried out at the same time, e can be reduced by a value e'minus for each bit of the original total current. This allows an inexpensive implementation without the need to store the number of original bits between two candidates in the transmitter or receiver.

A particularly simple to implement embodiment provides that the number of candidates is not necessarily chosen to be the maximum (that is, corresponding to the storage capacity of the recipient). Instead, the number of candidates is chosen so that it is in a simple ratio to the number of bits selected for the first redundancy version. In this context, a simple ratio (and thus a preferred exemplary embodiment) is, for example, the case where the number of candidates is a multiple of the number of bits selected for the first redundancy version. The rate adjustment algorithm, which selects the bits for the first redundancy version from the candidates, can then make a strictly regular selection (e.g. every 4th bit), which makes the resulting pattern as regular as possible again (there are only one or two possible intervals between adjacent selected bits, and the distribution of any two distances is even). For example, if 10 bits can be selected for the first redundancy version, the number of candidates should be divisible by 10. If the recipient actually has space for 45 reception values, only 40 candidates should still be used. Although the reduced number of If candidates have a deterioration in the transmission characteristics for a later redundancy version, this is more than compensated for by the improvement of the transmission characteristics for the first redundancy version, since the first redundancy version has a greater influence on the overall performance of the system.

A further simple ratio (and thus a preferred exemplary embodiment) is the case in this context that the number of candidates is in a simple division ratio to the number of bits selected for the first redundancy version. This allows the use of more candidates, but at the expense of the performance of the first redundancy version. One possible compromise is to use the simplest possible division ratio, in which the difference between the number of

Candidates and the memory size of the receiver is smaller than a specified threshold.

In the exemplary embodiments just discussed, it was assumed that the receiver knows the number of bits selected for the first transmission. This is usually a reasonable assumption. Although it may be that the receiver does not receive the first transmission and therefore these parameters due to transmission errors, the sender (since he learns of this fact from the HARQ protocol) should again send a "first" transmission (ie a self-decodable packet) , since it makes no sense to send a packet that is not self-decodable. This second “first” transmission packet means that the receiver now knows the number of bits selected for the first transmission.

If this is not guaranteed in all cases due to special properties of the transmission protocol (for example because the capacity of the channel fluctuates, for example due to changes in allocated resources), the currently valid number of for the first transmission selected bits are also explicitly communicated to the receiver. Alternatively, in a further exemplary embodiment, a typical number can be used instead of the currently valid number of bits selected for the first transmission. This typical number can be differentiated depending on the type of modulation and, if necessary, the type of coding. Since the type of modulation and possibly coding must be communicated to the receiver anyway, this does not result in any increased signaling requirements; in the event of a connection being established, these typical numbers must also be transmitted once.

Another quite different rate adjustment algorithm is shown in FIG. 14. The bits of a class (systematic, party 1 and / or parity 2) are written into an interleaver (scrambler), which outputs the bits in a different order. A block of bits with the desired number is then selected from this stream. This selection is represented by the horizontal arrows, which each select a block of bits from the interleavers (after scrambling). Different block sizes can also be selected from different interleavers. Parity 1 and 2 bits can either be written in separate interleavers or in a common interleaver.

The interleaver is intended to ensure that by selecting a block after the interleaver, bits that are as evenly distributed as possible are selected in front of the interleaver. In this concept, however, since the interleaver is the same for every possible number of selected bits, it cannot be optimal for every possible number. According to a preferred embodiment, the interleaver is optimized especially for a particularly relevant case of the number of bits to be selected. For example, for an HSDPA connection ("High Speed Downlink Packet Access") in UMTS mobile radio systems, in particular coding questions of% or% are proposed (depending on the channel properties). The As a result, the party bits are transmitted 50% of the time the first packet is transmitted, or only a sixth of the parity bits. If only a sixth of the parity bits are transmitted, a non-optimal selection of the parity bits has a particularly strong effect. According to the preferred exemplary embodiment, the interleaver for the parity bits would therefore be selected such that the bits in the first sixth of the interleaver are distributed as evenly as possible. For example, in this block there could be bits with the index in the original order of k * 6 + kO, where k passes through the values 1, 2, 3 ... and kO is a constant from the set 0,1,2,3,4 , 5 is. In the particularly relevant case, this ensures that an optimal bit selection is carried out. In the same way, the bits in the first half can be chosen as j * 2 + jO, where j passes through the values 1, 2, 3 ... here jO can be chosen either 1 or 0. Both cases can also be combined, jO = 1 must be selected if kO is chosen odd and jO = 0 is selected if kO is selected. An embodiment variant of such an interleaver consists in writing the bits in columns, then exchanging the lines of the interleaver according to a predetermined exchange rule, and then reading out the bits line by line (if necessary, additional exchanges can be made, for example within a line) Interleavers can then be determined by the exchange rule.

A possible exchange rule for the use of an interleaver with 30 lines is given by the exchange pattern 0, 20, 10, 5, 15, 25, 3, 13, 23, 8, 18, 28, 1, 11, 21, 6, 16, 26, 4, 14, 24, 19, 9, 29, 12, 2, 7, 22, 27, 17. That means line 0 remains line 0, line 1 becomes the original line 20 etc

If 1/6 of the bits are selected here, which corresponds to a particularly relevant rate, bits with the result Index 0 + i * 30, 20 + i * 30, 10 + i * 30, 5 + i * 30, 15 + i * 30, ordered, this gives the bits with the index 0, 5, 10, 15, 20, 30 , 35, 40, 45, 50, 60, ...

As you can see, there is no even distribution, but an enlarged gap between 20 and 30, between 50 and 60, etc.

This is because the column swapping operation is divided into 5 groups, each with 6 elements. A better choice would be a division into 6 groups, each with 5 elements, because then if 1/6 of the bits were selected, which corresponds to the first 5 lines, a group would be completely selected. This first group should contain the elements 0, 6, 12, 18, 24 in any order, the subsequent groups would then also contain 5 elements, within a group all elements have the same remainder when divided by 6 In addition, the elements within a group can still be permuted as desired, so that a better distribution can be achieved if the selection rate differs from 1/6. In order to optimize a selection rate of, the first 3 groups should also contain even and the following 3 groups odd elements.

A possible exchange rule would then be:

0, 12, 24, 6, 18,

4, 16, 28, 10, 22,

2, 14, 26, 8, 20, 1, 13, 25, 7, 19,

5, 17, 29, 11, 23,

3, 15, 27, 9, 21.

The first group is 0, 12, 24, 6, 18, the following groups emerge from this group by adding the values 4, 2, 1, 5 and 3 to the corresponding elements of the first group. The properties of interleavers, which are used according to the rate adjustment algorithm and the mapping algorithm, are described below. These interleavers are therefore different from the interleaver just described, which can be used as parts of a rate adjustment algorithm. If both interleavers are to be used, the rearrangement operation of the interleaver just described can also be undone, so that only the effect of the rate adjustment remains.

The two interleavers 4a, 4b are preferably designed such that they distribute adjacent or closely spaced input bits as well as possible within the frame to be sent (“frame” or TTI). In particular, those bits that are within the so-called influence length of the constituent convolutional code used for the channel or turbo encoder 2 should be distributed as evenly as possible in order to utilize the maximum time diversity ("time diversity").

Also, bits that are close to each other, which get into the different interleavers 4a, 4b, should be distributed as well as possible. For this reason, the interleavers 4a, 4b should be designed differently, since otherwise, for example, two adjacent bits, one of which is fed to the interleaver 4a and one to the interleaver 4b, would be distributed again to successive positions. However, this is undesirable for reasons of transmission security and transmission quality, since both bits are affected, for example, when poor channel properties or high noise levels occur, particularly during the transmission of the two corresponding symbols. Such decoding errors can, however, be corrected by decoders more poorly than errors which occur in a distributed manner. Therefore, there is basically also the need for interleaver structures, which can be used to achieve good transmission quality and transmission security when applying the previously explained invention.

At the output of the interleaver 4a, 4b, the bits are to be mapped to the corresponding modulation symbols in a suitable manner. In the arrangement according to the prior art shown in FIG. 2, it is assumed that the bits of the interleaver 4a, 4b are output after a parallel / serial conversion in the order HHLL, since each modulation symbol has two bits with high reliability and two bits with lower Reliability. For the selection of the interleaver 4a, 4b, however, it is advantageous if the bits are output in the order HLHL, i.e. bits of the interleaver 4a, which are to be mapped on bit positions of the modulation symbols with high reliability, and bits of the interleaver 4b, which are to be mapped on bit positions of the modulation symbols with low reliability, are alternately output. Sorting according to the HLHL scheme is easier to process, since only even positions and odd positions need to be distinguished. With the conventional HHLL scheme, on the other hand, four different positions in blocks of four bits each have to be distinguished.

The order HLHL is therefore assumed below, although the interleaver structures described below can of course be adapted accordingly for the order HHLL.

Interleavers that are easy to implement are block interleavers, into which data is written line by line and read out column by column. As already mentioned, such interleavers are problematic in the implementation of the invention, since consecutive bits would then also be output consecutively. However, this problem can be avoided if the data or bits are read out offset from the second interleaver. The result of this is that, for example, the first bit of the second interleaver output does not correspond to the first bit written into this interleaver, but rather to a bit shifted by a certain number of sets. With a suitable choice of the offset, very good nesting can thus be achieved.

The optimal choice of offset can be determined as follows. After interleaving, the first bit read in of the second interleaver should be approximately in the middle of all the bits output, since on the one hand it is far away from the first read bit and the neighboring bits of the first interleaver, and on the other hand the subsequent bits of the second interleaver are also far away are removed from the first bit of the first interleaver. If this bit is output extremely early, it will be close to the first output bit of the first interleaver. If, on the other hand, it is output extremely late, it will be close to the following bits of the second interleaver. In the case of interleavers with, for example, 64 * 30 bits, the offset should therefore be selected such that the first bit of the second interleaver read is output as output bit No. 960 = 64 * 30/2 or in the vicinity thereof.

In addition, a further optimization can be achieved if the position of the first output bit of the second interleaver is selected such that it lies as precisely as possible in the middle between the bits of the first interleaver closest in the order of writing.

A corresponding example is shown in FIG. 7. The diagram shows the bits horizontally when writing into the corresponding interleaver and vertically the order when reading them out, with bits 27 of the first interleaver having a Check and the bits 28 of the second interleaver are shown with a square. It can be seen from FIG. 7 that the first bit of the second interleaver output and the two closest bits of the first interleaver (marked with a circle in FIG. 7) are optimally shifted from one another, ie the (read) position of the first bit of the second The interleaver lies exactly in the middle of the (read) positions of the two bits of the first interleaver closest in the order of writing. It may be necessary to shift the positions of the second interleaver by one position, since the bits of the second interleaver, ie interleaver 4b in FIGS. 4 to 6, move to odd positions for mapping to bit positions with low reliability, as described should come to lie.

The previously described method of a suitable configuration of the two interleavers 4a, 4b in order to achieve optimal interleaving properties of the resulting overall interleaver can also be extended to other types of interleaver. This applies in particular to interleavers with column swapping, in which the individual columns are swapped according to a predefined pattern before the rows are read out. By means of a suitable column swapping rule, a further improvement in the interleaving properties can be achieved compared to block interleavers. This will be explained in more detail below.

The optimization criterion for a suitable combination of two identical interleavers is different in the case of interleavers with interchanged columns than when using block interleavers. The column swapping operation distributes successive bits much better. However, since the bits are distributed over the entire area, there are no "unoccupied" areas into which the output of the second interleaver could be shifted, as is possible with a block interleaver. Rather, in the optimal output of the second interleaver, the special selected column swapping operation are taken into account. The best displacement can then be determined by examining all possible displacements, the following displacement parameters being available:

(i) Shift in "horizontal" direction when registered:

The first bit written in the second interleaver does not necessarily have to be written in the first column of the second interleaver, but can alternatively also be written in any other column, in which case the remaining columns are described cyclically starting with this column.

(ii) Shift in "horizontal" direction when reading out: As a variant to (i), the shift can also take place when reading out, not when writing in. I.e. the first bit of the second interleaver output does not necessarily have to be read out from the first column, but can alternatively also be read out from any other column, the other columns then being read out cyclically starting at this spade.

(iii) Shift in "vertical" direction:

The first bit of the second interleaver to be read out does not necessarily have to be read out from the first line, but can alternatively also be read out from every other line of the second interleaver, the other lines then being read out cyclically starting with this line. In this case, such a shift in writing and reading out is equivalent, since in the interleavers under consideration there are generally no line swaps.

8 shows an exemplary embodiment for a "horizontal" shift by three columns when writing into the second interleaver (variant (i)) and a "vertical" shift by 15 rows (variant (iii)). The diagram shows the position horizontally (ie along the x-axis) of the bits when writing into the interleaver and vertically (ie along the y-axis) their position when reading out. For each bit, the corresponding position is also indicated next to the corresponding bit when writing to the interleaver, with only the first 120 bits which are written to the interleaver being shown for better illustration.

The above-described shift operation is indicated by an arrow in FIG. 8. The first written bit of the second interleaver (bit no. 2 of the entire interleaver) experiences the same column swapping as bit no. 4 of the first interleaver (bit no. 9 of the entire interleaver), but is compared to bit no. 4 of the first interleaver the second interleaver is only output 15 positions later (since bits are output alternately by both interleavers, this results in a total shift of 2 * 15 + 1 = 31 positions).

Another variant of the generation of two optimally coordinated interleavers 4a, 4b is to use different, but coordinated, column swapping operations for both interleavers 4a, 4b.

In block interleavers with column swapping - as has already been explained - the bits are written line by line and the columns are then exchanged according to a predetermined scheme, whereby according to one embodiment of the invention, even columns are exchanged only with even columns and odd columns only with odd columns. The bits are then read out in the following order: the first bit of the first column, the first bit of the second column, the second bit of the first column, the second bit of the second column, then alternately one bit each of the first and second columns to these have been completely read out, then analogous reading of the third and fourth columns etc. This process is equivalent to the use of two interleavers with different column swapping, but each time a column swapping is sought which, provided that only even columns and odd columns can be swapped, achieves the best possible scrambling or distribution of the bits.

A column swapping scheme that meets these conditions can be obtained, for example, by starting with a conventional column swapping scheme without the restriction regarding the prescribed swapping of the even and odd columns.

Such a conventional column swapping scheme is shown in the first row of Figure 9, with the columns numbered 0. If, in this conventional column swapping scheme, an odd column were exchanged for an even column or vice versa, an adjacent column or a column close to it could simply be used instead. The result of this operation is shown on the second line of FIG. 9, with the changes made compared to the first line of FIG. 9 being highlighted in bold. If this results in unfavorable conditions, you can try to improve this by swapping the columns. A corresponding one

The exemplary embodiment is shown in the third line of FIG. 9, with changes in relation to the second line of FIG. 9 again being highlighted in bold.

In this way, different column swapping schemes for both interleavers 4a, 4b can be determined, which enable the best possible results.

Claims

claims

1. Method for adapting the bit rate of a bit stream to be transmitted in a communication system, the bit stream to be transmitted being channel-coded and converted into systematic bits (S) and parity bits (Pl, P2), and wherein the systematic bits (S) and the parity bits ( Pl, P2) are modulated for transmission, the systematic bits (S) and the parity bits (Pl, P2) being mapped to bit positions of modulation symbols (13) which have different reliabilities with respect to transmission, characterized in that the systematic Bits (S) are mapped to bit positions of the modulation symbols (13) with a high reliability and, if the number of bit positions with the high reliability is not sufficient, to bit positions with a lower reliability, and that the parity bits (Pl, P2) are mapped to that remaining bit positions with the lower reliability according to the corresponding D Implementation of a bit rate adaptation (15, 16; 21, 22).

2. The method according to claim 1, characterized in that the parity bits (Pl, P2) are subjected to the bit rate adaptation in such a way that an adaptation of the number of parity bits (Pl, P2) to be mapped to the bit positions with the lower reliability to that shown in the figure of the systematic bits still available bit positions with the lower reliability.

3. The method according to claim 1 or 2, characterized in that the systematic bits (S) to be mapped to the bit positions with the lower reliability are selected uniformly from all systematic bits to be transmitted.

4. The method according to any one of the preceding claims, characterized in that the modulation symbols (13) have bit positions with at least a high reliability, a medium reliability and a low reliability, and that the systematic bits (S) on the bit positions with the high reliability and, if the number of high reliability bit positions is not sufficient, the medium reliability bit positions are mapped, while the parity bits (P1, P2) are mapped to the low reliability bit positions and the remaining medium reliability bit positions ,

5. The method according to any one of claims 1-3, characterized in that the modulation symbols (13) have bit positions with at least three different reliabilities, that the reliabilities are divided into a first group of reliabilities and a second group of reliabilities, the in Reliability contained in the first group are higher than the reliability contained in the second group, and that the systematic bits (S) on bit positions of the modulation symbols (13) with a reliability contained in the first group and, if the number of bit positions with a reliability contained in the first group is not sufficient, are mapped to bit positions with a reliability contained in the second group, and that the parity bits (P1, P2) to the remaining bit positions with a reliability contained in the second group after a corresponding implementation of a bit rate adjustment related to the parity bits (Pl, P2).

6. The method according to claim 5, characterized in that the modulation symbols (13) have bit positions with at least a high reliability, a medium reliability and a low reliability, and that the bit positions with the high reliability and the bit positions with the medium reliability of the first group and the bit positions with the low reliability are assigned to the second group.

7. The method according to any one of the preceding claims, characterized in that the systematic bits (S) and the parity bits (P1, P2) are supplied to an interleaver device (4a, 4b) which is configured in this way before they are mapped onto the modulation symbols (13) is that originally adjacent bits in the bit stream are mapped to bit positions that are as far apart as possible.

8. The method according to any one of the preceding claims, characterized in that the systematic bits (S) and the parity bits (Pl, P2) are supplied to a bit rate adaptation device (3) which has a first bit stream with bits to be mapped onto the bit positions with high reliability and one outputs a second bit stream with bits to be mapped to the bit positions with the lower reliability, the first bit stream before the mapping of the corresponding bits onto the modulation symbols of a first interleaver (4a) and the second bit stream before the mapping of the corresponding bits onto the modulation symbols of a second interleaver ( 4b) is fed.

9. The method according to claim 8, characterized in that a bit is alternately read from the first interleaver (4a) for mapping to a bit position with the high reliability and a bit from the second interleaver (4b) for mapping to a bit position with the lower reliability.

10. The method according to claim 8 or 9, characterized in that the systematic bits (S) are subjected to an algorithm (14) which bit by bit the systematic bits (S) either the first bit stream or one with the parity bits (Pl, P2) assigns second bit stream to be combined bit stream.

10. The method according to claim 8 or 9, characterized in that the parity bits (Pl, P2) are subjected to an algorithm (19, 20) which the parity bits (Pl, P2) bit by bit either with the systematic bits (S) to the first Assigns the bit stream to be combined or the second bit stream.

11. The method according to claim 10, so that the systematic bits (S) are subjected to a bit rate adaptation (26) before they are combined with the parity bits (Pl, P2) assigned to the first bit stream by the algorithm (19, 20).

12. The method according to any one of claims 8-11, characterized in that the bits of the first bit stream and the bits of the second bit stream offset with respect to one another from the first interleaver (4a) and the second interleaver (4b) for mapping to the corresponding bit positions the modulation symbols (13) can be read out.

13. The method according to claim 12, characterized in that the bit of the second bit stream, which is written into the second interleaver (4b), is to be mapped onto the modulation symbols (13) in the central region and is to be emitted from the first and second interleaver (4a, 4b) Bits is read out.

14. The method according to claim 12 or 13, characterized in that the first bit of the second bit stream written into the second interleaver (4b) is read out in the middle of the two bits of the first bit stream which are immediately before and after this bit in the first interleaver (4a) have been written.

15. The method according to any one of claims 8-14, characterized in that a block interleaver is used as the first and second interleaver (4a, 4b), the corresponding bits being written into the block interleaver in columns, the columns subsequently exchanged in accordance with a predetermined column exchange scheme and the then written bits can be read out line by line.

16. The method according to claim 15, so that the order of the columns to be described is shifted relative to one another when the bits are written into the first and second interleaver (4a, 4b).

17. The method according to claim 15 or 16, characterized in that before reading out the bits written in each of the first and second interleaver (4a, 4b) the order the columns in the first and second interleaver (4a, 4b) are shifted towards each other.

18. The method according to any one of claims 15-17, so that the order of the lines in the first and second interleaver (4a, 4b) is shifted relative to one another before the bits are read out.

19. The method according to any one of claims 15-18, so that the column interchanging scheme of the first interleaver (4a) and the column interchanging scheme of the second interleaver (4b) are different.

20. Communication device for transmitting a bit stream over a transmission channel, with a channel encoder (2) for channel coding of the bits to be transmitted, the channel-coded bits being in the form of systematic bits (S) and parity bits (P1, P2), with one after the channel encoder (2) arranged bit rate adjustment device (3), with an interleaver device (4a, 4b) arranged after the bit rate adjustment device (3), and with a modulator (5) arranged after the interleaver device (4a, 4b) for transmitting the bit rate adjustment device (3) and the interleaver (4a, 4b) processed systematic bits (S) and parity bits (Pl, P2) on bit positions of modulation symbols (13), which have different reliabilities with respect to the transmission, as characterized by the bit rate adaptation device (3), the interleaver device (4a, 4b) and the modulator (5) are designed such that the systematic bits (S) on bit positions of the modulation symbols (13) with high reliability and, if the number of bit positions with the high reliability reliability is not sufficient, are mapped to bit positions with a lower reliability, while the parity bits (Pl, P2) on the remaining bit positions with the lower reliability after a corresponding bit rate adjustment (15, 16; 21) has been carried out based on the parity bits (Pl, P2) , 22) are shown.

21. Communication device according to claim 20, so that the communication device (1) or the bit rate adaptation device (3), the interleaver device (4a, 4b) and the modulator (5) is designed to carry out the method according to one of claims 1-19.

22. Communication device according to claim 20 or 21, so that the communication device is a mobile radio transmitter.

23. Communication device according to one of claims 20-22, characterized in that the bit rate adaptation device (3) is designed such that it includes the systematic bits (S) and the parity bits (Pl, P2) in a first bit stream to the bit positions with the high Reliability to be mapped bits and a second bit stream with bits to be mapped to the bit positions with the lower reliability, and that the interleaver means a first interleaver (4a) to which the first bit stream is fed and a second interleaver (4b) to which the second bit stream is fed is included.

24. Communication device according to claim 23, characterized in that the bit rate adaptation device (3) comprises a mapping device (14) for bitwise assigning the systematic bits (S) either to the first bit stream or to one the parity bits (Pl, P2) to the second bit stream to be combined.

25. Communication device according to claim 24, characterized in that the bit rate adaptation device (3) has a device (15, 16) for adapting the bit rate of the parity bits (Pl, P2) before these with the corresponding from the mapping device (14) to the second Systematic bits assigned to the bit stream can be combined to form the second bit stream.

26. Communication device according to claim 23, so that the bit rate adaptation device (3) comprises a mapping device (19, 20) for bitwise assignment of the parity bits

(P1, P2) either to a bit stream to be combined with the systematic bits (S) to the first bit stream or to the second bit stream, and that the bit rate adaptation device (3) has a device (21, 22) for adapting the bit rate of the parity bits ( Pl, P2).

27. Communication device according to claim 26, so that the device (21, 22) for adapting the bit rate of the parity bits (P1, P2) is arranged after the mapping device (19, 20).

28. Communication device according to claim 26, so that the device (21, 22) for adapting the bit rate of the parity bits (P1, P2) is arranged in front of the mapping device (19, 20).

29. Communication device according to one of claims 26-28, characterized in that the bit rate adaptation device (3) has a device (26) for adapting the bit rate of the systematic bits (S) before this with the corresponding parity bits (Pl, P2) assigned to the first bit stream by the mapping device (19, 20) can be combined to form the first bit stream.

30. Communication device for receiving a bit stream transmitted via a transmission channel, so that the communication device is designed for receiving and evaluating a bit stream transmitted by a communication device according to one of claims 20-29.

31. Communication device according to claim 30, so that the communication device is a mobile radio receiver.