WO2003038792A2

WO2003038792A2 - Controlling data dependence and cross-talk between display elements

Info

Publication number: WO2003038792A2
Application number: PCT/US2002/032986
Authority: WO
Inventors: Douglas J. Mcknight; Bruce A. Doyle
Original assignee: Three-Five Systems, Inc.
Priority date: 2001-10-30
Filing date: 2002-10-15
Publication date: 2003-05-08
Also published as: WO2003038792A3; AU2002340231A1

Abstract

Methods, apparatuses, and computer readable media for reducing the effects of parasitic capacitance and current leakage on displayed data are disclosed. In one embodiment, a method includes loading data onto at least two display elements and controlling a potential of a column line subsequent to loading the data during a view period. Various embodiments may be directed to time sequential displays as well as spatial displays.

Description

CONTROLLING DATA DEPENDENCE AND CROSS-TALK BETWEEN DISPLAY

ELEMENTS

BACKGROUND OF THE INVENTION FIELD OF INVENTION

[0001] This invention relates generally to displays used to display data, and more particularly to controlling parasitic capacitance effects, data dependence and cross talk between display elements.

ART BACKGROUND

[0002] Active matrix displays, used to display both gray scale and color data, in which the data is loaded into a pixel storage element in an analogue fashion suffer from two problems related to column-wire coupled artifacts. These problems are undesirable and affect the image quality of the display. Both problems are a result of the non-ideal properties of the active matrix substrate used to form the display elements. Both problems are apparent in displays constructed using CMOS processes to create liquid crystal on silicon micro-displays. Both problems are apparent in displays constructed with other semiconductor manufacturing processes due to the non-ideal properties of physical devices. [0003] The first problem is due to undesirable parasitic capacitance existing between metal layers in a semiconductor, which is common to all CMOS processes. The data loaded to a display element is stored on a capacitor at the display element. The circuitry used to load the data to the capacitor has parasitic capacitance associated with it. Distortion of the data loaded to the display element capacitor occurs due to a capacitive division from a storage node to a virtual supply plane.

[0004] The second problem is due to the non-ideal switch characteristics found in transistors such as MOS transistors or thin film transistors (TFTs). A transistor is typically used as a switch to load data onto a storage element where the data is stored as charge on a capacitor (display element capacitor). Once loading is complete the transistor is switched to an "off state. In this off state the non-ideal transistor still has the ability to conduct a small amount of current. As this current is conducted through the transistor in the off state cross talk occurs between display elements that share a common column line. The cross talk creates a data dependent residual effect on the image displayed on the display elements that is undesirable.

[0005] What is needed is a way to remove the problems resulting from parasitic capacitance and current leakage within display devices that are constructed with real world non-ideal materials.

SUMMARY OF THE INVENTION

[0006] Methods, apparatuses, and computer readable media for reducing the effects of parasitic capacitance and current leakage on displayed data are disclosed.

[0007] Embodiments of the invention include methods of loading data onto at least two display elements, and controlling a potential of a column line subsequent to loading the data during a view period. In one embodiment, a method includes loading data onto display elements wherein the potential of the column line is chosen to minimize leakage to a display element in a dark state. The potential of the column line may be chosen based on data displayed in a sub-frame, during a view period, subsequent to loading data.

[0008] A computer readable medium containing executable program instructions, which when executed by a data processing system, cause the data processing system to perform a method including loading data onto at least two display elements and controlling a potential of a column line subsequent to said loading during a view period wherein the potential of the column line is chosen based on the data displayed in a sub-frame.

[0009] In one embodiment an apparatus includes: a first row line; a first display element coupled with the first row line; a second row line; a second display element coupled with the second row line; a column line coupled with the first display element and the second display element to allow data to be loaded sequentially by row or by column to the first display element and the second display element. A potential of the column line is controlled during a view period subsequent to loading the data.

[0010] Embodiments may be directed to time sequential color displays as well as spatial color displays, and monochrome displays such as those used in three-panel projector systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention is illustrated by way of example and is not limited in the figures of the accompanying drawings, in which like references indicate similar elements.

[0012] Figure 1 is an array of display elements.

[0013] Figure 2 is a diagram of a display element cell illustrating a secondary capacitance.

[0014] Figure 3 contains relationships used to estimate a value of a change in display element voltage due to secondary (parasitic) capacitance.

[0015] Figure 4 graphs a change in voltage occurring on display elements in row 1.

[0016] Figure 5 is a comparison of data dependent (Last row dependence) and non-data dependent display of data on display elements in row 1.

[0017] Figure 6 depicts minimizing leakage to display elements in a dark state by controlling the column line potential.

[0018] Figure 7 shows a view period of a time-sequential display.

[0019] Figure 8 depicts display elements in a spatial color display.

DETAILED DESCRIPTION

[0020] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings in which like references indicate similar elements, and in which is shown by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the invention is defined only by the appended claims.

[0021] In one embodiment, a display for viewing data may be constructed using an array of display elements arranged in a series of rows and columns as shown in Figure 1. With reference to Figure 1, the display 100 is configured by coupling DEll, DE 21, DE 31 with column line 110. In a similar way DE 12, DE 22, and DE 32 are coupled with column line 120 and DE 13, DE 23, and DE 33 are coupled with column line 130. Thus, each column of display elements shares a common column line. [0022] Row lines are similarly distributed to the display elements. Row line 10 is coupled with DE 11, DE 12, and DE 13. Row line 20 is coupled with DE 21, DE 22, and DE 23. Row line 30 is coupled with DE 31, DE 32, and DE 33. Each row of display elements shares a common row line.

[0023] In one embodiment, data is loaded to display 100 a row at a time. Control circuits may be used to drive the row wires that switch the display element transistors on and off. In one embodiment, all the row lines 10, 20 and 30 are in a low voltage state. Data intended to be loaded on row 1 (represented by row line 10), in the form of voltages, is placed on the column lines 110, 120 and 130. The data is sampled and held on DE 11, DEI 2, and DEI 3 under the control of row line 10, which is pulsed high, and then low if the display element sampling transistor is an n-MOSFET. When the row line 10 goes low the n- MOSFET is switched off, sampling the data onto the display element storage capacitor. If the display element column-access device is a p-MOSFET then the logic of the row signal is inverted. These steps are repeated in order to load data onto the display elements coupled with row 2 (represented by row line 20) and the display elements coupled with row line 3 (represented by row line 30).

[0024] In typical displays, the data is left on the column lines after the display elements in the last row sample the data for their row. In the example represented in Figure 1, the voltages representing the data loaded onto DE 31, DE 32, and DE 33 are left on column line 110, column line 120 and column line 130 respectively. In prior art displays; display element data from the last row creates an undesirable visual effect that is observed on the display due to the problems previously mentioned. As an example, if a uniform gray background is loaded onto the display 100 and the data for DE 32 (in the last row to load) called for DE 32 to be black, a weak dark band would appear to extend upward and be visible on DE 22 and DE 12.

[0025] In one embodiment, using the CMOS semiconductor manufacturing process a main display element storage capacitance is constructed with a MOS-FET. A secondary or parasitic capacitance is created between the metal2 and metal3 layers within a semiconductor. Figure 2 is a diagram of a display element cell 200 illustrating the secondary capacitance problem. With reference to Figure 2, a display element mirror 204 is formed at the metal3 level of the semiconductor substrate. A column line 202 is formed in the metal two layer of the semiconductor. The necessary gap between display element mirror 204 and the column line 202 forms a secondary capacitance gap 210. The secondary capacitance is created by the necessity to create individual metal layers within display element cell 200 and exists between each column line and the display elements coupled therewith.

[0026] Returning to the case where gray scale data was loaded to display 100 (Figure 1). With respect to the problem of parasitic capacitance. The previously described condition (Figure 2) causes the gray scale data (voltage value) loaded to the display element capacitor 208 to be influenced by the secondary capacitance gap 210, thereby changing the resultant voltage developed on the display element. The final undesirable effect of this problem is to shift the data values (voltages) of the colors displayed on display 100 (Figure 1), which causes a corresponding shift in displayed color corrupted by the data displayed to the last row of display 100.

[0027] It will be appreciated by those skilled in the art that use of the terms column and row are arbitrary labels. The previous discussion of the architecture of the semiconductor used to load data onto display elements would work equally well if the designation of row and column were reversed. The invention is not limited by these designations. It will also be appreciated by those of skill in the art that it is anticipated that the invention will find application beyond the particular semiconductor display architecture described herein. The discussion directed to Figure 2 and the detailed views presented in Figure 6 are but one example of a circuit in which the invention will find application.

[0028] Figure 3 contains relationships used to estimate a change in display element voltage due to secondary (parasitic) capacitance for a display element. The expressions listed in Figure 3 are applicable to display elements that share a common column line. In one embodiment, the display element may be referred to as a pixel. With reference to Figure 3, a change in voltage at a pixel, indicated as ΔVpixel is given by the expression in 305. Vcolumn at 325 represents a voltage left on a column line as a result of loading a last row of data to pixels on the last row. Vpixel at 320 is a voltage value written to a pixel based on data displayed to the pixel. Cparasitic at 315 is a value of the undesirable capacitance due to secondary capacitance gap 210 (Figure 2) that results from column to pixel coupling. Cpixel shown at 310 is the design capacitance of the pixel. A resultant voltage at the pixel is given by Vresultant at 330.

[0029] A noticeable change in displayed data can occur when the parasitic capacitance is 2 femto farads (fF). For example: Vpixel = 3.81 volts; Vcolumn = 0.0 volts; Cpixel = 150fF; Cparasitic = 2 fF

Which creates a value for Vpixel of -0.051 volts using 305 in Figure 3. In an 8 bit display system -0.051 volts corresponds to an amplitude change of 3.4 bits of dynamic range. Those of skill in the art will appreciate that amplitude changes of 2 bits in dynamic range are perceptible to the human eye. It should be noted that this change in magnitude occurs at each pixel on the display and will vary depending on the data left on the column wires after writing the last row of pixels.

[0030] The problem is further illustrated with reference to Figure 4 by analyzing a row that includes four (4) columns. Figure 4 graphs the change in voltage occurring on four display elements in row 1 of a display that includes at least two rows. It is appreciated by those of skill in the art that data and voltage may be used interchangeably. However, for clarity, in this example pertaining to Figure 4 and Figure 5, data written to the display elements will be referred to as voltages. With reference to Figure 4, voltages loaded to row 1 of the display are plotted in 400 and correspond to the definition of Vpixel at 320 in Figure 3. 410 is plotted on the vertical axis and columns 412 are indicated on the horizontal axis in 400. A constant voltage value has been loaded to the display elements in row 1 and is indicated by value 401 corresponding to a display element 1 in column 1, value 402 corresponding to a display element 2 in column 2, value 403 corresponding to a display element in column 3, and value 404 corresponding to a display element in column 4. [0031] A set of voltages loaded to a last row of the display are plotted in 440 as Vcolumn (results from last row of data) 450 on the vertical axis, and correspond to the definition of Vcolumn at 325 in Figure 3. These voltage values have been arbitrarily chosen to decrease as shown from column 1 to column 4 in 440. A voltage value loaded to a display element in column 1 of the last row of the display is indicated by value 421, a voltage value loaded to a display element in column 2 of the last row of the display is indicated by value 422, a voltage value loaded to a display element in column 3 of the last row of the display is indicated by value 423, and a voltage value loaded to a display element in column 4 of the last row of the display is indicated by value 424. [0032] ΔVpixel corresponding to a display element in row 1, column 1, of the display (defined at 305 in Figure 3) is computed by subtracting value 421 from value 401 and multiplying by the appropriate capacitance ratio. The resultant voltage is plotted in 470 as value 481. A "C" is used to label a vertical axis ΔVpixel (row 1) 480 in 470. The "C" represents the capacitance ratio Cparasitic/Cpixel as shown in 305 (Figure 3). Similarly, the change in voltages (ΔVpixel) corresponding to the rest of the columns in row 1 are computed in a similar way and are displayed in 470 for column 2, 3, and 4, as value 482, value 483, and value 484 respectively.

[0033] Figure 5 is a comparison of data dependent (last row dependence) 500 and non- data dependent 550 display of data on display elements in row 1 of the display. With reference to Figure 5, the resultant voltages existing on the display elements in row 1, of the display are shown in 500. The resultant voltage residing on the display element in row 1, column 1, is computed according to 330 (Figure 3) by subtracting value 481 (Figure 4) from value 401 (Figure 4) and is plotted in Figure 5 as value 511. Similar calculations produce resultant voltage value 512 for the display element in row 1, column 2 of the display; resultant voltage value 513 for the display element in row 1, column 3 of the display; and resultant voltage value 514 for the display element in row 1, column 4 of the display. It will be noticed that the resultant voltages residing on the display elements in 500 have a data dependent character influenced by the data loaded to the last row of the display as shown by values 421, 422, 423, and 424 in 440 (Figure 4).

[0034] Returning to Figure 4 at 440, the invention corrects the data dependent resultant voltage by controlling the potential of the column lines following the load of the last row of data. The potential of the column lines is controlled before the next pixel data are loaded to the column lines. Which pixel data drives a display element, such as a pixel, to cause the appearance of an image based on the pixel data. Controlled potential 460 is plotted as a constant level on all the column lines of the display. Controlled potential 460 is subtracted from values 401, 402, 403, and 404 to create constant ΔVpixel 490 values for the display elements in row 1 of the display as shown in 470. Constant ΔVpixel 490 values are subtracted from values 401, 402, 403, and 404 using equation 330 (Figure 3) to produce data independent resultant voltage 560 in Figure 5 plotted in 550. By controlling the potential of the column lines subsequent to loading the last row of data, the data dependent artifact resulting from unwanted parasitic capacitance, evident in 500, has been eliminated from the data displayed in 550. The same result is achieved for the other rows in the display (not shown).

[0035] The choice of the magnitude for controlled potential 460 is flexible. One level was chosen in the example described in conjunction with Figure 4 and Figure 5. Many other choices would work equally well. A mid point of the full-scale voltage range for display elements of a display has been found to produce successful results by eliminating the data dependent character resulting from unwanted parasitic capacitance. What is important is that the level of the potential chosen be one which does not induce an visually objectionable artifact. The preferred choice is where the potentials chosen are substantially equal on all the column lines of the display. This criterion prevents the potentials of the column lines from causing a column related "stripe" artifact, and is straightforward to implement. Many different selections are possible of the potential used to control the column lines subsequent to loading data. For example, the column wires could be set to potentials that gradually vary across the screen. This would induce a gradually varying capacitively-induced offset which, though not ideal, would in most circumstances not be visible and which would prevent the data-dependent artifacts that are visually objectionable. The present invention is not limited by the level selected for control of the potential of the column lines during a "view period." "View period" will be described below in conjunction with Figure 7.

[0036] It may be desirable to control the potential of the column lines so that the effects of leakage through the MOSFET are minimized subsequent to loading data to the display elements. Two display elements from the display 100 of Figure 1 are shown in more detail in Figure 6 in 150. Figure 6 depicts minimizing leakage to display elements in a dark state by controlling the column line potential. With reference to Figure 6, a leakage current 636 is shown between two display elements in 150. Another term that is used in the art for this effect of current leakage is cross talk.

[0037] In one embodiment, the components of DE 11 (Figure 1) are shown in more detail in 150 (Figure 6). A DE capacitor 611a is coupled with the row line 10, a DE MOSFET 611b is coupled with the DE capacitor 611a and the column line 110 is coupled with the DE MOSFET 61 lb. Similarly, DE 21 includes a DE capacitor 621a coupled with the row line 20, a DE MOSFET 621b coupled with the DE capacitor 621a and the column line 110 coupled with the DE MOSFET 621b. [0038] The DE shown in 150 (Figure 6) is suitable for controlling a liquid crystal layer, which is controlled by the voltages applied to electrodes that are connected to the storage capacitors at a node 632 and a node 634. Other DE designs may include extra circuitry that operates on this stored voltage, such as amplifiers, voltage followers or subsequent storage stages. Another example of the DE could contain several storage capacitors connected to several column wires by transistors under the control of a shared row wire in order to sample simultaneously red, green, and blue color data. Another example of the DE is one in which the column signal sampled by the DE may be used to control a circuit that drives a current instead of a voltage. Such a DE could be used to drive a pixel of a LED based display such as an organic LED display. Another example of the DE is one in which the column wire voltage sampled by the DE is used to control the time at which the DE electrode is switched in a pulse-width modulated display. It should be understood that these example DEs are only a small subset of all the possible configurations of DE that include the fundamental circuit elements and methods required to sample a column-wire voltage onto the DE storage capacitor (either explicit or implicit).

[0039] The state of the display devices depicted in 150 is such that the data has been loaded to the display devices and the display devices are in the "view period" in which a user views the display. The potential of the column line 110 is floating following loading the data to the display devices as indicated by floating 630. The display device may be configured so that 3.81 volts at the node 632 places DE 11 in "dark" state (black for this example). At the node 634, zero (0) volts places DE 21 in a "bright" state (white for this example). Zero (0) and 3.81 volts have been arbitrarily chosen for this example. The actual voltage levels that correspond to "dark" and "bright" states will depend on a particular display device. The DE MOSFET 611b and the DE MOSFET 621b may exhibit non-ideal characteristics in which the leakage current 636 flows from the DE MOSFET 611b to the DE MOSFET 621b. The result on the leakage current 636 flowing as described will be to make DE 11 appear less black than it should appear based on the potential corresponding to the loaded data. If a DE appears slightly less black than it should, this is more detrimental than a DE that appears slightly less bright than it should. The reason for this is because a small change in the dark state has a significant, and perhaps large, effect on the contrast ratio of the display (I_bright/I_dark), whereas a small change in the bright state causes only a small change in the contrast ratio. This reduction in quality of the dark state is a noticeable and undesirable effect that is eliminated by the present invention. [0040] In another embodiment, zero (0) volts can indicate a display device in a "dark" state and 3.81 volts can indicate a display device in a "bright" state, as previously mentioned. No limitation is implied by the use of a particular voltage to indicate the state of the display device. Nor is any limitation implied by the use of the range zero to 3.81 volts, the range depends on the design parameters of the display device.

[0041] The effect of the leakage current 636 may be reduced below noticeable levels by controlling a potential of the column line 110 as shown in 150a. The state of the display devices depicted in 150a is the same as 150 in that data has been loaded to the display devices and the display devices are in a view period in which a user views the display, however a potential of the column line 110 is being controlled. A potential of the column line 110 may be controlled to minimize leakage current 636 to display elements in a "dark" state. In this example, the potential of the column line 110 is being controlled at 3.81 volts as depicted at 660. Since the potential of the column line 110 is 3.81 volts in 150a, there is no potential difference across DE MOSFET 611b that would allow current to flow, thereby reducing the voltage at node 632 from 3.81 volts. The "dark" state of DE 11 is maintained by maintaining the potential of node 632 at 3.81 volts in 150a.

[0042] The previous discussion directed to Figure 6 has involved the simple case of two display elements, one column line and two row lines. The invention may be applied to a display of arbitrary size including a large number of row lines and column lines. Typical displays may include 768 rows by 1024 columns. The invention is not limited by display size. When implementing the invention in a display with multiple columns (which is the case with most practical displays) it has been found that best results are achieved when the potential of all the column lines are controlled similarly. Thus, it would be desirable to control all (or substantially all) of the column lines by bringing their potential to the voltage corresponding to the dark state. In the example discussed in Figure 6 this voltage is 3.81 volts, but different display modes, or indeed the display described above at a different time in its drive scheme can have a different voltage, such as zero (0) volts, corresponding to the dark state.

[0043] It is anticipated that the invention will be applied to a variety of displays. The invention is applicable to a time-sequential display. Figure 7 shows one embodiment of a view period of a time-sequential display. With reference to Figure 7, color data is displayed sequentially in time using the same display element. For example, the primary colors of red, green, and blue have been chosen as shown in 700. The color components of a data frame are divided into sub-frames. Time is displayed on a horizontal axis at 730. In the example of Figure 7, a red sub-frame 702 is followed in time by a green sub-frame 710, which is followed by a blue sub-frame 720. The sub-frames repeat for the next frame of data (not shown). Display data 740 may indicate columns or rows of data. The data for a frame of the display may be loaded from a first row to a last row or from the last row to the first row or in an arbitrary row order. No limitation is imposed on the invention by the order in which data is loaded to the display.^'

[0044] Each sub-frame is divided into three parts. The parts of a sub-frame perform the functions of loading data, settling data, and viewing data. The red sub-frame 702 has an R- data load 704 part, an R-settle 706, part and an R-view 708 part. Similarly, the green sub- frame 710 has a G-data load 714 part, a G-settle 716 part, and a G-view 718. Only the blue sub-frame 720 B-data load 724 part is shown. The previous discussion of reducing the effect of leakage current on the dark state, and reducing the amount of cross talk between display elements (Figure 6) may be applied to the time sequential display of 700 within each view period. For example, with application to the red sub-frame, the "dark" state may indicate the point in time when black is displayed and the "bright" state may indicate the point in time when the display element is red during the view period indicated as R-view 708. Referring back to Figure 6, the potential of the column line 110 is controlled as required to prevent the leakage current 636 from flowing during the view period which would reduce the constant between displaying elements in the "dark" state and display elements in the "bright" state on the same column line. Similarly, the potential of column line 110 would be controlled during the view period for green, indicated by G-view 718 (Figure 7), and a view period for blue (not shown in Figure 7).

[0045] In another embodiment, the invention may be employed in a spatial color display as shown in Figure 8. Figure 8 depicts a display element of a spatial color display 810. The spatial display element 810 includes a red spatial display element (SDE) 812, a green SDE 814, and a blue SDE 816. In one embodiment, the red, blue, and green data is simultaneously displayed to the SDE 810. The invention may be employed simultaneously on each of the color elements red SDE 812, green SDE 814, and blue SDE 816, rather than sequentially in time as discussed previously.

[0046] Although the invention has been described in the context of a CMOS liquid crystal on silicon micro display, it is anticipated that the invention will be applied to displays manufactured with other semiconductor process. For example, the invention will find application to poly-silicon transmissive displays. Application to a poly-silicon transmissive display would allow a display to be designed with greater parasitic capacitance between the display element and the column line, for example, without the displayed data being susceptible to the undesirable effects of parasitic capacitance and leakage currents discussed earlier.

[0047] It is anticipated that the invention will find application in a variety of displays used to display data. A nonexclusive list of anticipated displays are displays situated proximate to the eye, a hand-held computer display, a lap-top computer display, a camera display, a video camera display, a desk top computer display, and a vehicular display. Vehicular displays include, but are not limited to displays for automobiles, airplanes, boats and any other vehicle where it is desirable to display data. Vehicular displays may be used to display operating parameters of the vehicle such as speed fuel level, etc. or full motion video data.

[0048] Use herein of the term "data" is intended to be expansive and is not intended to place limitations on the invention. Therefore "data" as previously mentioned has been used interchangeably with voltage or potential to indicate an electrical signal that produces an effect in the display device that is observable by the user. It is anticipated that the invention will be applied to a wide range of different kinds of displays as well as a wide range of different kinds of visual information displayed thereon.

[0049] It will be appreciated that the methods described in conjunction with the figures may be embodied in machine-executable instructions, e.g. software. The instructions can be used to cause a general-purpose or special-purpose processor that is programmed with the instructions to perform the operations described. Alternatively, the operations might be performed by specific hardware components that contain hardwired logic for performing the operations, or by any combination of programmed computer components and custom hardware components. The methods may be provided as a computer program product that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer (or other electronic devices) to perform the methods. For the purposes of this specification, the terms "machine-readable medium" shall be taken to include any medium that is capable of storing or encoding a sequence of instructions for execution by the machine and that cause the machine to perform any one of the methodologies of the present invention. The term "machine-readable medium" shall accordingly be taken to included, but not be limited to, solid-state memories, optical and magnetic disks, and carrier wave signals. Furthermore, it is common in the art to speak of software, in one form or another (e.g., program, procedure, process, application, module, logic...), as taking an action or causing a result. Such expressions are merely a shorthand way of saying that execution of the software by a computer causes the processor of the computer to perform an action or a produce a result.

[0050] Thus, a display is disclosed which does not produce data dependent cross talk across display elements attached to a common column line. Additionally, techniques are disclosed which minimize parasitic capacitance effects on displayed data. Although the invention is described herein with reference to specific preferred embodiments, many modifications therein will readily occur to those of ordinary skill in the art. Accordingly, all such variations and modifications are included within the intended scope of the invention as defined by the following claims.

Claims

1. A method comprising: loading data onto at least two display elements; and controlling a potential of a column line subsequent to said loading during _. a view period.

2. The method of claim 1, wherein the potential of the column line is controlled for an amount of time substantially as long as an amount of time the at least two display elements are in a view state and wherein said controlling occurs before next pixel data are applied to the column line.

3. The method of claim 1, wherein the at least two display elements are configured to be used in a time-sequential display. .

4. The method of claim 1, wherein the at least two display elements are configured to be used in a spatial color display.

5. The method of claim 1, wherein at least one of the at least two display elements is a pixel.

6. The method of claim 5, wherein the pixel is a light emitting diode (LED).

7. The method of claim 1, wherein an Nchannel MOSFET is used to load the data onto a capacitor associated with a display element.

8. The method of claim 1, wherein the at least two display elements are constructed utilizing a CMOS process.

9. The method of claim 1 wherein the potential of the column line is configured to be held at a substantially constant potential, subsequent to said loading during the view period.

10. The method of claim 1, wherein the column line is maintained at a substantially fixed potential after the data is substantially loaded to the at least two display elements.

11. A method comprising: loading data onto at least two display elements; and controlling a potential of a column line subsequent to said loading during a view period wherein the potential of the column line is chosen to minimize leakage to a display element in a dark state.

12. The method as set forth in claim 11, wherein the potential of the column line is controlled for an amount of time substantially as long as an amount of time the at least two display elements are in a view state and wherein the potential of the column line is controlled before next pixel data is applied to the column line.

13. The method as set forth in claim 11, wherein the at least two display elements are configured to be used in a time-sequential display.

14. The method as set forth in claim 11, wherein the at least two display elements are configured to be used in a spatial color display.

15. The method as set forth in claim 11, wherein at least one of the at least two display elements is a pixel.

16. The method as set forth in claim 15, wherein the pixel is a light emitting diode (LED).

17. The method as set forth in claim 11, wherein an Nchannel MOSFET is used to load the data onto a capacitor associated with a display element.

18. The method as set forth in claim 11, wherein the at least two display elements are constructed utilizing a CMOS process.

19. The method as set forth in claim 11, wherein the potential of the column line is configured to be held at a substantially constant potential, subsequent to said loading during the view period.

20. The method as set forth in claim 11, wherein the column line is maintained at a substantially fixed potential after the data is substantially loaded to the at least two display elements.

21. An method, comprising: loading data onto at least two display elements; and controlling a potential of a column line subsequent to said loading during a view period wherein the potential of the column line is chosen based on the data displayed in a sub-frame.

22. The method as set forth in claim 21, wherein the potential of the column line is controlled for an amount of time substantially as long as an amount of time the at least two display elements are in a view state.

23. The method as set forth in claim 21, wherein the at least two display elements are configured to be used in a time-sequential display.

24. The method as set forth in claim 21, wherein the at least two display elements are configured to be used in a spatial color display.

25. The method as set forth in claim 21, wherein at least one of the at least two display elements is a pixel.

26. The method as set forth in claim 25, wherein the pixel is a light emitting diode (LED).

27. The method as set forth in claim 21, wherein an Nchannel MOSFET is used to load the data onto a capacitor associated with a display element.

28. The method as set forth in claim 21, wherein the at least two display elements are constructed utilizing a CMOS process.

29. The method as set forth in claim 21 wherein the potential of the column line is configured to be held at a substantially constant potential, subsequent to said loading during the view period.

30. The method as set forth in claim 21, wherein the column line is maintained at a substantially fixed potential after the data is substantially loaded to the at least two display elements.

31. A computer readable medium containing executable program instructions, which when executed by a data processing system, cause the data processing system to perform a method comprising: loading data onto at least two display elements; and controlling a potential of a column line subsequent to said loading during a view period.

32. A computer readable medium containing executable program instructions, which when executed by a data processing system, cause the data processing system to perform a method comprising: loading data onto at least two display elements; and controlling a potential of a column line subsequent to said loading during a view period wherein the potential of the column line is chosen to minimize leakage to pixels in a dark state.

33. A computer readable medium containing executable program instructions, which when executed by a data processing system, cause the data processing system to perform a method comprising: loading data onto at least two display elements; and controlling a potential of a column line subsequent to said loading during a view period wherein the potential of the column line is chosen based on the data displayed in a sub-frame.

34. An apparatus comprising: a first row line; a first display element coupled with said first row line; a second row line; a second display element coupled with said second row line; a column line coupled with said first display element and said second display element to allow data to be loaded sequentially by row or by column to said first display element and said second display element; and a column line driver coupled with said column line, said column line driver controlling a potential of said column line, during a view period subsequent to loading the data wherein the potential is different than the potential used to load the data to a display element coupled with said column line and a last row line.

35. The apparatus of claim 34, wherein the potential of said column line is applied for an amount of time substantially as long as an amount of time said at least two display elements are in a view state.

36. The apparatus of claim 34, wherein said at least two display elements are configured to be used in a time-sequential display.

37. The apparatus of claim 34, wherein said at least two display elements are configured to be used in a spatial color display.

38. The apparatus of claim 34, wherein at least one of said at least two display elements is a pixel.

39. The apparatus of claim 38, wherein the pixel is a light emitting diode (LED).

40. The apparatus of claim 34, wherein an Nchannel MOSFET is used to load the data onto a capacitor associated with a display element.

41. The apparatus of claim 34, wherein said at least two display elements are constructed utilizing a CMOS process.

42. The apparatus of claim 34, wherein a potential of said column line is configured to be held at a substantially constant potential, during the view period subsequent to loading the data.

43. The apparatus of claim 34, wherein said column line is maintained at a fixed potential after the data is substantially loaded to an array of display elements.

44. The apparatus of claim 34, further comprising a display incorporating said at least two display elements.

45. The apparatus of claim 44, wherein said display is selected from the group consisting of a display situated proximate to the eye, a cellular telephone display, a hand-held computer display, a lap-top computer display, a camera display, a video camera display, and a desk top computer display.

46. An apparatus comprising: a first row line; a first display element coupled with said first row line; a second row line; a second display element coupled with said second row line; and a column line coupled with said first display element and said second display element to allow data to be loaded sequentially by row or by column to said first display element and said second display element, wherein a potential of said column line is configured to minimize leakage to a display element in a dark state during a view period subsequent to loading the data.

47. The apparatus of claim 46, wherein the potential of said column line is applied for an amount of time substantially as long as an amount of time said at least two display elements are in a view state.

48. The apparatus of claim 46, wherein said at least two display elements are configured to be used in a time-sequential display.

49. The apparatus of claim 46, wherein said at least two display elements are configured to be used in a spatial color display.

50. The apparatus of claim 46, wherein at least one of said at least two display elements is a pixel.

51. The apparatus of claim 50, wherein the pixel is a light emitting diode (LED).

52. The apparatus of claim 46, wherein an Nchannel MOSFET is used to load the data onto a capacitor associated with a display element.

53. The apparatus of claim 46, wherein said at least two display elements are constructed utilizing a CMOS process.

54. The apparatus of claim 46, wherein a potential of said column line is configured to be held at a substantially constant potential, during the view period subsequent to loading the data.

55. The apparatus of claim 46, wherein said column line is maintained at a fixed potential after the data is substantially loaded to an array of display elements.

56. The apparatus of claim 46, further comprising a display incorporating said at least two display elements.

57. The apparatus of claim 56, wherein said display is selected from the group consisting of a display situated proximate to the eye, a cellular telephone display, a hand-held computer display, a lap-top computer display, a camera display, a video camera display, and a desk top computer display.

58. An apparatus comprising: a first row line; a first display element coupled with said first row line; a second row line; a second display element coupled with said second row line; and a column line coupled with said first display element and said second display element to allow data to be loaded sequentially by row or by column to said first display element and said second display element, wherein a potential of said column line is chosen based on the data displayed in a sub-frame.

59. The apparatus of claim 58, wherein the potential of said column line is applied for an amount of time substantially as long as an amount of time said at least two display elements are in a view state.

60. The apparatus of claim 58, wherein said at least two display elements are configured to be used in a time-sequential display. .

61. The apparatus of claim 58, wherein said at least two display elements are configured to be used in a spatial color display.

62. The apparatus of claim 58, wherein at least one of said at least two display elements is a pixel.

63. The apparatus of claim 62, wherein the pixel is a light emitting diode (LED).

64. The apparatus of claim 58, wherein an Nchannel MOSFET is used to load the data onto a capacitor associated with a display element.

65. The apparatus of claim 58, wherein said at least two display elements are constructed utilizing a CMOS process.

66. The apparatus of claim 58, wherein a potential of said column line is configured to be held at a substantially constant potential, during the view period subsequent to loading the data.

67. The apparatus of claim 58, wherein said column line is maintained at a fixed potential after the data is substantially loaded to an array of display elements.

68. The apparatus of claim 58, further comprising a display incorporating said at least two display elements.

69. The apparatus of claim 68, wherein said display is selected from the group consisting of a display situated proximate to the eye, a cellular telephone display, a hand-held computer display, a lap-top computer display, a camera display, a video camera display, and a desk top computer display.

70. An apparatus comprising: a first row line; a first display element coupled with said first row line; a second row line; a second display element coupled with said second row line; and a column line coupled with said first display element and said second display element to allow data to be loaded sequentially by row or by column to said first display element and said second display element, wherein a potential of said column line is configured to be controlled during a view period subsequent to loading the data.

71. The apparatus of claim 70, further comprising a display incorporating said at least two display elements.

72. The apparatus of claim 71, wherein said display is selected from the group consisting of a display situated proximate to the eye, a cellular telephone display, a hand-held computer display, a lap-top computer display, a camera display, a video camera display, and a desk top computer display.