WO2003038620A3 - Procede de memorisation de donnees avec correction d'erreur - Google Patents

Procede de memorisation de donnees avec correction d'erreur Download PDF

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Publication number
WO2003038620A3
WO2003038620A3 PCT/FR2002/003758 FR0203758W WO03038620A3 WO 2003038620 A3 WO2003038620 A3 WO 2003038620A3 FR 0203758 W FR0203758 W FR 0203758W WO 03038620 A3 WO03038620 A3 WO 03038620A3
Authority
WO
WIPO (PCT)
Prior art keywords
words
data storage
storage method
group
correction
Prior art date
Application number
PCT/FR2002/003758
Other languages
English (en)
Other versions
WO2003038620A2 (fr
Inventor
Michael Nicolaidis
Original Assignee
Iroc Technologies
Michael Nicolaidis
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0114231A external-priority patent/FR2831970A1/fr
Application filed by Iroc Technologies, Michael Nicolaidis filed Critical Iroc Technologies
Priority to EP02793205A priority Critical patent/EP1573541A2/fr
Priority to US10/494,080 priority patent/US7124348B2/en
Publication of WO2003038620A2 publication Critical patent/WO2003038620A2/fr
Publication of WO2003038620A3 publication Critical patent/WO2003038620A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

L'invention concerne un procédé de mémorisation de données permettant des détections et corrections d'erreur dans une mémoire organisée pour lire et écrire des mots d'un premier nombre (m) de bits et éventuellement pour modifier une partie seulement d'un tel mot, comprenant les étapes suivantes associer un code de détection et de correction d'erreur à un groupe d'un deuxième nombre (k≥) de mots ; et à chaque écriture partielle dans le groupe de mots calculer un nouveau code du groupe de mots modifié, effectuer une opération de vérification et, si une erreur apparaît, effectuer une correction d'erreur du mot modifié et/ou du nouveau code.
PCT/FR2002/003758 2001-11-02 2002-10-31 Procede de memorisation de donnees avec correction d'erreur WO2003038620A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP02793205A EP1573541A2 (fr) 2001-11-02 2002-10-31 Procede de memorisation de donnees avec correction d'erreur
US10/494,080 US7124348B2 (en) 2001-11-02 2002-10-31 Data storage method with error correction

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0114231A FR2831970A1 (fr) 2001-11-02 2001-11-02 Procede de memorisation de donnees avec correction d'erreur
FR01/14231 2001-11-02
FR02/08626 2002-07-09
FR0208626A FR2831971A1 (fr) 2001-11-02 2002-07-09 Procede de memorisation de donnees avec correction d'erreur

Publications (2)

Publication Number Publication Date
WO2003038620A2 WO2003038620A2 (fr) 2003-05-08
WO2003038620A3 true WO2003038620A3 (fr) 2006-08-10

Family

ID=26213242

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2002/003758 WO2003038620A2 (fr) 2001-11-02 2002-10-31 Procede de memorisation de donnees avec correction d'erreur

Country Status (4)

Country Link
US (1) US7124348B2 (fr)
EP (1) EP1573541A2 (fr)
FR (1) FR2831971A1 (fr)
WO (1) WO2003038620A2 (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006190425A (ja) * 2005-01-07 2006-07-20 Nec Electronics Corp 半導体記憶装置
EP1798888B1 (fr) * 2005-12-19 2011-02-09 St Microelectronics S.A. Protection de l'exécution d'un algorithme DES
US8196011B2 (en) * 2006-02-15 2012-06-05 Hitachi Ulsi Systems Co., Ltd. Error detection and correction circuit and semiconductor memory
US7724593B2 (en) * 2006-07-07 2010-05-25 Rao G R Mohan Memories with front end precharge
US8291379B2 (en) * 2006-12-13 2012-10-16 International Business Machines Corporation Runtime analysis of a computer program to identify improper memory accesses that cause further problems
US20080168331A1 (en) * 2007-01-05 2008-07-10 Thomas Vogelsang Memory including error correction code circuit
US8271648B2 (en) * 2007-04-03 2012-09-18 Cinedigm Digital Cinema Corp. Method and apparatus for media duplication
JP5340264B2 (ja) * 2007-04-26 2013-11-13 アギア システムズ インコーポレーテッド エラー訂正機能および効率的なパーシャル・ワード書き込み動作を有するメモリ・デバイス
US7995409B2 (en) * 2007-10-16 2011-08-09 S. Aqua Semiconductor, Llc Memory with independent access and precharge
US8095853B2 (en) * 2007-10-19 2012-01-10 S. Aqua Semiconductor Llc Digital memory with fine grain write operation
US9164834B2 (en) * 2013-05-06 2015-10-20 Samsung Electronics Co., Ltd. Semiconductor memory devices, memory systems including the same and method of writing data in the same
US9569308B1 (en) 2013-07-15 2017-02-14 Rambus Inc. Reduced-overhead error detection and correction
US10176038B2 (en) 2015-09-01 2019-01-08 International Business Machines Corporation Partial ECC mechanism for a byte-write capable register
US9766975B2 (en) 2015-09-01 2017-09-19 International Business Machines Corporation Partial ECC handling for a byte-write capable register
US9985655B2 (en) * 2015-09-01 2018-05-29 International Business Machines Corporation Generating ECC values for byte-write capable registers
US10198315B2 (en) * 2016-02-29 2019-02-05 Sandisk Technologies Llc Non-volatile memory with corruption recovery
US20170286216A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Energy efficient read/write support for a protected memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573728A (en) * 1969-01-09 1971-04-06 Ibm Memory with error correction for partial store operation
US3814921A (en) * 1972-11-15 1974-06-04 Honeywell Inf Systems Apparatus and method for a memory partial-write of error correcting encoded data
EP0491073A1 (fr) * 1990-12-18 1992-06-24 Siemens Nixdorf Informationssysteme Aktiengesellschaft Méthode et procédé de protection de données dans des unités de mémoire
WO2001014971A1 (fr) * 1999-08-04 2001-03-01 Sun Microsystems, Inc. Systeme et procede de detection d'erreurs type double bit et de correction de telles erreurs imputables a des defaillances de composants

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4277844A (en) * 1979-07-26 1981-07-07 Storage Technology Corporation Method of detecting and correcting errors in digital data storage systems
US5357529A (en) * 1992-04-24 1994-10-18 Digital Equipment Corporation Error detecting and correcting apparatus and method with transparent test mode
US5841795A (en) * 1996-02-12 1998-11-24 Compaq Computer Corporation Error correction codes

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573728A (en) * 1969-01-09 1971-04-06 Ibm Memory with error correction for partial store operation
US3814921A (en) * 1972-11-15 1974-06-04 Honeywell Inf Systems Apparatus and method for a memory partial-write of error correcting encoded data
EP0491073A1 (fr) * 1990-12-18 1992-06-24 Siemens Nixdorf Informationssysteme Aktiengesellschaft Méthode et procédé de protection de données dans des unités de mémoire
WO2001014971A1 (fr) * 1999-08-04 2001-03-01 Sun Microsystems, Inc. Systeme et procede de detection d'erreurs type double bit et de correction de telles erreurs imputables a des defaillances de composants

Also Published As

Publication number Publication date
FR2831971A3 (fr) 2003-05-09
US7124348B2 (en) 2006-10-17
US20050028061A1 (en) 2005-02-03
FR2831971A1 (fr) 2003-05-09
WO2003038620A2 (fr) 2003-05-08
EP1573541A2 (fr) 2005-09-14

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