WO2003036723A3 - Semiconductor structure provided with a component capacitively uncoupled from the substrate - Google Patents

Semiconductor structure provided with a component capacitively uncoupled from the substrate Download PDF

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Publication number
WO2003036723A3
WO2003036723A3 PCT/EP2002/009705 EP0209705W WO03036723A3 WO 2003036723 A3 WO2003036723 A3 WO 2003036723A3 EP 0209705 W EP0209705 W EP 0209705W WO 03036723 A3 WO03036723 A3 WO 03036723A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
semiconductor structure
structure provided
uncoupled
insulating layer
Prior art date
Application number
PCT/EP2002/009705
Other languages
German (de)
French (fr)
Other versions
WO2003036723A2 (en
Inventor
Josef Boeck
Thomas Meister
Herbert Schaefer
Reinhard Stengl
Original Assignee
Infineon Technologies Ag
Josef Boeck
Thomas Meister
Herbert Schaefer
Reinhard Stengl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Josef Boeck, Thomas Meister, Herbert Schaefer, Reinhard Stengl filed Critical Infineon Technologies Ag
Publication of WO2003036723A2 publication Critical patent/WO2003036723A2/en
Publication of WO2003036723A3 publication Critical patent/WO2003036723A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention concerns a semiconductor structure comprising a substrate (10), an insulating layer (14) arranged on one surface of the substrate (10), a layer (18) for components arranged on one surface (16) of the insulating layer (14) opposite the substrate (10), a semiconductor component (30a, 30b) arranged in the layer (18) for components and zone designed for capacitively uncoupling said semiconductor component (30a, 30b) relative to the substrate (10), said zone being formed by a space charge zone (96) formed in a region of the substrate (10) adjacent to the insulating layer (14).
PCT/EP2002/009705 2001-10-17 2002-08-30 Semiconductor structure provided with a component capacitively uncoupled from the substrate WO2003036723A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10151132.9 2001-10-17
DE2001151132 DE10151132A1 (en) 2001-10-17 2001-10-17 Semiconductor structure with a component capacitively decoupled from the substrate

Publications (2)

Publication Number Publication Date
WO2003036723A2 WO2003036723A2 (en) 2003-05-01
WO2003036723A3 true WO2003036723A3 (en) 2003-10-23

Family

ID=7702731

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/009705 WO2003036723A2 (en) 2001-10-17 2002-08-30 Semiconductor structure provided with a component capacitively uncoupled from the substrate

Country Status (2)

Country Link
DE (1) DE10151132A1 (en)
WO (1) WO2003036723A2 (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371401A (en) * 1992-08-31 1994-12-06 Hitachi, Ltd. Semiconductor integrated circuit fully isolated from the substrate
US5624854A (en) * 1992-09-02 1997-04-29 Motorola Inc. Method of formation of bipolar transistor having reduced parasitic capacitance
US5892264A (en) * 1993-10-04 1999-04-06 Harris Corporation High frequency analog transistors, method of fabrication and circuit implementation
US5994759A (en) * 1998-11-06 1999-11-30 National Semiconductor Corporation Semiconductor-on-insulator structure with reduced parasitic capacitance
FR2779869A1 (en) * 1998-06-15 1999-12-17 Commissariat Energie Atomique INTEGRATED SOI-TYPE CIRCUIT WITH DECOUPLING CAPACITY, AND METHOD FOR PRODUCING SUCH A CIRCUIT
US6084270A (en) * 1997-03-28 2000-07-04 Nec Corporation Semiconductor integrated-circuit device having n-type and p-type semiconductor conductive regions formed in contact with each other
US6130458A (en) * 1996-03-28 2000-10-10 Kabushiki Kaisha Toshiba Power IC having SOI structure
US6215155B1 (en) * 1997-12-19 2001-04-10 Advanced Micro Devices, Inc. Silicon-on-insulator configuration which is compatible with bulk CMOS architecture
US20010008284A1 (en) * 1999-08-31 2001-07-19 Feng-Yi Huang Silicon-germanium BiCMOS on SOI

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4441724A1 (en) * 1994-11-23 1996-05-30 Siemens Ag Modified silicon-on-insulator substrate for MOSFET back gate control

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371401A (en) * 1992-08-31 1994-12-06 Hitachi, Ltd. Semiconductor integrated circuit fully isolated from the substrate
US5624854A (en) * 1992-09-02 1997-04-29 Motorola Inc. Method of formation of bipolar transistor having reduced parasitic capacitance
US5892264A (en) * 1993-10-04 1999-04-06 Harris Corporation High frequency analog transistors, method of fabrication and circuit implementation
US6130458A (en) * 1996-03-28 2000-10-10 Kabushiki Kaisha Toshiba Power IC having SOI structure
US6084270A (en) * 1997-03-28 2000-07-04 Nec Corporation Semiconductor integrated-circuit device having n-type and p-type semiconductor conductive regions formed in contact with each other
US6215155B1 (en) * 1997-12-19 2001-04-10 Advanced Micro Devices, Inc. Silicon-on-insulator configuration which is compatible with bulk CMOS architecture
FR2779869A1 (en) * 1998-06-15 1999-12-17 Commissariat Energie Atomique INTEGRATED SOI-TYPE CIRCUIT WITH DECOUPLING CAPACITY, AND METHOD FOR PRODUCING SUCH A CIRCUIT
US5994759A (en) * 1998-11-06 1999-11-30 National Semiconductor Corporation Semiconductor-on-insulator structure with reduced parasitic capacitance
US20010008284A1 (en) * 1999-08-31 2001-07-19 Feng-Yi Huang Silicon-germanium BiCMOS on SOI

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BURGHARTZ J N ET AL: "A LOW-CAPACITANCE BIPOLAR/BICMOS ISOLATION TECHNOLOGY, PART 1- CONCEPT, FABRICATION PROCESS, AND CHARACTERIZATION", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 41, no. 8, 1 August 1994 (1994-08-01), pages 1379 - 1386, XP000483758, ISSN: 0018-9383 *

Also Published As

Publication number Publication date
WO2003036723A2 (en) 2003-05-01
DE10151132A1 (en) 2003-05-08

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