WO2003036723A2

WO2003036723A2 - Semiconductor structure provided with a component capacitively uncoupled from the substrate

Info

Publication number: WO2003036723A2
Application number: PCT/EP2002/009705
Authority: WO
Inventors: Josef Boeck; Thomas Meister; Herbert Schaefer; Reinhard Stengl
Original assignee: Infineon Technologies Ag
Priority date: 2001-10-17
Filing date: 2002-08-30
Publication date: 2003-05-01
Also published as: DE10151132A1; WO2003036723A3

Abstract

The invention concerns a semiconductor structure comprising a substrate (10), an insulating layer (14) arranged on one surface of the substrate (10), a layer (18) for components arranged on one surface (16) of the insulating layer (14) opposite the substrate (10), a semiconductor component (30a, 30b) arranged in the layer (18) for components and zone designed for capacitively uncoupling said semiconductor component (30a, 30b) relative to the substrate (10), said zone being formed by a space charge zone (96) formed in a region of the substrate (10) adjacent to the insulating layer (14).

Description

description

Semiconductor structure with a component capacitively decoupled from the substrate

The present invention relates to a semiconductor structure with a semiconductor component which is capacitively decoupled from a substrate of the semiconductor structure.

The increasingly higher integration density of semiconductor components in semiconductor chips has the consequence, among other things, that the semiconductor components have increasingly smaller distances from one another. The smaller the distance between two semiconductor components, the greater the capacitive coupling and thus the electrical crosstalk between the semiconductor components. The capacitive coupling can take place directly within the component layer of the chip and indirectly via the underlying substrate, which generally has an electrical conductivity. In the case of an SOI structure (SOI = Silicon On Insulator), the (silicon) component layer is electrically insulated from the substrate by an insulating layer, which is usually formed by a buried oxide layer. The buried oxide layer is also referred to as BOX (BOX = buried oxide). If the component is an integrated coil, its electrical quality is influenced or deteriorated by a capacitive coupling to another component. In the case of integrated high-frequency circuits, the power loss is further increased by the capacitive coupling between individual components of a chip and between a component and semiconductor material that is not part of a component.

A requirement in the design and construction of semiconductor structures is therefore the greatest possible reduction in the capacitive coupling between the individual components. Another requirement is the most effective full dissipation of power loss of the components of the semiconductor structure. Both of these requirements partially conflict with one another, since with many materials, for example with the oxide often used for electrical insulation in semiconductor technology, good electrical insulation properties are associated with poor thermal conductivity.

Previous solutions to meet these requirements are known as full trench and partial trench isolation in SOI structures for CMOS components (CMOS = complementary metal oxide semiconductor). Examples are given in the article "Impact of 0.18 μm SOI CMOS Technology using Hybrid Trench Isolation with High Resistivity Substrate on Embedded RF / Analog Applications" by S. Maeda et al., 2000 Symposium on VLSI Technology - Digest of Technical Papers (Cat No00CH37104), pp. 154-155, and in the article "Impact of 0.10 μm SOI CMOS with Body-Tied Hybrid Trench Isolation Structure to Break Through the Scaling Crisis of Silicon Technology" by Y. Hirano et al., IEDM 2000, Technical Digest (Cat. No. 00CH37138), pp. 467-470.

In this context, a trench or trench is a trench in a component layer, which is preferably filled with an electrically insulating material, for the isolation of two laterally adjacent regions in the component layer. A partial or shallow trench or a shallow trench is a trench that does not extend to the buried oxide layer of the SOI structure, in which silicon therefore remains between the trench and the buried oxide layer. An STI (shallow trench isolation) brought about by a shallow trench is thus similar to isolation by trenches on a normal bulk or bulk wafer without an SOI structure, in which a current path between two components in the wafer separated by the trench constricted and extended, but not completely interrupted. The article “A 73 GHz f _τ 0.18 μm RF-SiGe BiCMOS Technology considering Thermal Budget Trade-off and with reduced Boron-spike effect on HBT Characteristics "by T. Hashimoto et al., IEDM 2000, Technical Digest (Cat. No. 00CH37138), pp. 149-152) shows in FIG. 2 a cross section of an example of such an isolation in the case of one BiCMOS processes or chips (BiCMOS = bipolar-CMOS = combination of bipolar and CMOS technology) The partial trench is characterized by a comparatively small etching depth which is in the range of the minimal lateral lithography resolution, for example the depth of a partial Trench typically 0.3 μm in the case of a 0.25 μm CMOS process.

A filling trench or a complete trench is a trench between components of a chip with an SOI structure, in which the silicon is etched or interrupted up to the buried oxide or insulator layer, so that current paths between the components are completely interrupted , A filling trench can separate larger transistor areas from one another, as is also described in the above-mentioned article by S. Maeda. Larger passive components can be arranged above a filling trench.

A deep trench or a deep trench is described, for example, in the article "An SOI-Based High Performance Self-Aligned Bipolar Technology Featuring 20 ps Gate Delay and a 8.6 fJ Power Delay Product" by E. Bertagnolli et al., 1993 Symposium on VLSI Technology, Digest of Technical Papers (Cat. No .: 93CH3303-5) pp. 63-64) This article presents a bipolar process on SOI in which a bipolar transistor is isolated by a deep trench , which extends to the buried oxide layer of the SOI structure and has a depth-to-width ratio> 1. In contrast to the filling trench, the deep trench is not wide enough to be able to integrate passive components in their full dimensions. Rather, the deep trench is used exclusively for dielectric component isolation - the principle of the deep

Trench or isolation with a deep trench is in that Article "Process yields 50-MHZ op amp." By JH Day, Electronic Engineering Times, April 2, 2001.

In the following, a distinction is no longer made between a complete trench and a deep trench, and all trenches which extend as far as the buried oxide layer are referred to as deep trenches.

Conventionally, a capacitive decoupling of a semiconductor component in a semiconductor structure from an underlying substrate, a thick insulating layer, which is usually at least about 1 micron thick, is used, which usually consists of an oxide. Since this has a very poor specific thermal conductivity, the thick insulating layer hinders the heat dissipation of components into the substrate and thus the dissipation of power loss. This disadvantage is all the more serious the greater the integration density of components in the semiconductor structure and the faster the semiconductor structure is clocked.

The object of the present invention is to provide an improved semiconductor structure and a method for its production.

This object is achieved by a semiconductor structure according to claim 1 or a method according to claim 15.

A semiconductor structure according to the present invention comprises a substrate, an insulating layer which is arranged on a surface of the substrate, a component layer which is arranged on a surface of the insulating layer which faces away from the substrate, a semiconductor component which is arranged in the component layer and a region for capacitive decoupling of the semiconductor component from the substrate, which is formed by a space charge zone formed in a region of the substrate adjoining the insulating layer. In a region adjacent to the insulating layer, the substrate preferably has a flat pn junction aligned parallel to the surface of the substrate. Alternatively, the space charge zone can be generated by applying a voltage to the substrate, by means of which an inversion layer adjoining the insulating layer is also generated in the substrate. The insulating layer preferably has a thickness that is less than 1 μm. The thickness of the insulating layer is particularly preferably in the range from 3 nm to 400 nm, this range including all values greater than 3 nm and less than 400 nm. The insulating layer preferably has a thermal resistance in the direction perpendicular to the insulating layer, which is smaller or substantially smaller than the thermal resistance of the substrate.

A method for producing a semiconductor structure according to the present invention comprises the following steps:

Creating a substrate;

Creating an insulating layer on a surface of the substrate;

Producing a component layer on a surface of the insulating layer facing away from the substrate;

Generating a semiconductor component in the component layer; and

Generating an area for capacitive decoupling of the semiconductor component from the substrate, which is formed by a space charge zone formed in an area of the substrate adjoining the insulating layer. Further preferred developments of the present invention are defined in the subordinate claims.

The present invention is based on the knowledge that the functions of electrostatic or dielectric insulation and the capacitive decoupling of a component layer and a substrate in a semiconductor structure do not require a thick insulating layer, but instead by means of a very thin insulating layer and an adjoining high-resistance layer Space charge zone can be fulfilled, wherein the insulating layer can in particular be thinner or significantly thinner than 1 μm.

An advantage of the present invention is that it simultaneously enables excellent capacitive decoupling of a semiconductor component in a semiconductor structure from its substrate and unhindered dissipation of heat loss from the semiconductor component into the substrate.

Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the accompanying figures. Show it:

1 shows a schematic sectional illustration of a preferred exemplary embodiment of the present invention;

2 shows a schematic sectional illustration of a further preferred exemplary embodiment of the present invention;

3a to 3c different variants of a detail of the embodiment shown in Fig. 2;

4 shows a diagram which shows schematically for two different substrate doping a relationship between a voltage to be applied to a substrate contact and a doping implantation dose; FIG. 5 shows a schematic sectional illustration of the semiconductor structure shown in FIG. 1 in a first phase during a production method according to an exemplary embodiment of the present invention;

FIG. 6 shows a schematic sectional illustration of the semiconductor structure from FIG. 1 in a second phase of the production method from FIG. 5;

FIG. 7 shows a schematic sectional illustration of the semiconductor structure from FIG. 1 in a third phase of the production method from FIG. 5;

FIG. 8 shows a schematic sectional illustration of the semiconductor structure from FIG. 1 in a first phase of a production method according to a further exemplary embodiment of the present invention;

FIG. 9 shows a schematic sectional illustration of the semiconductor structure from FIG. 1 in a second phase of the production method from FIG. 8; and

FIG. 10 shows a schematic sectional illustration of the semiconductor structure from FIG. 1 in a third phase of the production method from FIG. 8.

1 is a schematic illustration of a section through a semiconductor structure according to an exemplary embodiment of the present invention, the section being arranged perpendicular to layers of the semiconductor structure. The semiconductor structure comprises a substrate 10 with a surface 12 on which an insulating layer 14 is arranged. Arranged on a surface 16 of the insulating layer 14 facing away from the substrate is a component layer 18 with a surface 20 facing away from the insulating layer 14, in which a first bipolar transistor 30a and a second bipolar transistor 30b are in turn arranged. The first bipolar Transistor 30a and the second bipolar transistor 30b each have an emitter 32, a base 34 and a collector 36.

Only the first bipolar transistor 30a is described below; in this exemplary embodiment, the second bipolar transistor 30b has the same structure as the first bipolar transistor 30a.

The emitter 32 adjoins the base 34 and is open on the surface 20 of the component layer 18, so that it is accessible for electrical contacting. Compared to other areas of the semiconductor structure, the emitter 32 is electrically insulated by a spacer or an emitter insulating layer 42, which surrounds it essentially in a cylindrical manner. The base 34 also borders on the collector 36 and a first base contacting area 44. A second base contacting area 46 extends from the surface 20 of the component layer 18 to the first base contacting area 44. The collector 36 also borders on a first collector contacting area 48 which passes through a buried layer of the bipolar transistor is formed. A second collector contact area 50 extends from the surface 20 of the component layer 18 to the first collector contact area 48.

The first and second bipolar transistors 30a, 30b are electrically isolated from one another and to the outside by electrically insulating material as follows. A first component insulating layer 60 borders on the insulating layer 14 and in the lateral direction on the first collector contacting areas 48. A second component insulating layer 62 borders on the first component insulating layer 60, the first collector contacting areas 48, ie the buried layer, and laterally to the second collector contact areas 50 and the collectors 36. A third component insulation layer 64 borders on the second component insulation layer 62, the collectors 36 and laterally on the bases 34 and the second collector contact layers. animal regions 50. A fourth component insulation layer 66 borders the third component insulation layer 64 and laterally the first base contact regions 44 and the second collector contact regions 50. A fifth component insulation layer 68 borders the fourth component insulation layer 66, the first base contact regions 44 and laterally to the second base contact areas 46, the emitter insulating layers 42 and the second collector contact areas 50.

A substrate contact region 80 extends from the surface 20 of the component layer 18 through all component insulating layers 60 to 68 and the insulating layer 14 into the substrate 10 and is laterally spaced apart from the bipolar transistors 30a, 30b.

The emitters 32, the bases 34, the collectors 36, the base contact regions 44, 46 and the collector contact regions 48, 50 have doped and thus electrically conductive monocrystalline or polycrystalline silicon. In this exemplary embodiment, the emitters 32 and the collectors 36 are n-doped, the bases 34 are p-doped and the bipolar transistors 30a, 30b are thus npn-bipolar transistors.

The insulating layer 14, the emitter insulating layers 42 and the component insulating layers 60-68 have one or more electrically insulating materials, for example a silicon oxide or a silicon nitride, and bring about galvanic or dielectric or electrostatic insulation. The emitter insulation layers 42 completely enclose the emitters 32 in the lateral direction and thus isolate them from the respectively adjacent first base contact area 44. The first collector contact areas 48 and the substrate contact area 80 each adjoin the first component insulation layer 60 in the lateral direction along their entire circumference or outer edge The collectors 36, the second collector contacting areas 50 and the substrate contacting area 80 each border in the lateral direction along their the entire circumference to the second component insulating layer 66. The bases 34, the second collector contacting regions 50 and the substrate contacting region 80 each border in the lateral direction along the entire circumference of the third component insulating layer 64. The first base contacting regions 44, the second collector contacting regions 50 and the In the lateral direction, substrate contacting regions 80 each adjoin the fourth component insulating layer 66 along their entire circumference. The second base contacting regions 46, the second collector contacting regions 50 and the substrate contacting region 80 in each case adjoin the fifth component insulating layer 68 in the lateral direction along their entire circumference.

In other words, the collectors 36 of the bipolar transistors 30a, 30b in particular are insulated by a shallow trench or a shallow trench, which is essentially formed by the second component insulating layer 62. This has the advantage that overlap capacitances and Ccs (Ccs = collector-substrate capacitances are reduced. Apart from the collector 36 and the first collector contacting region 48), no further parasitic silicon borders on the trench. This results from the lower capacitances resulting from this reduced parasitic currents, as can be induced, for example, by an adjacent coil.

The substrate 10 has p-doped silicon with a doping concentration of 10 ¹³ cm ^-3 to 10 ¹⁴ cm ^-3 and a specific resistance of 1000 Ωcm to 100 Ωcm. Interrupt areas are on the surface 12 of the substrate 10

90a, 90b, 90c, which have p-doped silicon with a doping concentration that is higher than that of the other regions of the substrate 10. A first interruption region 90a is arranged on the left in FIG. 1 on the edge of the semiconductor structure shown, a second one Interruption area 90b is between the bipolar transistors 30a, 30b is arranged, and a third interruption region 90c is arranged adjacent to the substrate contacting region 80.

An electrostatic potential which is independent of potentials of the bipolar transistors 30a, 30b can be applied to the substrate 10 via the substrate contacting region 80 and the third interruption region 90c. Typical potential ratios are +5 V at the collector 36 and 0 V at the substrate 10. In this case, a thin inversion layer 94 is formed in the substrate 10 immediately adjacent to the surface 12 and then a much thicker space charge zone 96 the concentration of the majority charge carriers (holes) is greatly reduced in relation to a region 98 of the substrate which is further away from the surface 12, so that the space charge zone 96 has an almost vanishing electrical conductivity. The inversion layer 94 is produced by a movement of minority charge carriers, in the case of the p-type substrate electrons, to the interface between the insulator and the semiconductor. It has finite electrical conductivity.

Between the interruption regions 90a, 90b, 90c and the inversion layer 94, pn junctions oriented laterally with respect to the semiconductor structure are formed, so that different regions of the inversion layer 94, which are spatially separated from one another by interruption regions 90a, 90b, 90c, are also electrically are isolated from each other.

Because of the structure of the semiconductor structure described, the bipolar transistors 30a, 30b are not only completely electrically isolated from one another, but moreover are also largely capacitively decoupled. One of the reasons for the extensive capacitive decoupling of the two bipolar transistors 30a, 30b from one another is that a space 102 between them is completely filled by the component insulating layers 60 to 68 and thus contains no semiconductor material which is not a necessary component one of the bipolar transistors 30a, 30b. Thus, compared to a conventional semiconductor structure with the same arrangement of two bipolar transistors, the effective distance determining the size of the capacitive coupling between them is maximally increased. Capacities between the bipolar transistors 30a, 30b or their components are therefore minimal for a given spatial arrangement.

As already mentioned, a further consequence of the described construction of the component layer 18 is a reduction in parasitic currents which can be induced in semiconductor material, for example, by adjacent coils.

Furthermore, the semiconductor structure illustrated with reference to FIG. 1 has a very low capacitive coupling of each of the bipolar transistors 30a, 30b to the substrate 10 and via this to the other of the bipolar transistors 30a, 30b. At the same time, the semiconductor structure shown has a very good heat-conductive connection between the bipolar transistors 30a, 30b and the substrate 10. Whereas in conventional semiconductor structures an electrostatic isolation and a capacitive decoupling of components in the component layer from the substrate is brought about by a thick insulating layer between the component layer and the substrate, according to the present invention the bipolar transistors 30a, 30b or also other components in the component layer 18 capacitively decoupled from the substrate by the insulating layer 14 and the space charge zone 96. Since the capacitive decoupling is essentially effected by the space charge zone 96, the insulating layer 14 can be made so thin that it just barely fulfills the function of the electrostatic insulation. A lower limit for the thickness of the insulating layer 14 is approximately 3 nm. In the case of an even thinner insulating layer, a tunnel current occurs which results in finite conductivity. The thickness of the insulating layer 14 is particularly preferably in the range from 20 nm to approximately 100 nm, the thickness in particular also all Can assume values between 20 nm and 100 nm. Further preferred thicknesses of the insulating layer 14 are in the range up to approximately 400 nm.

While the insulating layer 14 with a thickness in the range from 3 nm to 400 nm sufficiently isolates the bipolar transistors 30a, 30b from the substrate 10, at the same time it has a significantly higher thermal conductivity than an insulating layer according to the prior art. Since the oxide of the insulating layer 14 has a thermal conductivity which is approximately 100 times lower than that of silicon, the insulating layer 14 significantly influences the dissipation of power loss or of heat generated by the bipolar transistors 30a, 30b to the substrate and via this to the environment. Practice the semiconductor structure. Effective removal of waste heat generated by components is of great and increasing importance with an increasing integration density and an increasingly faster clocking of the components in modern semiconductor structures. The small thickness of the insulating layer 14 and the associated high thermal conductivity thereof are made possible in that, according to the present invention, the capacitive decoupling of the bipolar transistors from the substrate 10 is effected by the thick space charge zone 96.

Via the substrate contact 80, it is possible to determine the electrostatic potential of the inversion zone 94 or also the space charge zone 96 in the substrate 10 below the insulating layer 14. In the case of low p-doped material, an inversion layer naturally already arises under the insulating layer 14 due to positive oxide charges. Since the first collector contact region 48 of the npn bipolar transistor 30a, 30b has a positive polarity with respect to the substrate, the formation of a space charge zone is supported , This is the deeper or thicker the higher the specific resistance of the substrate 10. For example, in the case of a specific resistance of the substrate 10, more precisely says the area 98 outside the space charge zone 96 of 1000 Ωcm the thickness of the space charge zone 96 below the inversion layer 94 about 9 microns. This corresponds to an effective thickness of the insulating layer 14 of approximately 3 μm.

The inversion layer 94 at the interface or surface 12 of the substrate 10 to the insulating layer 14 has a finite sheet resistance which is generally greater than approximately 10 kΩ / D, as described, for example, in the article “Modeling and Measurement of Substrate Coupling in Si-Bipolar IC s up to 40 GHz "by M. Pfost et al., IEEE Journal of Solid State Circuits, Vol. 33, No. 4, April 1998, pp. 582-591 To prevent the bipolar transistors 30a, 30b from capacitively coupling to one another indirectly via the inversion layer 94, the inversion layer 94 is interrupted by the interruption areas or channel stops 90a, 90b, 90c, the interruption areas the bipolar transistors 30a, 30b or sections 94a, 94b of the inversion layer 94 lying underneath the same, preferably laterally completely enclose and electrically isolate them from one another This condition does not result in indirect coupling between the bipolar transistors 30a, 30b. The interruption or insulation effect of the interruption regions 90a, 90b, 90c is based on the fact that they each form two pn junctions connected to one another with respect to the inversion layer 94, of which one always depends on the potential difference between the different sections 94a, 94b of the inversion layer 94 Is blocked. In order to fulfill this function, the interruption regions 90a, 90b, 90c in the direction perpendicular to the surface 12 of the substrate 10 must have a thickness which is greater than the thickness of the inversion layer 94. Since the layer resistance of the interruption regions 90a, 90b, 90c with approximately 600 Ω / D (see the above-mentioned article by M. Pfost) is substantially less than that of the inversion layer 94, the interruption regions 90a, 90b, 90c point laterally in the direction from one section 94a to the other section 94b of the inversion layer 94 preferably has the smallest possible width. A typical doping density of the interruption regions 90a, 90b, 90c is 2 x 10 ¹⁷ cm ^"3 .

FIG. 2 is a schematic sectional illustration of a further exemplary embodiment of a semiconductor structure according to the present invention. The semiconductor structure shown in FIG. 2 differs from that shown in FIG. 1 in that the substrate 10 has an n-doped region 110 which is adjacent to the surface 12 of the substrate and thus to the insulating layer 14 and the substrate contacting region 80. A voltage of approximately 5 V is preferably applied to the substrate contact 80 and to the collectors 36 of the bipolar transistors 30a, 30b with respect to the substrate 10 or the region 98 of the substrate 10. As a result, the n-doped region 110 of the substrate 10 is blocked with respect to the region 98 of the substrate 10, and a space charge zone 96 is formed in the substrate 10. This space charge zone 96 fulfills the same function as the space charge zone 96 in that shown in FIG. 1 Embodiment, namely the capacitive decoupling of the component layer 18 or the bipolar transistors 30a, 30b in the component layer 18 from the substrate 10 or the region 98 in which the substrate is conductive.

In contrast to the embodiment shown in FIG. 1, the embodiment shown in FIG. 2 has no inversion layer 94. The N layer or N well or the n-doped region 110 is formed by implanting an n-doping in the originally p-doped substrate. The implantation dose and thus the doping density in the n-doped region 110 is to be selected such that the n-doped region 110 is completely cleared of the voltage applied to the substrate contacting region 80 or has a minimal charge carrier density and the high-impedance space charge zone 96 through the n-doped region 110 extends right up to the insulating layer 14 or adjacent to this. With a penetration depth of the implanted doping of 1 μm, a typical doping concentration is 10 ¹⁵ cm ^"3. In this exemplary embodiment, p + -doped channel stops or interruption regions 90a, 90c are only required and provided at the edge of the chip in order to delimit the space charge zone 96 in a controlled manner or define their edge.

By polarizing the pn junction formed by the n-doped region 110 and the rest of the substrate 10 in the blocking direction, the capacitance between the bipolar transistors 30a, 30b and the substrate or its region 98 outside the space charge zone 96 can practically disappear to be brought. For example, in the case of a 20 nm thick insulating layer 14 with a breakdown field strength of 10 MV / cm and a p-doped substrate with a specific resistance of 1000 Ωcm, a space charge zone 96 of almost 50 μm thickness at a voltage of 20 V is possible to create.

For capacitive decoupling of a bipolar transistor 30a, 30b from the substrate 10, the pn junction formed by the n-doped region 110 and the rest of the substrate 10 does not have to be fully polarized in the reverse direction, but is sufficient if it is in the region and is blocked in the vicinity of the bipolar transistor.

FIG. 3 is a schematic sectional illustration of three variants of the design or the spatial extent of the n-doped region 110 in the substrate 10, only the substrate 10 with the interruption regions 90a, 90c and the one-part or multi-part n-doped region 110 in each case and the insulating layer 14 and a section 120 of the component layer 18 are shown. This corresponds to a state in one phase during the production of the semiconductor structure according to the invention described below. The section 120 of the component layer 18 shown represents a section in or on the component, for example that in FIGS. 1 and 2 The bipolar transistors 30a, 30b shown are formed or are formed in a later phase of the production process.

In FIG. 3a, the n-doped region 110 is continuous between the interruption regions 90a, 90c and thus has the shape already shown in FIG. 2. Such an n-doped region 110 is preferably formed by implanting the n-doping in the substrate 10 before the section 120 is applied, it being possible for the implantation to be carried out easily through the thin insulating layer 14 already applied.

3b shows a variant in which the n-doped region 110 was only produced by implantation after the section 120 had been formed on the insulating layer 14. For this purpose, the section 120 is protected during the implantation of the n-doping by a protective layer (not shown) on its surface 122 facing away from the insulating layer 14. The implantation does not have to take place homogeneously within the n-doped region 110, as shown in FIG. 3b, but can also be carried out, for example, by means of a grating mask which reduces the mean implantation dose and results in a spatially variable doping concentration or an inhomogeneously n-doped Area 110 leads as shown in FIG. 3c. If the lateral dimensions of section 120 are not much larger than the typical space charge zone width, the one shown is formed by diffusion of the doping atoms into edge regions under section 120 and, above all, by diffusion of charge carriers

Space charge zone 96, which also extends completely below section 120 in FIGS. 3b and 3c and fulfills the function described with reference to FIGS. 1 and 2. In other words, the diffusion regions of the doping atoms need not overlap, but only the space charge zones generated by all parts of the n-doped region 110. An application of this knowledge is described in the following. Usually implantation doses larger than or equal to 1 x 10 ¹¹ cm ^"2 are used. In order to obtain smaller effective doses in the substrate 10, it is possible to implant with a mask whose structures are smaller than the space charge zone widths that occur. This is described, for example, in the article" Variation of Lateral Doping as a Field Terminator for High Voltage Power Devices "by R. Stengl et al., IEEE Transactions on Electron. Devices Vol. 33 No. 3, p. 426, March 1986. For example, in order to obtain an effective dose of 5 x 10 ¹⁰ cm ^"2 with an implantation dose of 1 x 10 ¹¹ cm ^-2 , the simplest case would be to implant through a grid mask made of lacquer, each with 0.5 μm wide openings and The width of 0.5 μm is much smaller than the typical space charge zone widths in a semiconductor material with a specific resistance of 1000 Ω cm at a few volts, so that a largely homogeneous space charge zone would be generated despite the use of the grid mask.

FIG. 4 is a schematic representation of a relationship between the voltage of the substrate contacting region 80 with respect to the substrate 10 and the dose to be implanted into the substrate 10 to form the n-doped region 110 under the boundary condition that the space charge zone 96 generated by the voltage borders directly on the insulating layer 14. This relationship is for a substrate with a basic doping concentration of 1 x 10 ¹³ cm ^"3 (specific resistance approx. 1000 Ωcm; curve 124) and for a substrate with a basic doping concentration of 1 x 10 ¹⁴ cm ^{" 3} (specific resistance approx. 100 Ωcm; curve 126). It can be seen that the more the n-doped region 110 is doped, the greater the voltage of the substrate contacting region 80 with respect to the substrate if the high-resistance space charge zone is to connect directly to the insulating layer 14. In other words, the smaller the implantation dose used for doping the n-doped region 110, the lower voltages between the substrate contact region 80 and the substrate 10 are sufficient to create a space charge zone which extends directly to the insulating layer 14.

5, 6 and 7, the semiconductor structure shown in FIG. 1 is shown in different phases of a manufacturing method according to an embodiment of the present invention. The manufacturing method shown is based on an SOI structure in which there is the insulating layer 14 on the substrate 10 and a monocrystalline silicon layer thereon, in which the first collector contact areas 48 are later formed.

5, the interruption areas 90a, 90b, 90c have already been introduced into the substrate 10 and the insulating layer 14 has been produced on the surface 12. An n + -doped buried layer or buried layer with a thickness of 600 nm and a doping concentration of approximately 10 × 10 ²⁰ cm ^{3 was} produced in the silicon layer of the SOI structure on the surface 16 of the insulating layer 14 facing away from the substrate 10 , which later forms the first collector contact areas 48. Furthermore, the n + -doped buried layer has already been structured laterally by etching in Fig. 5. In particular, by etching complete trenches 130 which are in the vertical direction or in the direction perpendicular to the Surface 12 of substrate 10 and surface 16 of insulating layer 14 extend to surface 16 of insulating layer 14, which defines the first collector contact areas 48 in their lateral extension.

6 that the complete trenches 130 are filled with a first oxide in subsequent process steps. Subsequently, a flat surface 132 of the first oxide and of the first collector contact area 48 is produced by CMP (chemical mechanical polishing). The first oxide between the surface 16 of the insulating layer 14 and the surface 132 forms the first component insulation layer 60. A second oxide layer is then formed on the surface 132, in which openings are created by photolithography and anisotropic etching, the lateral dimensions of which correspond to those of the later collectors 36. In these openings, semiconductor material with a thickness of 300 nm is deposited on the buried layer or the first collector contacting regions 48 by selective epitaxy to form the collectors 36. 6 shows the state of the semiconductor structure according to the invention produced according to these method steps. The area defined by the second component insulation layer 62 in the intermediate space 102 between the collectors 36 can also be seen as a shallow trench filled with oxide.

7 shows a state of the semiconductor structure in which the bases 34, the third component insulation layer 64, the first base contact regions 44 and the fourth component insulation layer 66 have already been applied. Furthermore, the first base contact regions 44 each contain a hole 134 which extends to the base 34. The second, third and fourth component insulating layers 62, 64, 66 have holes 150 which extend to the first collector contact areas 48. The first, second, third and fourth component insulating layers 60, 62, 64, 66 and the insulating layer 14 have a hole 180 which extends up to the surface 12 of the substrate 10 or at that point below the surface 12 interruption area 90c reached. The holes 134, 150, 180 are filled with monocrystalline or polycrystalline semiconductor material in the following method steps in order to form the emitters 32, the second collector contacting regions 50 and the substrate contacting region 80.

The first base contact region 44 has p + -doped polycrystalline semiconductor material and is in each case in

Contact to the p + -doped bases 34. The base contact regions 44 are now except in the vicinity of the bases 34 in capacitively decoupled areas with thick dielectric insulation. The p + -doped polycrystalline semiconductor material is a material that is also used for passive integrated resistors.

5, 6 and 7 show a method for producing the semiconductor structure according to the invention using a CMP step and a selective epitaxy, FIGS. 8, 9 and 10 show different phases in a method for producing the semiconductor structure according to the invention Use of a full-surface collector epitaxy and two CMP steps, whereby this method also starts from an SOI structure.

FIG. 8 shows a state of the semiconductor structure according to the invention shown in FIG. 1, in which the insulating layer 14 and the interruption regions 90a, 90b, 90c on or below the surface 12 of the substrate 10 and a silicon layer on the surface 16 of the insulating layer 14 ge - were formed. An n + doping was diffused over the entire surface of the silicon layer in order to form the buried layer, which will later form the first collector contacting regions 48. Subsequently, a silicon layer was epitaxially applied to the buried layer, which will later form the collectors 36. Both layers were structured together by photolithography and anisotropic etching, deep trenches or filling trenches 130 being produced which extend in the vertical direction to the surface 16 of the insulating layer 14. The state thus generated is shown in Fig. 8.

In FIG. 9 it can be seen that the complete trenches 130 are filled with an oxide in a subsequent process step, which oxide forms the first and second component insulating layers 60, 62. A flat surface 182 of the collectors 36 and the oxide is formed in a CMP step. FIG. 10 shows a state of the semiconductor structure according to the invention in which, starting from the state shown in FIG. 9, edge regions 184 of the collectors 36 and the first collector contact regions 48 have been structured by etching in order to reduce the lateral expansion of the collectors 36. A further oxide layer 186 was then applied, which forms parts of the second component insulation layer 62 and the third component insulation layer 64. The trenches 184 represent shallow trenches.

After the state shown in FIG. 10, a second CMP step follows for planarization of the surface 188 of the oxide layer 186 facing away from the substrate 10, after essentially the same structure as that shown in FIG. 6 is present.

An advantage of the method illustrated with reference to FIGS. 8 to 10 compared to that illustrated with reference to FIGS. 5 to 7

The method is to avoid side wall defects which can arise during the selective epitaxy of the collectors 36. A disadvantage is that two planarization steps are necessary.

In particular in FIGS. 9 and 10 it can be clearly seen that the electrically insulating material surrounding the bipolar transistors instead of the layers shown in FIGS. 1 and 2 can also have a different (layer) structure, as long as it does Gap 102 completely fills up between the bipolar transistors 30a, 30b.

While silicon is used as the semiconductor material in the exemplary embodiments shown above, other semiconductor materials can also be used, for example GaAs. The insulating layer 14, the emitter insulating layers 42 and the component insulating layers 60 to 68 can do this have the same or different electrically insulating materials, for example oxides, in particular silicon oxide, or a nitride. In contrast to the exemplary embodiments shown, the semiconductor structure according to the invention can also have reversed doping signs, ie pnp bipolar transistors on an essentially n-doped substrate. In this case, the signs of all other doping must also be reversed.

An important aspect of the present invention is that the bipolar transistors 30a, 30b are completely surrounded and separated from each other by insulating material and that no further semiconductor material is arranged in the space 102 between the bipolar transistors 30a, 30b. However, this requirement is to be restricted if components of the two bipolar transistors 30a, 30b are short-circuited to one another directly via semiconductor material. In this case, the space 102 from the region in which the bipolar transistors 30a, 30b are short-circuited to one another is completely filled with insulating material.

In contrast to the exemplary embodiments shown above, the semiconductor structure according to the invention can have one or more other arbitrary active or passive semiconductor components instead of two bipolar transistors 30a, 30b. The present invention is therefore not limited to bipolar technology, but can equally well be applied to CMOS technology, BiCMOS technology, etc. LIST OF REFERENCE NUMBERS

10 substrate

12 surface of the substrate 10 14 insulating layer

16 surface of the insulating layer 14

18 component layer

20 surface of the component layer 18

30a first bipolar transistor 30b second bipolar transistor

32 emitters

34 base

36 collector

42 Emitter insulation layer 44 first base contact area

46 second basic contact area

48 first collector contact area

50 second collector contact area

60 first component insulation layer 62 second component insulation layer

64 third component insulation layer

66 fourth component insulation layer

68 fifth component insulation layer

80 substrate contact region 90a, 90b, 90c interruption region

94 inversion layer

94a, 94b portion of the inversion layer 94

96 space charge zone

98 area 102 space

110 n-doped region in substrate 10 120 section

122 surface of the section 120 130 deep trench 132 surface 134 hole 150 hole 180 holes

182 surface

184 ditch

186 oxide layer

188 surface

Claims

claims

1. Semiconductor structure with the following features:

a substrate (10);

an insulating layer (14) arranged on a surface (12) of the substrate (10);

a component layer (18) which is arranged on a surface (16) of the insulating layer (14) facing away from the substrate (10);

a semiconductor device (30a, 30b) arranged in the device layer (18); and

a region for capacitively decoupling the semiconductor component (30a, 30b) from the substrate (10), which is formed by a space charge zone (96) formed in a region of the substrate (10) adjoining the insulating layer (14).

2. The semiconductor structure as claimed in claim 1, in which the substrate (10) has a flat pn junction aligned parallel to the surface (12) of the substrate (10) in a region adjacent to the insulating layer (14).

3. The semiconductor structure as claimed in claim 1, in which the space charge zone is generated by applying a voltage to the substrate (10), by means of which an inversion layer (94) adjoining the insulating layer (14) is also produced in the substrate (10).

4. The semiconductor structure according to claim 2, wherein the substrate (10) substantially has a resistivity of 1000

Ω cm ^"1 and the insulating layer (14) have a thickness of 20 nm and a breakdown field strength of 10 MVcm ^{" 1} .

5. The semiconductor structure according to one of claims 1 to 4, further comprising a further semiconductor component (30a, 30b) which is arranged laterally spaced in the component layer (18) and from the semiconductor component (30a, 30b).

6. The semiconductor structure according to claim 5, further comprising an interruption region (90b) which laterally in the region of the substrate (10) adjoining the insulating layer (14) between the semiconductor component (30a, 30b) and the further semiconductor component (30a , 30b) is arranged, has the same conductivity type as the substrate (10) and has a higher doping density than the substrate (10).

7. The semiconductor structure according to claim 5 or 6, wherein the

Semiconductor component is a bipolar transistor (30a, 30b), furthermore with an insulating region (60, 62, 64, 66, 68) connected to the bipolar transistor (30a, 30b), the further semiconductor component (30a, 30b) and the insulating layer (14) adjoins, completely occupies a space between the bipolar transistor (30a, 30b) and the further semiconductor component (30a, 30b) and has an electrically insulating material.

8. The semiconductor structure of claim 7, wherein the isolation region (60-68) has a deep trench (130) and a shallow trench (184) that are filled with the electrically insulating material.

9. The semiconductor structure according to claim 8, wherein the deep trench (130) directly adjoins a buried layer of the bipolar transistor (30a, 30b) and the shallow trench (184) directly adjoins a collector (36) of the bipolar transistor (30a, 30b) adjoins.

10. Semiconductor structure according to one of claims 1 to 9, in which the substrate (10) is essentially p-doped.

11. The semiconductor structure according to one of claims 1 to 10, wherein the semiconductor component (30a, 30b) is an npn bipolar transistor.

12. Semiconductor structure according to one of claims 1 to 11, wherein the insulating layer (14) has a thickness which is less than 1 micron.

13. Semiconductor structure according to one of claims 1 to 12, in which the insulating layer (14) has a thickness in the range from 3 nm to 400 nm.

14. Semiconductor structure according to one of claims 1 to 13, wherein the substrate (10) has a doping density of 1 x 10 ¹³ cm ^"3 .

15. A method for producing a semiconductor structure, comprising the following steps:

Creating a substrate (10);

Creating an insulating layer (14) on a surface (12) of the substrate (10);

Producing a component layer (18) on a surface (16) of the insulating layer (14) facing away from the substrate (10);

Producing a semiconductor component (30a, 30b) in the component layer (18); and

Generating a region for capacitively decoupling the semiconductor component (30a, 30b) from the substrate (10), which is formed by a space charge zone (96) formed in a region of the substrate (10) adjoining the insulating layer (14).