WO2003030254A3 - Process for assembling systems and structure thus obtained - Google Patents
Process for assembling systems and structure thus obtained Download PDFInfo
- Publication number
- WO2003030254A3 WO2003030254A3 PCT/US2002/029691 US0229691W WO03030254A3 WO 2003030254 A3 WO2003030254 A3 WO 2003030254A3 US 0229691 W US0229691 W US 0229691W WO 03030254 A3 WO03030254 A3 WO 03030254A3
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- WIPO (PCT)
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- components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US32607601P | 2001-09-28 | 2001-09-28 | |
US60/326,076 | 2001-09-28 |
Publications (2)
Publication Number | Publication Date |
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WO2003030254A2 WO2003030254A2 (en) | 2003-04-10 |
WO2003030254A3 true WO2003030254A3 (en) | 2004-02-12 |
Family
ID=23270715
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/029691 WO2003030254A2 (en) | 2001-09-28 | 2002-09-17 | Process for assembling systems and structure thus obtained |
Country Status (1)
Country | Link |
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WO (1) | WO2003030254A2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004112136A1 (en) * | 2003-06-12 | 2004-12-23 | Koninklijke Philips Electronics N.V. | Electronic device |
DE10340608A1 (en) | 2003-08-29 | 2005-03-24 | Infineon Technologies Ag | Polymer formulation and method of making a dielectric layer |
DE102004005247A1 (en) * | 2004-01-28 | 2005-09-01 | Infineon Technologies Ag | Imprint-lithographic process for manufacturing e.g. MOSFET, involves structuring polymerized gate dielectric layer by imprint stamp that is used to form hole on layer, and etching base of hole till preset thickness of layer is reached |
US11037904B2 (en) * | 2015-11-24 | 2021-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Singulation and bonding methods and structures formed thereby |
WO2017111865A1 (en) * | 2015-12-22 | 2017-06-29 | Intel Corporation | Microelectronic devices designed with high frequency communication devices including compound semiconductor devices integrated on an inter die fabric on package |
US10546835B2 (en) * | 2015-12-22 | 2020-01-28 | Intel Corporation | Microelectronic devices designed with efficient partitioning of high frequency communication devices integrated on a package fabric |
WO2017111975A1 (en) * | 2015-12-22 | 2017-06-29 | Intel Corporation | Microelectronic devices with high frequency communication modules having compound semiconductor devices integrated on a package fabric |
DE102016109950B3 (en) * | 2016-05-30 | 2017-09-28 | X-Fab Semiconductor Foundries Ag | Integrated circuit having a component applied by a transfer pressure and method for producing the integrated circuit |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5161093A (en) * | 1990-07-02 | 1992-11-03 | General Electric Company | Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5545291A (en) * | 1993-12-17 | 1996-08-13 | The Regents Of The University Of California | Method for fabricating self-assembling microstructures |
US5877550A (en) * | 1996-07-31 | 1999-03-02 | Taiyo Yuden Co., Ltd. | Hybrid module and method of manufacturing the same |
US6294741B1 (en) * | 1995-07-10 | 2001-09-25 | Lockheed Martin Corporation | Electronics module having high density interconnect structures incorporating an improved dielectric lamination adhesive |
-
2002
- 2002-09-17 WO PCT/US2002/029691 patent/WO2003030254A2/en not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5161093A (en) * | 1990-07-02 | 1992-11-03 | General Electric Company | Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5545291A (en) * | 1993-12-17 | 1996-08-13 | The Regents Of The University Of California | Method for fabricating self-assembling microstructures |
US6294741B1 (en) * | 1995-07-10 | 2001-09-25 | Lockheed Martin Corporation | Electronics module having high density interconnect structures incorporating an improved dielectric lamination adhesive |
US5877550A (en) * | 1996-07-31 | 1999-03-02 | Taiyo Yuden Co., Ltd. | Hybrid module and method of manufacturing the same |
Non-Patent Citations (1)
Title |
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CHOU S Y ET AL: "IMPRINT OF SUB-25 NM VIAS AND TRENCHES IN POLYMERS", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 67, no. 21, 20 November 1995 (1995-11-20), pages 3114 - 3116, XP001074602, ISSN: 0003-6951 * |
Also Published As
Publication number | Publication date |
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WO2003030254A2 (en) | 2003-04-10 |
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