WO2003030235A1 - Plasma processor and plasma processing method - Google Patents

Plasma processor and plasma processing method Download PDF

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Publication number
WO2003030235A1
WO2003030235A1 PCT/JP2002/008968 JP0208968W WO03030235A1 WO 2003030235 A1 WO2003030235 A1 WO 2003030235A1 JP 0208968 W JP0208968 W JP 0208968W WO 03030235 A1 WO03030235 A1 WO 03030235A1
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WIPO (PCT)
Prior art keywords
substrate
plasma processing
processed
processing apparatus
lower electrode
Prior art date
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PCT/JP2002/008968
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French (fr)
Japanese (ja)
Inventor
Yoshiyuki Kobayashi
Keiichi Nagakubo
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Tokyo Electron Limited
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Publication of WO2003030235A1 publication Critical patent/WO2003030235A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68742Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32532Electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching

Definitions

  • the present invention relates to a plasma processing apparatus and a plasma processing method, and more particularly to a plasma processing apparatus for performing a plasma processing such as etching on a substrate to be processed such as a semiconductor substrate (semiconductor wafer) or a glass substrate (glass wafer) for a display device.
  • the present invention relates to a processing apparatus and a plasma processing method. Background art
  • plasma is generated in a processing chamber, and this plasma is applied to a substrate to be processed (for example, a semiconductor wafer or a glass substrate for a display device) arranged in the processing chamber.
  • a plasma processing apparatus that performs a predetermined process (for example, etching, film formation, and the like) is used.
  • a predetermined process is performed by applying plasma to a substrate to be processed in a vacuum chamber whose inside can be hermetically closed.
  • a so-called parallel plate type plasma processing apparatus an upper electrode and a lower electrode are provided in the vacuum chamber so as to face in parallel. Then, the substrate to be processed is placed on the lower electrode, high-frequency power is supplied between the upper electrode and the lower electrode to generate plasma, and the plasma is applied to the substrate to be processed to perform a predetermined process. It is configured as follows.
  • the lower electrode also serves as a support for the substrate to be processed. And for this lower electrode
  • the loading and unloading of substrates to be processed is usually automatically performed by a transport mechanism.
  • the lower electrode penetrates the lower electrode vertically so that the substrate to be processed is placed on the lower electrode and the substrate to be processed placed on the lower electrode can be easily taken out.
  • a substrate supporting member is provided. And, by moving the substrate support member and the lower electrode relatively up and down, the substrate support member protrudes above the lower electrode, and the substrate to be processed is supported on the lower electrode by the substrate support member; and From this state, the substrate supporting member is retracted into the lower electrode, and the substrate to be processed can be placed on the lower electrode.
  • the above-mentioned substrate support member is often formed in a pin shape (elongated rod shape). In many cases, about three or four pin-shaped substrate support members are provided, and the substrate to be processed is supported at three or four points. Further, in order to provide such a substrate support member, three or four through holes are provided in the lower electrode so as to penetrate in the vertical direction.
  • the lower electrode also serving as a support for the substrate to be processed is provided with a through-hole for providing a pin-shaped substrate support member or the like. During the plasma processing, the substrate support member is retracted into the lower electrode, and the processing is performed while the substrate to be processed is supported on the upper surface of the lower electrode.
  • the substrate to be processed mounted on the lower electrode is in a non-contact state with the lower electrode at the portion of the through hole described above.
  • An object of the present invention is to provide a plasma processing apparatus capable of performing uniform processing over the entire surface of a substrate to be processed and improving the uniformity of processing within the surface of the substrate to be processed, as compared with the related art. And to provide a plasma processing method.
  • a vacuum chamber which is capable of airtightly closing the inside thereof, performs a predetermined process by applying plasma to a substrate to be processed, and a mounting surface provided in the vacuum chamber and formed on an upper surface.
  • An electrode configured to place the substrate to be processed thereon, and an electrode provided so as to penetrate the electrode, and by moving up and down relatively to the electrode, the back side of the substrate to be processed is moved.
  • a plasma processing apparatus comprising: a substrate supporting member configured to support and move the substrate to be processed up and down between the mounting surface and the mounting surface. The apparatus is characterized in that it is electrically connected and that the substrate support member is kept in contact with the back surface of the substrate to be processed during the processing of the substrate to be processed.
  • the present invention is characterized in that in the above-mentioned plasma processing apparatus, high-frequency power is supplied to the electrode.
  • the present invention is characterized in that, in the plasma processing apparatus, the substrate support member is formed in a pin shape and is elastically expandable and contractible. Further, the present invention is characterized in that, in the above-described plasma processing apparatus, four pin-shaped substrate support members are provided on a vertically movable support.
  • the present invention also provides the plasma processing apparatus, wherein the contact portion of the pin-shaped substrate support member with the back surface of the substrate to be processed is made of a conductive resin. It is characterized by being composed of a material or a protective film.
  • the present invention is characterized in that, in the plasma processing apparatus, an etching process is performed by applying plasma to the substrate to be processed.
  • the method of the present invention is characterized in that a predetermined process is performed by applying plasma to the substrate to be processed using the plasma processing apparatus.
  • FIG. 1 is a diagram schematically showing a schematic configuration of an embodiment of the plasma processing apparatus of the present invention.
  • FIG. 2 is a diagram schematically showing an enlarged main part configuration of the plasma processing apparatus of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 schematically shows an outline of a configuration of an embodiment in which the present invention is applied to a plasma etching apparatus for etching a wafer.
  • reference numeral 1 denotes a vacuum chamber which is made of, for example, aluminum or the like and is configured so as to be able to hermetically close the inside thereof, and forms a cylindrical plasma processing chamber.
  • a shield box 10 is provided above the vacuum chamber 1.
  • a drive mechanism 20 for moving a lower electrode 2 described later up and down is provided below the vacuum chamber 1.
  • a lower electrode 2 for supporting a wafer W as a substrate to be processed substantially horizontally with the surface to be processed facing upward. Then, in the vacuum chamber 1 so as to face the lower electrode 2 in parallel.
  • An upper electrode 3 is provided on the ceiling.
  • the upper electrode 3 is formed with a large number of through holes (not shown) to form a so-called short head.
  • a predetermined processing gas supplied from a processing gas supply source (not shown) can be uniformly delivered from these through holes toward the wafer W provided on the lower electrode 2.
  • an exhaust port (not shown) is provided at the bottom of the vacuum chamber 1 so that the inside of the vacuum chamber 1 can be exhausted to a predetermined degree of vacuum by an exhaust mechanism such as a vacuum pump (not shown).
  • the upper electrode 3 is electrically connected to a high-frequency power supply 22 via a matching box 21 so that the upper electrode 3 has a predetermined frequency (for example, 380 kHz to 100 MHz). It is configured to be able to supply high frequency power.
  • a predetermined frequency for example, 380 kHz to 100 MHz. It is configured to be able to supply high frequency power.
  • a ring-shaped clamp ring 4 supported from the ceiling side of the vacuum chamber 1 is provided between the lower electrode 2 and the upper electrode 3.
  • the clamp ring 4 is configured to be vertically movable by a clamp ring drive mechanism 4a.
  • the clamping ring 4 and the clamp ring driving mechanism 4 a press the peripheral portion of the wafer W toward the lower electrode 2, and fix the wafer W on the lower electrode 2.
  • a coolant flow path (not shown) for circulating a coolant is provided to the lower electrode 2, and He gas is supplied to the back surface of the wafer W in order to efficiently transmit cold heat from the coolant to the wafer W.
  • a gas introduction mechanism (not shown) is provided to control the temperature of the wafer W to a desired temperature.
  • a resin film (not shown) is provided on the upper surface of the lower electrode 2 (the mounting surface of the wafer W) so as not to damage the rear surface of the wafer W.
  • the lower electrode 2 is configured to be vertically movable by the above-described driving mechanism 20 including, for example, a ball screw and a motor for rotating the ball screw. Has been established.
  • a bellows 5 made of stainless steel or the like is provided between the lower electrode 2 and the bottom in the vacuum chamber 1 to hermetically close the space therebetween.
  • a lifter unit 6 provided with a plurality (four in this example) of lifter pins described later as a substrate support member is provided at the center of the lower electrode 2. Then, as the lower electrode 2 moves up and down, the lifter pin is configured to be able to protrude above the lower electrode 2 through the through hole 2 a provided in the lower electrode 2.
  • reference numeral 7 denotes a high frequency power of a predetermined frequency (for example, 380 kHz to 40.6 MHz) from the high frequency power supply 24 via the matching unit 23, and 2 shows the RF port to supply to 2.
  • Reference numeral 8 denotes a temperature sensor cable for deriving a detection signal from a temperature sensor provided in the lower electrode 2.
  • FIG. 2 schematically shows the configuration of the lifter unit 6, and the left side of the dashed line shown in the center of the figure shows the state in which the lifter pin 60 is lowered. The right side of indicates that the lifter pin 60 has been raised.
  • the lifter pins 60 shown in FIG. 2 are arranged so as to penetrate through holes 2 a provided in the lower electrode 2, and the lower end thereof is fixed to the base 61 by screwing or the like. I have. Usually, about three or four lifter pins 60 are provided. In the present embodiment, four lifter pins 60 are fixed to the base 61, and these lift pins 60 are symmetrically arranged around the center of the lower electrode 2.
  • a through hole 61 a is provided in the center of the base 61. Then, the support shaft 62 is inserted into the through hole 61a from below, and the upper end of the support shaft 62 is The base 61 is fixed to the lower electrode 2 with screws or the like, and the base 61 is supported by a stopper 63 provided at the lower end of the support shaft 62. Are supported so as to be relatively vertically movable. Further, a lifter spring 64 is provided on the support shaft 62 so that the base 61 is directed downward with respect to the lower electrode 2 (in the direction in which the lift pin 60 descends). ) Is configured to be biased.
  • a lift shaft 65 and a rod 66 there are provided a lift shaft 65 and a rod 66, and through these lift shaft 65 and the rod 66, the base is provided.
  • the bottom of 6 1 is pressed, and the base 6 1 moves upward relative to the lower electrode 2 while contracting the lift spring 6 4, and the lift pin 60 protrudes from the upper surface of the lower electrode 2. It is configured to be.
  • the bottom of the base 61 is pressed by the lift shaft 65 and the rod 66 by moving the lower electrode 2 up and down, or by the lift shaft 65 and the rod 66. Is performed by moving up and down.
  • a spring (coil spring, etc.) (not shown) is built in the lift pin 60, and as shown in the right end of FIG. 2, a predetermined stroke S, for example, about 3 mm, is elastically expandable and contractable. It is configured.
  • a coating film 60a made of a conductive resin, for example, conductive Teflon (registered trademark) is applied to a tip portion of the rifle pin 60, and the coating film 60a is applied through the coating film 60a. The top of the pin 60 is in contact with the back surface of the wafer W.
  • the present invention is not limited to the formation of the coating layer, and a configuration may be adopted in which a conductive resin material is attached to the tip of the pin 60 by bonding or the like.
  • the rifle pin 60, the base 61, the support shaft 62, the rifle spring 64, and the like are made of a conductive material such as stainless steel. Further, since the coating film 60a is also conductive, (C) The top of the riff pin 60 contacting the rear surface of W is in a state of being electrically connected to the lower electrode 2 and has substantially the same potential as the lower electrode 2. .
  • the coating film 60a is for preventing the back surface of the wafer W from being scratched. In order to improve the processing uniformity, it is preferable to make the coating film as thin as possible. The thickness is preferably, for example, about 50 5m to 200 / m. Further, it is possible to prevent the back surface of the wafer W from being scratched by machining the tip of the lift pin 60 without providing the coating film 60a.
  • the lift pins 60 are relatively lowered with respect to the lower electrode 2, and the wafer W mounted on the lower electrode 2 is fixed by the clamp ring 4 described above, and a predetermined etching process is performed on the wafer W.
  • the top of the pin 60 is pressed against the back surface of the wafer W by a spring built in the bin 60 as shown on the left side of FIG. (The remaining stroke S 1 of the pin 60 shown in the figure is, for example, about 1 mm).
  • the remaining stroke S 1 of the pin 60 shown in the figure is, for example, about 1 mm).
  • each of the four provided lift pins 60 is brought into contact with the back surface of the wafer W by the elastic force of each built-in individual panel.
  • each lifter pin 60 Even if there is a slight deviation in the height of the top (the contact surface with the wafer W), it is possible to ensure that all four pins 60 of each rift are securely in contact with the back surface of the wafer W. .
  • a gate valve (not shown) is opened, and the wafer W is loaded into the vacuum chamber 1 by a transfer ham of an automatic transfer mechanism or the like via a load lock chamber (not shown) arranged adjacent to the gate valve.
  • the lower electrode 2 is lowered to a predetermined position in advance, and the four riff pins 60 are projected on the lower electrode 2.
  • the wafer W is placed.
  • the transfer arm is retracted out of the vacuum chamber 1, and the gate valve is closed.
  • the lower electrode 2 is raised to a predetermined height by the drive mechanism 20, and accordingly, substantially the entirety of the lift pin 60 is housed in the lower electrode 2. Then, the peripheral edge of the wafer W is pressed against the lower electrode 2 by the clamp ring 4, and the wafer W is fixed on the lower electrode 2. At this time, as shown in the left part of FIG. 2 described above, the top of each lifter pin 60 is in a state of being abutted on the back surface of the wafer W by the spring built in the lifter pin 60. It has been.
  • the inside of the vacuum chamber 1 is evacuated by the exhaust mechanism, and a predetermined processing gas is introduced into the vacuum chamber 1 through the through hole of the upper electrode 3, for example.
  • a predetermined processing gas is introduced into the vacuum chamber 1 through the through hole of the upper electrode 3, for example.
  • it is introduced at a flow rate of 100 to 1 000 sccm, and the inside of the vacuum chamber 1 has a predetermined pressure, for example, 1.33 to: L33Pa (10 to: LOO OmT orr), preferably 2.67 to 26.7. It is kept at about P a (20 to 200 mT orr).
  • high-frequency power having a frequency of, for example, 380 KHz to 100 MHz is supplied from the high-frequency power supplies 22 and 24 to the upper electrode 3 and the lower electrode 2, and the processing gas supplied into the vacuum chamber 1 is supplied.
  • the film is turned into plasma, and a predetermined film on the wafer W is etched by the plasma.
  • each rifle pin 60 electrically connected to the lower electrode 2 is in contact with the back surface of the wafer W as described above. This suppresses non-uniform processing, such as a decrease in the etching rate at the portion of the through-hole 2 a of the lower electrode 2, and improves in-plane uniformity of the etching processing of the wafer W. be able to.
  • the supply of the high-frequency power from the high-frequency power sources 22 and 24 and the supply of the processing gas are stopped, the etching process is stopped, and the procedure is reverse to the procedure described above. Then, the wafer W is carried out of the vacuum chamber 1.
  • the pressure in the vacuum chamber 1 was 26.7 Pa (200 mTorr), and the processing gas was CHF 3 (flow rate 45 SCCM) + CF 4 (flow rate 90 SCCM) + Ar (flow rate 600 SCCM).
  • the high-frequency power as 1 1 00W, PR (photoresist g) in Bruno £ 03 Bruno 3:10 2 went 60 seconds etching of the wafer W is formed.
  • PR photoresist g
  • the in-plane uniformity of the etching rate of the wafer W was 3.7%. .
  • each of the ribs 60 was changed to one without a built-in panel.
  • the etching process was performed in the state of being brought into contact with the substrate.
  • the in-plane uniformity of the etching rate was 5.0%.
  • each lifter pin 60 was etched under the same conditions without contacting the back surface of the wafer W.
  • the etching rate of the portion of the wafer W corresponding to each rifle pin 60 (through hole 2a) was reduced, and the in-plane uniformity of the etching rate was 13.9%.
  • the present invention is not limited to such a case.
  • it may be one that processes a substrate other than the wafer W, and may be applied to plasma processing other than etching, for example, a film forming apparatus such as a CVD.
  • the case where four lift pins 60 are used as the substrate supporting member has been described.
  • the number of lift pins 60 may be any number.
  • the present invention is not limited to the pin-shaped substrate supporting member, and a substrate supporting member having another shape may be used.
  • uniform processing can be performed over the entire surface of a substrate to be processed, and the uniformity of processing within the surface of the substrate to be processed can be improved as compared with the related art.
  • the plasma processing apparatus and the plasma processing method according to the present invention can be used in a semiconductor manufacturing industry or the like that manufactures semiconductor devices. Therefore, the present invention has industrial applicability.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Plasma & Fusion (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Drying Of Semiconductors (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

While a wafer (W) mounted on a lower electrode (2) is etched as predetermined, the top of a lifter pin (60) electrically connected to the lower electrode (2) remains pressed on the wafer (W) by a spring built in the lifter pin (60). Most part of the rear of the wafer (W) corresponding to a through hole (2a) receives the contact of the top of this lifter pin (60) to keep a condition similar to a contact with the lower electrode (2). Thus, the whole of a substrate to be processed is processed uniformly, so that the uniformity of the in-plane processing of the substrate to be processed is more improved than conventional.

Description

明 細 書 プラズマ処理装置及びプラズマ処理方法 技術分野  Description Plasma processing apparatus and plasma processing method
本発明は、 プラズマ処理装置及びプラズマ処理方法に係り、 特に半導 体基板 (半導体ウェハ) やディスプレイ装置用のガラス基板 (ガラスゥ ェハ) 等の被処理基板に、 エッチング等のプラズマ処理を施すプラズマ 処理装置及びプラズマ処理方法に関する。 背景技術  The present invention relates to a plasma processing apparatus and a plasma processing method, and more particularly to a plasma processing apparatus for performing a plasma processing such as etching on a substrate to be processed such as a semiconductor substrate (semiconductor wafer) or a glass substrate (glass wafer) for a display device. The present invention relates to a processing apparatus and a plasma processing method. Background art
従来から、 半導体装置の製造分野においては、 処理室内にプラズマを 発生させ、 このプラズマを処理室内に配置した被処理基板 (例えば半導 体ウェハやディスプレイ装置用のガラス基板等) に作用させて、 所定の 処理 (例えば、 エッチング、 成膜等) を行うプラズマ処理装置が用いら れている。  Conventionally, in the field of semiconductor device manufacturing, plasma is generated in a processing chamber, and this plasma is applied to a substrate to be processed (for example, a semiconductor wafer or a glass substrate for a display device) arranged in the processing chamber. A plasma processing apparatus that performs a predetermined process (for example, etching, film formation, and the like) is used.
このようなプラズマ処理装置では、 内部を気密に閉塞可能とされた真 空チャンバ内において、 被処理基板にプラズマを作用させて所定の処理 を施すようになつている。 例えば、 所謂平行平板型のプラズマ処理装置 では、 この真空チャンバ内に、 上部電極と下部電極が、 平行に対向する ように設けられている。 そして、 下部電極上に被処理基板を載置し、 上 部電極と下部電極との間に高周波電力を供給してプラズマを生起し、 被 処理基板にこのプラズマを作用させて所定の処理を行うように構成され ている。  In such a plasma processing apparatus, a predetermined process is performed by applying plasma to a substrate to be processed in a vacuum chamber whose inside can be hermetically closed. For example, in a so-called parallel plate type plasma processing apparatus, an upper electrode and a lower electrode are provided in the vacuum chamber so as to face in parallel. Then, the substrate to be processed is placed on the lower electrode, high-frequency power is supplied between the upper electrode and the lower electrode to generate plasma, and the plasma is applied to the substrate to be processed to perform a predetermined process. It is configured as follows.
すなわち、 上記のようなプラズマ処理装置では、 下部電極が被処理基 板の支持台を兼ねた構成となっている。 そして、 この下部電極に対する 被処理基板の搬入搬出は、 通常、 搬送機構によって自動的に行うように なっている。 That is, in the above-described plasma processing apparatus, the lower electrode also serves as a support for the substrate to be processed. And for this lower electrode The loading and unloading of substrates to be processed is usually automatically performed by a transport mechanism.
このため、 下部電極上への被処理基板の載置及び下部電極上に載置さ れた被処理基板の取り出しを容易に行えるように、 下部電極には、 この 下部電極を上下方向に貫通するように基板支持部材が設けられている。 そして、 この基板支持部材と下部電極とを相対的に上下動させることに よって、 基板支持部材を下部電極上に突出させて基板支持部材によって 下部電極上に被処理基板を支持した状態、 及び、 この状態から基板支持 部材を下部電極内に引っ込めて下部電極上に被処理基板を載置した状態 とすることができるように構成されている。  For this reason, the lower electrode penetrates the lower electrode vertically so that the substrate to be processed is placed on the lower electrode and the substrate to be processed placed on the lower electrode can be easily taken out. Thus, a substrate supporting member is provided. And, by moving the substrate support member and the lower electrode relatively up and down, the substrate support member protrudes above the lower electrode, and the substrate to be processed is supported on the lower electrode by the substrate support member; and From this state, the substrate supporting member is retracted into the lower electrode, and the substrate to be processed can be placed on the lower electrode.
なお、 上記の基板支持部材は、 ピン状 (細長い棒状) に形成されたも のが多い。 そして、 このピン状の基板支持部材を 3個若しくは 4個程度 設け、 3点若しくは 4点で被処理基板を支持するように構成されたもの が多い。 また、 このような基板支持部材を設けるため、 下部電極には、 上下方向に貫通する貫通孔が、 3個若しくは 4個設けられている。 上述したとおり、 プラズマ処理装置においては、 被処理基板の支持台 を兼ねた下部電極に、 ピン状等の基板支持部材を設けるための貫通孔が 設けられている。 そして、 プラズマ処理中には、 基板支持部材を下部電 極内に引っ込めた状態とし、 下部電極の上面で被処理基板を支持した状 態で処理を行っている。  In addition, the above-mentioned substrate support member is often formed in a pin shape (elongated rod shape). In many cases, about three or four pin-shaped substrate support members are provided, and the substrate to be processed is supported at three or four points. Further, in order to provide such a substrate support member, three or four through holes are provided in the lower electrode so as to penetrate in the vertical direction. As described above, in the plasma processing apparatus, the lower electrode also serving as a support for the substrate to be processed is provided with a through-hole for providing a pin-shaped substrate support member or the like. During the plasma processing, the substrate support member is retracted into the lower electrode, and the processing is performed while the substrate to be processed is supported on the upper surface of the lower electrode.
しかしながら、 上述した従来のプラズマ処理装置では、 下部電極上に 載置された被処理基板が、 上述した貫通孔の部分で、 下部電極と非接触 の状態となっている。  However, in the above-described conventional plasma processing apparatus, the substrate to be processed mounted on the lower electrode is in a non-contact state with the lower electrode at the portion of the through hole described above.
このため、 この貫通孔の部分の処理速度が他の部分と異なる、 例えば 貫通孔の部分のエッチングレートが他の部分に比べて遅くなる等の現象 が生じ、 被処理基板の面内の処理の均一性が損なわれるという問題があ る o 発明の開示 For this reason, the processing speed of the through-hole portion is different from that of the other portions, for example, a phenomenon that the etching rate of the through-hole portion is slower than that of the other portions occurs. The problem of loss of uniformity O Disclosure of the invention
本発明の目的は、 被処理基板の全面に亙って均一な処理を行うことが でき、 従来に比べて、 被処理基板の面内の処理の均一性を向上させるこ とのできるプラズマ処理装置及びプラズマ処理方法を提供することにあ o  SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma processing apparatus capable of performing uniform processing over the entire surface of a substrate to be processed and improving the uniformity of processing within the surface of the substrate to be processed, as compared with the related art. And to provide a plasma processing method.
本発明は、 内部を気密に閉塞可能とされ、 被処理基板にプラズマを作 用させて所定の処理を施すための真空チャンバと、 前記真空チャンバ内 に設けられ、 上面に形成された載置面上に前記被処理基板を載置するよ う構成された電極と、 前記電極を貫通するように設けられ、 当該電極に 対して相対的に上下動することにより、 前記被処理基板の裏面側を支持 して、 前記載置面の上方と前記載置面との間で前記被処理基板を上下動 させる基板支持部材とを具備したプラズマ処理装置であって、 前記基板 支持部材が、 前記電極と電気的に接続され、 かつ、 前記被処理基板の処 理中に、 前記基板支持部材が前記被処理基板の裏面に当接された状態に 維持されるよう構成されたことを特徴とする。  According to the present invention, there is provided a vacuum chamber which is capable of airtightly closing the inside thereof, performs a predetermined process by applying plasma to a substrate to be processed, and a mounting surface provided in the vacuum chamber and formed on an upper surface. An electrode configured to place the substrate to be processed thereon, and an electrode provided so as to penetrate the electrode, and by moving up and down relatively to the electrode, the back side of the substrate to be processed is moved. A plasma processing apparatus, comprising: a substrate supporting member configured to support and move the substrate to be processed up and down between the mounting surface and the mounting surface. The apparatus is characterized in that it is electrically connected and that the substrate support member is kept in contact with the back surface of the substrate to be processed during the processing of the substrate to be processed.
また、 本発明は、 上記プラズマ処理装置において、 前記電極に高周波 電力を供給するよう構成されたことを特徴とする。  Further, the present invention is characterized in that in the above-mentioned plasma processing apparatus, high-frequency power is supplied to the electrode.
また、 本発明は、 上記プラズマ処理装置において、 前記基板支持部材 が、 ピン状に形成され、 弾性的に伸縮自在とされたことを特徴とする。 また、 本発明は、 上記プラズマ処理装置において、 前記ピン状に形成 された基板支持部材が、 上下動可能とされた支持体上に 4本設けられて いることを特徴とする。  Further, the present invention is characterized in that, in the plasma processing apparatus, the substrate support member is formed in a pin shape and is elastically expandable and contractible. Further, the present invention is characterized in that, in the above-described plasma processing apparatus, four pin-shaped substrate support members are provided on a vertically movable support.
また、 本発明は、 上記プラズマ処理装置において、 前記ピン状に形成 された基板支持部材の前記被処理基板裏面との当接部が、 導電性の樹脂 材料または保護膜により構成されていることを特徴とする。 The present invention also provides the plasma processing apparatus, wherein the contact portion of the pin-shaped substrate support member with the back surface of the substrate to be processed is made of a conductive resin. It is characterized by being composed of a material or a protective film.
また、 本発明は、 上記プラズマ処理装置において、 前記被処理基板に プラズマを作用させてエツチング処理を施すことを特徴とする。  Further, the present invention is characterized in that, in the plasma processing apparatus, an etching process is performed by applying plasma to the substrate to be processed.
また、 本発明方法は、 上記プラズマ処理装置を用い、 前記被処理基板 にプラズマを作用させて所定の処理を施すことを特徴とする。 図面の簡単な説明  The method of the present invention is characterized in that a predetermined process is performed by applying plasma to the substrate to be processed using the plasma processing apparatus. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明のプラズマ処理装置の一実施形態の概略構成を模式的 に示す図。  FIG. 1 is a diagram schematically showing a schematic configuration of an embodiment of the plasma processing apparatus of the present invention.
図 2は、 図 1のプラズマ処理装置の要部構成を拡大して模式的に示す 図。 発明を実施するための最良の形態  FIG. 2 is a diagram schematically showing an enlarged main part configuration of the plasma processing apparatus of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の詳細を、 実施の形態について、 図面を参照して説明す る。  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
図 1は、 本発明を、 ウェハのエッチングを行うプラズマエッチング装 置に適用した実施の形態の構成の概略を模式的に示すものである。 同図 において、 符号 1は、 材質が例えばアルミニウム等からなり、 内部を気 密に閉塞可能に構成され、 円筒状のプラズマ処理室を構成する真空チヤ ンバを示している。  FIG. 1 schematically shows an outline of a configuration of an embodiment in which the present invention is applied to a plasma etching apparatus for etching a wafer. In the figure, reference numeral 1 denotes a vacuum chamber which is made of, for example, aluminum or the like and is configured so as to be able to hermetically close the inside thereof, and forms a cylindrical plasma processing chamber.
この真空チャンバ 1の上部には、 シールドボヅクス 1 0が設けられて いる。 また、 真空チャンバ 1の下部には、 後述する下部電極 2を上下に 移動させるための駆動機構 2 0が設けられている。  A shield box 10 is provided above the vacuum chamber 1. A drive mechanism 20 for moving a lower electrode 2 described later up and down is provided below the vacuum chamber 1.
上記真空チャンバ 1の内部には、 被処理基板としてのウェハ Wを、 被 処理面を上側に向けて略水平に支持する下部電極 2が設けられている。 そして、 この下部電極 2 と平行に対向するように、 真空チャンバ 1内の 天井部には、 上部電極 3が設けられている。 Inside the vacuum chamber 1, there is provided a lower electrode 2 for supporting a wafer W as a substrate to be processed substantially horizontally with the surface to be processed facing upward. Then, in the vacuum chamber 1 so as to face the lower electrode 2 in parallel. An upper electrode 3 is provided on the ceiling.
この上部電極 3には、 図示しない多数の透孔が形成され、 所謂シャ ヮ一ヘッ ドが構成されている。 そして、 これらの透孔から、 図示しない 処理ガス供給源から供給された所定の処理ガスを、 下部電極 2上に設け られたウェハ Wに向けて均一に送出できるように構成されている。 一方、 真空チャンバ 1の底部には、 図示しない排気口が設けられており、 図示 しない真空ポンプ等の排気機構により、 真空チャンバ 1内を所定の真空 度まで排気できるように構成されている。  The upper electrode 3 is formed with a large number of through holes (not shown) to form a so-called short head. A predetermined processing gas supplied from a processing gas supply source (not shown) can be uniformly delivered from these through holes toward the wafer W provided on the lower electrode 2. On the other hand, an exhaust port (not shown) is provided at the bottom of the vacuum chamber 1 so that the inside of the vacuum chamber 1 can be exhausted to a predetermined degree of vacuum by an exhaust mechanism such as a vacuum pump (not shown).
また、 上部電極 3は、 整合器 2 1を介して高周波電源 2 2と電気的に 接続されており、 上部電極 3に所定の周波数 (例えば、 3 8 0 K H z〜 1 0 0 M H z ) の高周波電力を供給可能に構成されている。  The upper electrode 3 is electrically connected to a high-frequency power supply 22 via a matching box 21 so that the upper electrode 3 has a predetermined frequency (for example, 380 kHz to 100 MHz). It is configured to be able to supply high frequency power.
また、 上記下部電極 2と上部電極 3との間に位置するように、 真空 チャンバ 1の天井側から支持されたリング状のクランプリング 4が設け られている。 このクランプリング 4は、 クランプリング駆動機構 4 aに よって、 上下方向に移動可能に構成されている。 そして、 これらのクラ ンプリング 4及びクランプリング駆動機構 4 aによって、 ウェハ Wの周 縁部を下部電極 2側に押圧し、 ウェハ Wを下部電極 2上に固定するよう に構成されている。  Also, a ring-shaped clamp ring 4 supported from the ceiling side of the vacuum chamber 1 is provided between the lower electrode 2 and the upper electrode 3. The clamp ring 4 is configured to be vertically movable by a clamp ring drive mechanism 4a. The clamping ring 4 and the clamp ring driving mechanism 4 a press the peripheral portion of the wafer W toward the lower electrode 2, and fix the wafer W on the lower electrode 2.
また、 下部電極 2には、 冷媒を循環するための冷媒流路 (図示せず) と、 冷媒からの冷熱を効率よくウェハ Wに伝達するためにウェハ Wの裏 面に H eガスを供給するガス導入機構 (図示せず) とが設けられ、 ゥェ ハ Wを所望の温度に温度制御できるようになつている。 また、 下部電極 2の上面 (ウェハ Wの載置面) には、 ウェハ Wの裏面を傷付けないよう に、 図示しない樹脂製の膜が設けられている。  In addition, a coolant flow path (not shown) for circulating a coolant is provided to the lower electrode 2, and He gas is supplied to the back surface of the wafer W in order to efficiently transmit cold heat from the coolant to the wafer W. A gas introduction mechanism (not shown) is provided to control the temperature of the wafer W to a desired temperature. Further, a resin film (not shown) is provided on the upper surface of the lower electrode 2 (the mounting surface of the wafer W) so as not to damage the rear surface of the wafer W.
また、 下部電極 2は、 例えば、 ボール捩子及びこのボール捩子を回転 させるモー夕等からなる前記した駆動機構 2 0によって上下動可能に構 成されている。 そして、 下部電極 2と真空チャンバ 1内の底部との間に は、 これらの間を気密に閉塞するためのステンレス鋼等からなるベロ一 ズ 5が設けられている。 The lower electrode 2 is configured to be vertically movable by the above-described driving mechanism 20 including, for example, a ball screw and a motor for rotating the ball screw. Has been established. A bellows 5 made of stainless steel or the like is provided between the lower electrode 2 and the bottom in the vacuum chamber 1 to hermetically close the space therebetween.
さらに、 下部電極 2の中央部には、 基板支持部材としての後述するリ フタ一ピンが複数 (本例では 4本) 設けられたリフタ一ュニヅ ト 6が設 けられている。 そして、 下部電極 2の上下動に伴って、 リフ夕一ピンが 下部電極 2に設けられた透孔 2 aを貫通して、 下部電極 2上に突出可能 に構成されている。  Further, a lifter unit 6 provided with a plurality (four in this example) of lifter pins described later as a substrate support member is provided at the center of the lower electrode 2. Then, as the lower electrode 2 moves up and down, the lifter pin is configured to be able to protrude above the lower electrode 2 through the through hole 2 a provided in the lower electrode 2.
なお、 図 1において、 符号 7は、 整合器 2 3を介して高周波電源 2 4 から所定の周波数 (例えば、 3 8 0 K H z〜 4 0 . 6 8 M H z ) の高周 波電力を下部電極 2に供給するための R F口ッ ドを示している。 また、 符号 8は下部電極 2内に設けられた温度センサからの検出信号を導出す るための温度センサ用ケーブルを示している。  In FIG. 1, reference numeral 7 denotes a high frequency power of a predetermined frequency (for example, 380 kHz to 40.6 MHz) from the high frequency power supply 24 via the matching unit 23, and 2 shows the RF port to supply to 2. Reference numeral 8 denotes a temperature sensor cable for deriving a detection signal from a temperature sensor provided in the lower electrode 2.
次に、 上述したリフ夕一ユニッ ト 6の構成について、 図 2を参照して 説明する。 なお、 図 2は、 リフ夕一ユニッ ト 6の構成を模式的に示すも ので、 図中の中央部分に示す一点鎖線の左側部分は、 リフターピン 6 0 を下降させた状態を示し、 一点鎖線の右側部分は、 リフターピン 6 0を 上昇させた状態を示している。  Next, the configuration of the above-described rifle unit 6 will be described with reference to FIG. Note that FIG. 2 schematically shows the configuration of the lifter unit 6, and the left side of the dashed line shown in the center of the figure shows the state in which the lifter pin 60 is lowered. The right side of indicates that the lifter pin 60 has been raised.
図 2に示すリフターピン 6 0は、 下部電極 2に設けられた透孔 2 aを 貫通するように配置されており、 その下側端部が基台 6 1に捩子止め等 により固定されている。 このリフターピン 6 0は、 通常 3乃至 4本程度 設けられる。 本実施形態では、 基台 6 1にリフターピン 6 0が 4本固定 されており、 これらのリフ夕一ピン 6 0は、 下部電極 2の中心の回りに、 対称に配置されている。  The lifter pins 60 shown in FIG. 2 are arranged so as to penetrate through holes 2 a provided in the lower electrode 2, and the lower end thereof is fixed to the base 61 by screwing or the like. I have. Usually, about three or four lifter pins 60 are provided. In the present embodiment, four lifter pins 60 are fixed to the base 61, and these lift pins 60 are symmetrically arranged around the center of the lower electrode 2.
上記基台 6 1の中央部には、 透孔 6 1 aが設けられている。 そして、 この透孔 6 1 aに支軸 6 2を下側から挿入し、 支軸 6 2の上側端部を、 下部電極 2に捩子等によって固定するとともに、 支軸 6 2の下側端部に 設けられたス トヅパ 6 3で基台 6 1を支持することにより、 基台 6 1が 下部電極 2に対して相対的に上下動可能なように支持されている。 また、 支軸 6 2には、 リフタスプリング 6 4が設けられており、 下部電極 2に 対して基台 6 1を下側に向けて (リフ夕一ピン 6 0が下降する方向に向 けて) 付勢するように構成されている。 A through hole 61 a is provided in the center of the base 61. Then, the support shaft 62 is inserted into the through hole 61a from below, and the upper end of the support shaft 62 is The base 61 is fixed to the lower electrode 2 with screws or the like, and the base 61 is supported by a stopper 63 provided at the lower end of the support shaft 62. Are supported so as to be relatively vertically movable. Further, a lifter spring 64 is provided on the support shaft 62 so that the base 61 is directed downward with respect to the lower electrode 2 (in the direction in which the lift pin 60 descends). ) Is configured to be biased.
また、 基台 6 1の下部には、 リフ夕一シャフ ト 6 5、 ロッ ド 6 6が設 けられており、 これらのリフ夕一シャフ ト 6 5、 ロッ ド 6 6を介して、 基台 6 1の底部が押圧され、 リフ夕スプリング 6 4を収縮させつつ基台 6 1が下部電極 2に対して相対的に上方に移動し、 下部電極 2の上面に リフ夕—ピン 6 0が突出するように構成されている。 なお、 かかるリフ 夕一シャフ ト 6 5及びロッ ド 6 6による基台 6 1の底部の押圧は、 下部 電極 2側を上下動させるか、 又は、 リフ夕一シャフ ト 6 5及びロッ ド 6 6を上下動させることによって行われる。  At the lower part of the base 61, there are provided a lift shaft 65 and a rod 66, and through these lift shaft 65 and the rod 66, the base is provided. The bottom of 6 1 is pressed, and the base 6 1 moves upward relative to the lower electrode 2 while contracting the lift spring 6 4, and the lift pin 60 protrudes from the upper surface of the lower electrode 2. It is configured to be. The bottom of the base 61 is pressed by the lift shaft 65 and the rod 66 by moving the lower electrode 2 up and down, or by the lift shaft 65 and the rod 66. Is performed by moving up and down.
さらに、 上記リフ夕一ピン 6 0には、 図示しないバネ (コイルスプリ ング等) が内蔵され、 図 2の右側端部に示すように、 所定ストローク S 、 例えば 3 m m程度、 弾性的に伸縮可能に構成されている。 また、 リフ 夕一ピン 6 0の先端部には、 導電性の樹脂、 例えば導電性のテフロン (登録商標) によるコーティング膜 6 0 aが被着され、 このコ一ティン グ膜 6 0 aを介してリフ夕一ピン 6 0の頂部がウェハ Wの裏面に当接す るよう構成されている。 なお、 被膜層を形成するに限らず、 導電性の樹 脂材料をリフ夕一ピン 6 0の先端部に接着等により取り付けるように構 成してもよい。  Further, a spring (coil spring, etc.) (not shown) is built in the lift pin 60, and as shown in the right end of FIG. 2, a predetermined stroke S, for example, about 3 mm, is elastically expandable and contractable. It is configured. Further, a coating film 60a made of a conductive resin, for example, conductive Teflon (registered trademark) is applied to a tip portion of the rifle pin 60, and the coating film 60a is applied through the coating film 60a. The top of the pin 60 is in contact with the back surface of the wafer W. It should be noted that the present invention is not limited to the formation of the coating layer, and a configuration may be adopted in which a conductive resin material is attached to the tip of the pin 60 by bonding or the like.
上記リフ夕一ピン 6 0、 基台 6 1、 支軸 6 2及びリフ夕スプリング 6 4等は、 例えば、 ステンレス鋼等の導電性の材料から構成されている。 また、 上記コーティング膜 6 0 aも導電性とされていることから、 ゥェ ハ Wの裏面に当接するリフ夕一ピン 6 0の頂部は、 下部電極 2 と電気的 に接続された状態となっており、 実質的に下部電極 2と同電位となって いる。 。 The rifle pin 60, the base 61, the support shaft 62, the rifle spring 64, and the like are made of a conductive material such as stainless steel. Further, since the coating film 60a is also conductive, (C) The top of the riff pin 60 contacting the rear surface of W is in a state of being electrically connected to the lower electrode 2 and has substantially the same potential as the lower electrode 2. .
なお、 上記コ一ティング膜 6 0 aは、 ウェハ Wの裏面に傷が付くこと を防止するためのものであり、 処理の均一性を向上させるためには、 で きる限り薄くすることが好ましく、 その厚さは、 例えば、 5 0〃m〜 2 0 0 / m程度とすることが好ましい。 また、 コ一ティング膜 6 0 aを設 けずに、 リフ夕一ピン 6 0の先端部を機械加工して、 ウェハ Wの裏面に 傷が付くことを防止することも可能である。  The coating film 60a is for preventing the back surface of the wafer W from being scratched. In order to improve the processing uniformity, it is preferable to make the coating film as thin as possible. The thickness is preferably, for example, about 50 5m to 200 / m. Further, it is possible to prevent the back surface of the wafer W from being scratched by machining the tip of the lift pin 60 without providing the coating film 60a.
そして、 下部電極 2に対してリフ夕一ピン 6 0を相対的に下降させ、 下部電極 2上に載置されたウェハ Wを前述したクランプリング 4で固定 してウェハ Wに所定のエッチング処理を行っている間は、 図 2の左側部 分に示すように、 リフ夕一ピン 6 0の頂部が、 リフ夕一ビン 6 0に内蔵 されたバネによってウェハ Wの裏面に押圧された状態 (同図に示すリフ 夕一ピン 6 0の残りのストローク S 1 が例えば 1mm 程度となる状態) となる。 これによつて、 ウェハ W裏面の透孔 2 aに対応する部分の大部 分が、 このリフ夕一ピン 6 0の頂部が当接されることによって、 電気的 には、 実質的に下部電極 2に接触された状態と同様な状態に保たれるよ うになつている。  Then, the lift pins 60 are relatively lowered with respect to the lower electrode 2, and the wafer W mounted on the lower electrode 2 is fixed by the clamp ring 4 described above, and a predetermined etching process is performed on the wafer W. During this operation, the top of the pin 60 is pressed against the back surface of the wafer W by a spring built in the bin 60 as shown on the left side of FIG. (The remaining stroke S 1 of the pin 60 shown in the figure is, for example, about 1 mm). As a result, most of the portion corresponding to the through-hole 2a on the back surface of the wafer W is brought into contact with the top of the pin 60, so that the lower electrode is substantially electrically electrically connected. The state is kept the same as the state of contact with 2.
この時、 4本設けられた夫々のリフ夕一ピン 6 0が、 夫々内蔵された 個別のパネの弾性力によって、 ウェハ Wの裏面に当接されるので、 例え ば、 各リフターピン 6 0の頂部 (ウェハ Wとの当接面) の高さに僅かな ずれがあっても、 各リフ夕一ピン 6 0を 4本とも確実にウェハ Wの裏面 に当接された状態とすることができる。  At this time, each of the four provided lift pins 60 is brought into contact with the back surface of the wafer W by the elastic force of each built-in individual panel. For example, each lifter pin 60 Even if there is a slight deviation in the height of the top (the contact surface with the wafer W), it is possible to ensure that all four pins 60 of each rift are securely in contact with the back surface of the wafer W. .
—方、 ウェハ Wを下部電極 2に対して搬入、 搬出する際には、 図 2の 右側部分に示すように、 下部電極 2に対してリフ夕一ピン 6 0を相対的 に上昇させ、 リフ夕一ピン 6 0が下部電極 2上に突出した状態とし、 4 本のリフターピン 6 0によって、 ウェハ Wを下部電極 2上に持ち上げた 状態に支持するようになっている。 この際、 ウェハ Wを保持した状態で リフ夕一ピン 6 0はほとんど収縮せず、 リフ夕一ピン 6 0が最下点まで 下降した状態で、 リフターピン 6 0の先端部は、 下部電極 2の上面に全 ストローク S (例えば 3mm ) からス トローク S i 減算した値だけ突出 するように各リフタ一ピン 6 0に内蔵されたパネの弾性力が設定されて いる。 On the other hand, when loading and unloading the wafer W to and from the lower electrode 2, as shown on the right side of FIG. The wafer W is lifted above the lower electrode 2 by four lifter pins 60 so that the wafer W is supported by the four lifter pins 60. At this time, with the wafer W held, the lift pin 60 hardly shrinks, the lift pin 60 descends to the lowest point, and the tip of the lifter pin 60 is connected to the lower electrode 2. The elastic force of the panel built in each lifter pin 60 is set on the upper surface of the panel so as to protrude by a value obtained by subtracting the stroke S i from the total stroke S (for example, 3 mm).
次に、 このように構成されたプラズマエッチング装置におけるプラズ マエッチング処理について説明する。  Next, a plasma etching process in the plasma etching apparatus configured as described above will be described.
まず、 図示しないゲートバルブを開放し、 このゲートバルブに隣接し て配置された図示しないロードロック室を介して、 自動搬送機構の搬送 ァ一ム等によりウェハ Wが真空チャンバ 1内に搬入される。 この時、 予 め下部電極 2が所定の位置に下降され、 下部電極 2上に 4本のリフ夕一 ピン 6 0が突出した状態とされており、 これらのリフ夕一ピン 6 0の上 に、 ウェハ Wが載置される。 ウェハ W載置後、 搬送アームを真空チャン バ 1外へ退避させ、 ゲ一トバルブが閉じられる。  First, a gate valve (not shown) is opened, and the wafer W is loaded into the vacuum chamber 1 by a transfer ham of an automatic transfer mechanism or the like via a load lock chamber (not shown) arranged adjacent to the gate valve. . At this time, the lower electrode 2 is lowered to a predetermined position in advance, and the four riff pins 60 are projected on the lower electrode 2. The wafer W is placed. After placing the wafer W, the transfer arm is retracted out of the vacuum chamber 1, and the gate valve is closed.
この後、 駆動機構 2 0によって下部電極 2が所定の高さまで上昇され、 これに伴って、 リフ夕一ピン 6 0の略全体が下部電極 2内に収容された 状態となる。 そして、 ウェハ Wの周縁部がクランプリング 4によって下 部電極 2に押圧され、 ウェハ Wが下部電極 2上に固定される。 この時、 前述した図 2の左側部分に示すように、 各リフターピン 6 0の頂部は、 リフ夕一ピン 6 0内に内蔵されたバネによって弹性的にウェハ Wの裏面 に当接された状態とされている。  Thereafter, the lower electrode 2 is raised to a predetermined height by the drive mechanism 20, and accordingly, substantially the entirety of the lift pin 60 is housed in the lower electrode 2. Then, the peripheral edge of the wafer W is pressed against the lower electrode 2 by the clamp ring 4, and the wafer W is fixed on the lower electrode 2. At this time, as shown in the left part of FIG. 2 described above, the top of each lifter pin 60 is in a state of being abutted on the back surface of the wafer W by the spring built in the lifter pin 60. It has been.
しかる後、 排気機構により、 真空チャンバ 1内が排気されるとともに- 上部電極 3の透孔を介して、 真空チャンバ 1内に所定の処理ガスが、 例 えば 100〜 1 000 s c c mの流量で導入され、 真空チャンバ 1内が 所定の圧力、 例えば 1. 33〜: L 33 P a ( 1 0〜: L O O OmT o r r) 、 好ましくは 2. 67〜26. 7 P a (2 0〜200mT o r r) 程度に保持される。 After that, the inside of the vacuum chamber 1 is evacuated by the exhaust mechanism, and a predetermined processing gas is introduced into the vacuum chamber 1 through the through hole of the upper electrode 3, for example. For example, it is introduced at a flow rate of 100 to 1 000 sccm, and the inside of the vacuum chamber 1 has a predetermined pressure, for example, 1.33 to: L33Pa (10 to: LOO OmT orr), preferably 2.67 to 26.7. It is kept at about P a (20 to 200 mT orr).
そして、 この状態で高周波電源 2 2、 24から、 上部電極 3、 下部電 極 2に、 周波数が例えば 380KH z〜 100MH zの高周波電力が供 給され、 真空チヤンバ 1内に供給された処理ガスがプラズマ化されて、 そのプラズマによりウェハ W上の所定の膜がエッチングされる。  Then, in this state, high-frequency power having a frequency of, for example, 380 KHz to 100 MHz is supplied from the high-frequency power supplies 22 and 24 to the upper electrode 3 and the lower electrode 2, and the processing gas supplied into the vacuum chamber 1 is supplied. The film is turned into plasma, and a predetermined film on the wafer W is etched by the plasma.
この時、 前述したとおり、 下部電極 2と電気的に接続された各リフ 夕一ピン 60の頂部が、 ウェハ Wの裏面と当接されている。 これによつ て、 下部電極 2の透孔 2 aの部分でエッチングレートが低下する等、 処 理が不均一になることが抑制され、 ウェハ Wのエッチング処理の面内均 一性を向上させることができる。  At this time, the top of each rifle pin 60 electrically connected to the lower electrode 2 is in contact with the back surface of the wafer W as described above. This suppresses non-uniform processing, such as a decrease in the etching rate at the portion of the through-hole 2 a of the lower electrode 2, and improves in-plane uniformity of the etching processing of the wafer W. be able to.
そして、 所定のエッチング処理が実行されると、 高周波電源 2 2、 2 4からの高周波電力の供給及び処理ガスの供給が停止され、 エッチング 処理が停止されて、 上述した手順とは逆の手順で、 ウェハ Wが真空チヤ ンバ 1外に搬出される。  When the predetermined etching process is performed, the supply of the high-frequency power from the high-frequency power sources 22 and 24 and the supply of the processing gas are stopped, the etching process is stopped, and the procedure is reverse to the procedure described above. Then, the wafer W is carried out of the vacuum chamber 1.
上述したエッチング装置を用いて、 真空チャンバ 1内の圧力を 26. 7 P a (2 00mT o r r) 、 処理ガスを C H F3 (流量 45SCCM) + C F4 (流量 90SCCM) + A r (流量 600SCCM ) 、 高周波電力を 1 1 00Wとして、 PR (フォトレジス ト) ノで£ 03ノ3 :102 が形成さ れたウェハ Wのエッチングを 60秒間行った。 この結果、 各リフ夕ーピ ン 60 (透孔 2 a ) に対応するウェハ Wの部分のェヅチングレートの低 下が抑制され、 ウェハ Wのエッチングレートの面内均一性が 3. 7%と なった。 また、 同様な条件で、 各リフ夕一ビン 6 0を、 パネを内蔵し ないものに変更し、 これらのリフ夕一ピン 60の頂部をウェハ Wの裏面 に接触させた状態でエッチング処理を行った。 この結果、 エッチング レートの面内均一性が 5 . 0 %となった。 Using the etching apparatus described above, the pressure in the vacuum chamber 1 was 26.7 Pa (200 mTorr), and the processing gas was CHF 3 (flow rate 45 SCCM) + CF 4 (flow rate 90 SCCM) + Ar (flow rate 600 SCCM). the high-frequency power as 1 1 00W, PR (photoresist g) in Bruno £ 03 Bruno 3:10 2 went 60 seconds etching of the wafer W is formed. As a result, a decrease in the etching rate of the portion of the wafer W corresponding to each of the lift pins 60 (through holes 2a) was suppressed, and the in-plane uniformity of the etching rate of the wafer W was 3.7%. . Also, under the same conditions, each of the ribs 60 was changed to one without a built-in panel. The etching process was performed in the state of being brought into contact with the substrate. As a result, the in-plane uniformity of the etching rate was 5.0%.
また、 比較のため、 各リフターピン 6 0を、 ウェハ Wの裏面に接触さ せず、 同様な条件でエッチング処理を行った。 この結果、 各リフ夕一ピ ン 6 0 (透孔 2 a ) に対応するウェハ Wの部分のエッチングレートが低 下し、 エッチングレートの面内均一性が 1 3 . 9 %となった。  For comparison, each lifter pin 60 was etched under the same conditions without contacting the back surface of the wafer W. As a result, the etching rate of the portion of the wafer W corresponding to each rifle pin 60 (through hole 2a) was reduced, and the in-plane uniformity of the etching rate was 13.9%.
上記の結果から明らかなように、 エッチング処理中に、 下部電極 2と 電気的に接続された状態のリフ夕一ピン 6 0の頂部をウェハ Wの裏面に 接触させることによって、 エッチングレートの面内均一性を大幅に向上 させることができた。 また、 パネを内蔵したリフターピン 6 0を使用し てリフ夕一ピン 6 0を確実にウェハ Wの裏面に接触させるようにするこ とによって、 さらにエッチングレートの面内均一性を大幅に向上させる ことができた。  As is evident from the above results, during the etching process, the top of the pin 60, which is electrically connected to the lower electrode 2, is brought into contact with the back surface of the wafer W, so that the in-plane etching rate is reduced. The uniformity was greatly improved. In addition, the use of lifter pins 60 with built-in panels ensures that the pins 60 are in contact with the back surface of the wafer W, thereby greatly improving the in-plane uniformity of the etching rate. I was able to.
なお、 上記実施の形態においては、 本発明をウェハ Wのエッチングを 行うエッチング装置に適用した場合について説明したが、 本発明はかか る場合に限定されるものではない。 例えば、 ウェハ W以外の基板を処理 するものであっても良く、 エッチング以外のプラズマ処理、 例えば C V D等の成膜処理装置にも適用することができる。  In the above embodiment, the case where the present invention is applied to the etching apparatus for etching the wafer W has been described, but the present invention is not limited to such a case. For example, it may be one that processes a substrate other than the wafer W, and may be applied to plasma processing other than etching, for example, a film forming apparatus such as a CVD.
また、 上記実施の形態においては、 基板支持部材として、 リ フ夕一ピ ン 6 0を 4本使用した場合について説明したが、 リフ夕一ピン 6 0の本 数は、 何本でも良く、 また、 ピン状の基板支持部材に限らず、 他の形状 の基板支持部材を用いることもできる。  Further, in the above embodiment, the case where four lift pins 60 are used as the substrate supporting member has been described. However, the number of lift pins 60 may be any number. However, the present invention is not limited to the pin-shaped substrate supporting member, and a substrate supporting member having another shape may be used.
以上説明したとおり、 本発明によれば、 被処理基板の全面に亙って均 一な処理を行うことができ、 従来に比べて、 被処理基板の面内の処理の 均一性を向上させることができる。 産業上の利用可能性 As described above, according to the present invention, uniform processing can be performed over the entire surface of a substrate to be processed, and the uniformity of processing within the surface of the substrate to be processed can be improved as compared with the related art. Can be. Industrial applicability
本発明に係るプラズマ処理装置及びプラズマ処理方法は、 半導体装置 の製造を行う半導体製造産業等において使用することが可能である。 し たがって、 本発明は産業上の利用可能性を有する。  INDUSTRIAL APPLICABILITY The plasma processing apparatus and the plasma processing method according to the present invention can be used in a semiconductor manufacturing industry or the like that manufactures semiconductor devices. Therefore, the present invention has industrial applicability.

Claims

請 求 の 範 囲 The scope of the claims
1 . 内部を気密に閉塞可能とされ、 被処理基板にプラズマを作用させて 所定の処理を施すための真空チャンバと、 1. A vacuum chamber for allowing the inside to be hermetically closed and for applying a predetermined process by applying plasma to the substrate to be processed;
前記真空チャンバ内に設けられ、 上面に形成された載置面上に前記被 処理基板を載置するよう構成された電極と、  An electrode provided in the vacuum chamber and configured to mount the substrate to be processed on a mounting surface formed on an upper surface;
前記電極を貫通するように設けられ、 当該電極に対して相対的に上下 動することにより、 前記被処理基板の裏面側を支持して、 前記載置面の 上方と前記載置面との間で前記被処理基板を上下動させる基板支持部材 とを具備したプラズマ処理装置であって、  The substrate is provided so as to penetrate the electrode, and moves up and down relatively to the electrode to support the back side of the substrate to be processed, and between the upper side of the mounting surface and the mounting surface. A substrate support member for vertically moving the substrate to be processed, and
前記基板支持部材が、 前記電極と電気的に接続され、 かつ、 前記被処 理基板の処理中に、 前記基板支持部材が前記被処理基板の裏面に当接さ れた状態に維持されるよう構成されたことを特徴とするプラズマ処理装  The substrate support member is electrically connected to the electrode, and the substrate support member is kept in contact with the back surface of the substrate to be processed during processing of the substrate to be processed. Plasma processing apparatus characterized by comprising
2 . 請求項 1記載のプラズマ処理装置において、 2. The plasma processing apparatus according to claim 1,
前記電極に高周波電力を供給するよう構成されたことを特徴とするプ ラズマ処理装置。  A plasma processing apparatus configured to supply high-frequency power to the electrode.
3 . 請求項 1記載のプラズマ処理装置において、  3. The plasma processing apparatus according to claim 1,
前記基板支持部材が、 ピン状に形成され、 弾性的に伸縮自在とされた ことを特徴とするプラズマ処理装置。  A plasma processing apparatus, wherein the substrate support member is formed in a pin shape and is elastically stretchable.
4 . 請求項 3記載のプラズマ処理装置において、  4. The plasma processing apparatus according to claim 3,
前記ピン状に形成された基板支持部材が、 上下動可能とされた支持体 上に 4本設けられていることを特徴とするプラズマ処理装置。  4. A plasma processing apparatus, wherein four pin-shaped substrate support members are provided on a vertically movable support.
5 . 請求項 3記載のプラズマ処理装置において、  5. The plasma processing apparatus according to claim 3,
前記ピン状に形成された基板支持部材の前記被処理基板裏面との当接 部が、 導電性の樹脂材料または保護膜により構成されていることを特徴 とするプラズマ処理装置。 A contact portion of the pin-shaped substrate support member with the back surface of the substrate to be processed is made of a conductive resin material or a protective film. Plasma processing apparatus.
6 . 請求項 1載のプラズマ処理装置において、  6. The plasma processing apparatus according to claim 1,
前記被処理基板にプラズマを作用させてエツチング処理を施すことを 特徴とするプラズマ処理装置。  A plasma processing apparatus, wherein an etching process is performed by applying plasma to the substrate to be processed.
7 . 請求項 1記載のプラズマ処理装置を用い、 前記被処理基板にプラズ マを作用させて所定の処理を施すことを特徴とするプラズマ処理方法。  7. A plasma processing method using the plasma processing apparatus according to claim 1, wherein predetermined processing is performed by applying plasma to the substrate to be processed.
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