WO2003028102A2 - Modification of the function of a chip using a multi-chip housing - Google Patents

Modification of the function of a chip using a multi-chip housing Download PDF

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Publication number
WO2003028102A2
WO2003028102A2 PCT/EP2002/009706 EP0209706W WO03028102A2 WO 2003028102 A2 WO2003028102 A2 WO 2003028102A2 EP 0209706 W EP0209706 W EP 0209706W WO 03028102 A2 WO03028102 A2 WO 03028102A2
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WIPO (PCT)
Prior art keywords
chip
functionality
interface
connections
housing
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PCT/EP2002/009706
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German (de)
French (fr)
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WO2003028102A3 (en
Inventor
Peter Poechmueller
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Infineon Technologies Ag
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Publication of WO2003028102A2 publication Critical patent/WO2003028102A2/en
Publication of WO2003028102A3 publication Critical patent/WO2003028102A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382—Adaptable interconnections, e.g. for engineering changes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

Definitions

  • the present invention relates to an electronic device in which a plurality of chips are housed in a multi-chip package in order to implement a modification of the functionality of one of the chips, and in particular to such an electronic device which allows flexible modification of high-volume semiconductor devices by using Multichip package enables.
  • the object of the present invention is to provide an electronic module which enables the implementation of special modules with reasonable effort. This object is achieved by an electronic module according to claim 1.
  • the present invention provides an electronic module with the following features:
  • a second chip housed in the multichip housing in operative connection with the first chip and external connections of the multichip housing, the second chip providing a modification of the predetermined functionality provided by the first chip at the external connections, so that only the external connections modified functionality is available.
  • the first chip is preferably a high-volume semiconductor component, i. H. High-volume chip, which is combined with the second chip, which can be referred to as a functionality modification chip, in a relatively inexpensive multi-chip housing in order to implement a changed application functionality.
  • the second chip which can be referred to as a functionality modification chip, in a relatively inexpensive multi-chip housing in order to implement a changed application functionality.
  • the multichip housing can be an existing and relatively inexpensive multichip housing that can have standardized dimensions and connection arrangements.
  • the functional connection of the functionality modification chip to the first chip preferably takes place via a first interface, which is connected to connections of the first
  • Chips is coupled, and via a second interface, which with at least part of the external connections of the multi chip housing is coupled.
  • the second chip can therefore be referred to as an interface chip.
  • Such an interface chip can be realized inexpensively in a very short time using today's logic design methods, so that special modules can be inexpensively realized by combining such an interface chip and a high-volume chip, for example a high-volume semiconductor memory, for example using an existing and relatively inexpensive multichip housing technology can.
  • the present invention is not limited to special modifications.
  • a modified functionality are, for example, different frequencies with which the interface chip communicates on the one hand with the high-volume chip and on the other hand with the outside world.
  • the special interface chip can be used to implement modified functionality in the sense of a modified memory technology, the high-volume chip, for example, providing the function of a synchronous DRAM memory, while the special interface chip on the outer connections of the multichip housing provides the functionality of a EDO memory is supplied.
  • the modification of the functionality can relate to different refreshing methods, different transmission bandwidths, different bus cycles and the like.
  • the present invention thus enables the use of high-volume chips, which retain their predetermined functionality in the electronic component according to the invention, for realizing special components, for example for niche markets which have so far not justified tapping due to the lengthy and costly development.
  • According to the invention for the production of such special building blocks realizes an interface chip together with the high-volume chip in a multichip housing, such an interface chip can be implemented inexpensively in a very short time using today's logic design methods and can also be implemented in a different technology than the high-volume chip.
  • This interface chip provides the functionality of the special module on the external connections of the multichip housing.
  • High-volume chip continues to work according to its predetermined functionality and the interface chip uses the “result” of the predetermined functionality in order to provide modified functionality at the external connections of a multichip housing.
  • the present invention can provide a high-volume chip that has undergone a complicated and lengthy product development. can be used to manufacture a large number of special components, each with slightly different functionality, for example.
  • Fig. 1 is a schematic, isometric representation of a
  • Fig. 2 is a schematic representation for explaining the present invention.
  • an electronic component comprises a multi-chip housing 10.
  • the multi-chip housing 10 is shown “transparently” in FIG. 1, so that the illustration shows a view of the relevant ones in FIG the multichip housing 10 arranged components allows.
  • the chips 12 and 14 may be arranged and packaged in the multi-chip package 10 in any manner using known techniques, for example using a carrier board or the like.
  • the interface chip 14 is mounted on the high-volume chip 12; high-volume chip is understood to be a chip whose number of production pieces justifies a complicated and lengthy development.
  • the high-volume chip 12 comprises a plurality of connections 16 in the form of connection surfaces.
  • the interface chip 14 also comprises a plurality of connections 18 in the form of connection surfaces.
  • five connections 16 are connected via bonding wires 20 to connecting lines 22 arranged in the multichip housing 10.
  • the connecting lines 22 can be provided, for example, on the above-mentioned carrier board in the multichip housing 10.
  • three connections of the high-volume chip 12 are connected to connections 18 of the interface chip 14 via bond wires 24.
  • two connection surfaces of the interface chip 14 are connected via bonding wires 25 to connecting lines 26 provided in the multichip housing 10, which can also be provided on the carrier board mentioned.
  • the inner connecting lines 22 and 26 are connected to outer connections 28 and 30 of the multichip housing.
  • the outer connections 28 and 30 can be connected to a communication bus (not shown) using conventional techniques in order to enable the electronic component according to the invention to communicate with the surroundings.
  • the electrical connections shown in FIG. 1 caused by bonding wires and connecting lines can be replaced by other contacting methods, for example flip-chip contacts and the like.
  • the illustration of FIG. 1 is to be regarded as purely schematic both with regard to the number of connection areas and connections and also with regard to which connections are connected to one another. It should be noted that, depending on the functionality modification that is to be provided by the interface chip 14 according to the invention, some or all of the connections of the chips are connected to one another and to the outer connections, so that the modified functionality is delivered to the outer connections.
  • the multichip housing 10 can be a conventional standard multichip housing which can have both standardized dimensions and standardized external connections or connection arrangements, so that the electronic component according to the invention can be easily integrated into electronic circuits.
  • the interface chip 14 thus has a first interface 32, via which it is coupled to the high-volume chip 12 or connections thereof using a suitable coupling device 34. Via a second interface 36, the interface chip 14 is in turn coupled to the external connections (not shown in FIG. 2) of the multichip housing 10 via a suitable coupling device 38.
  • the electronic module according to the invention can be connected to a communication bus (not shown) and thus to an external circuit 40 or an operating interface via the external connections.
  • the high-volume chip 12 provides a predetermined functionality at its connections 16.
  • This predetermined functionality tat is that of a 128 Mb DRAM memory in the embodiment shown.
  • the interface chip 14 now reads several bits in parallel from the connections 16 of the DRAM memory at a first frequency for which the high-volume chip 12 has been configured and developed. A parallel / serial conversion of the read bits then takes place in the interface chip 14 in order to generate a serial bit stream. This serial bit stream can then be output at a higher frequency compared to the frequency at which the bits are read in parallel from the connections 16 of the high-volume chip to the external connections of the multichip housing and thus to a communication bus of an external circuit.
  • the interface chip 14 provides a modification of the functionality provided by the high-volume chip. In this exemplary embodiment, this modification relates to the difference between the frequency with which the interface chip 14 communicates with the high-volume chip 12 via the interface 32 and the frequency with which the interface chip 14 communicates with an external circuit via the interface 36.
  • the interface chip can be designed in order to provide the functionality of an EDO memory on the external connections of the electronic module according to the invention.
  • the interface 32 shown in FIG. 2, which is used for communication with the high-volume chip 12, can be pre-developed for various applications, ie high-volume chip implementations.
  • various applications ie functionalities of special components, all that is required the respective application interface 36 through which the functionality is modified can also be implemented.
  • the advantage here is that the interface chip can be implemented in other technologies than the high-volume chip, ie high-volume module, so that the interface chip can be implemented inexpensively in a very short time using today's logic design methods.
  • the module according to the invention thus appears as a module that only supplies the modified functionality, the actual functionality of the first chip after being housed in the multichip housing no longer being accessible.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

The invention relates to an electronic component comprising a multi-chip housing (10), a first chip (12), which supplies a predetermined function and is housed in the multi-chip housing (10) and a second chip (14), which is housed in the multi-chip housing (10) and interacts with the first chip (12) and external connections (28, 30) of the multi-chip housing (10). The second chip (14) supplies a modification to the predetermined function supplied by the first chip (12) to the external connections (28, 30) of the multi-chip housing (10), in such a way that only the modified function is available at the external connections. The first chip (12) can be a high-volume chip, whereas the modified function can be that of a special component, whose production quantity does not justify a complex and lengthy product development.

Description

Beschreibungdescription
Modifikation der Funktionalität eines Chips unter Einsatz eines MultichipgehausesModification of the functionality of a chip using a multi-chip package
Die vorliegende Erfindung bezieht sich auf einen elektronischen Baustein, bei dem eine Mehrzahl von Chips in einem Multichipgehause gehaust sind, um eine Modifikation der Funktionalität von einem der Chips zu realisieren, und insbesondere einen solchen elektronischen Baustein, der eine flexible Modifikation von Hochvolumenhalbleiterbausteinen durch Einsatz von Multichipgehäusen ermöglicht.The present invention relates to an electronic device in which a plurality of chips are housed in a multi-chip package in order to implement a modification of the functionality of one of the chips, and in particular to such an electronic device which allows flexible modification of high-volume semiconductor devices by using Multichip package enables.
Heutige Halbleiterbausteine für Hochvolumenanwendungen erfor- dern eines sehr komplizierte und langwierige Produktentwicklung, um eine optimierte und kostengünstige Lösung zu erreichen. Dies ist insbesondere beispielsweise bei der Herstellung von dynamischen Halbleiterspeichern, sogenannten DRAMs, der Fall. Bei derartigen Bauelementen kann die Entwicklung eines neuen Produkts bis zu zwei Jahre dauern und Entwicklungskosten in zweistelliger Millionenhöhe verschlingen. Aus diesem Grund ist es kaum vertretbar, selbst relativ große Nischenmärkte mit entsprechend optimalen Produkten zu versorgen, beispielsweise Niederleistungs-DRAMs, Höchstfrequenz- DRAMs und dergleichen.Today's semiconductor devices for high-volume applications require a very complicated and lengthy product development in order to achieve an optimized and cost-effective solution. This is particularly the case, for example, in the production of dynamic semiconductor memories, so-called DRAMs. With such components, the development of a new product can take up to two years and devour development costs in the tens of millions. For this reason, it is hardly justifiable to supply even relatively large niche markets with correspondingly optimal products, for example low-power DRAMs, high-frequency DRAMs and the like.
Bisher mußte, um Nischenmärkte mit entsprechend optimalen Produkten zu versorgen, eine langwierige und kostspielige Entwicklung von entsprechenden Spezialbausteinen, wie sie o- ben angesprochen ist, erfolgen. Andernfalls erfolgte aufgrund schlechter Amortisationserwartungen keine Erschließung möglicher Märkte durch eine entsprechend langwierig und kostspielige Entwicklung von Spezialbausteinen.In the past, in order to supply niche markets with correspondingly optimal products, a lengthy and costly development of corresponding special modules, as mentioned above, had to take place. Otherwise, due to poor amortization expectations, there was no opening up of possible markets through a correspondingly lengthy and costly development of special components.
Die Aufgabe der vorliegenden Erfindung besteht darin, einen elektronischen Baustein zu schaffen, der mit vertretbarem Aufwand die Implementierung von Spezialbausteinen ermöglicht. Diese Aufgabe wird durch einen elektronischen Baustein gemäß Anspruch 1 gelöst.The object of the present invention is to provide an electronic module which enables the implementation of special modules with reasonable effort. This object is achieved by an electronic module according to claim 1.
Die vorliegende Erfindung schafft einen elektronischen Baustein mit folgenden Merkmalen:The present invention provides an electronic module with the following features:
einem Multichipgehause;a multichip housing;
einem ersten, in dem Multichipgehause gehäusten Chip, der eine vorbestimmte Funktionalität liefert; unda first chip packaged in the multi-chip package that provides predetermined functionality; and
einem zweiten, in dem Multichipgehause gehäusten Chip in Wirkverbindung mit dem ersten Chip und äußeren Anschlüssen des Multichipgehauses, wobei der zweite Chip eine Modifikation der von dem ersten Chip gelieferten, vorbestimmten Funktionalität an den äußeren Anschlüssen liefert, so daß an den äußeren Anschlüssen nur noch die modifizierte Funktionalität zur Verfügung steht.a second chip housed in the multichip housing in operative connection with the first chip and external connections of the multichip housing, the second chip providing a modification of the predetermined functionality provided by the first chip at the external connections, so that only the external connections modified functionality is available.
Erfindungsgemäß ist der erste Chip vorzugsweise ein Hochvolumenhalbleiterbaustein, d. h. Hochvolumenchip, der mit dem zweiten Chip, der als Funktionalitätsmodifikationschip bezeichnet werden kann, in einem relativ kostengünstigen Multi- chipgehäuse kombiniert ist, um eine geänderte Anwendungsfunktionalität zu realisieren. Auf diese Weise ist es erfindungsgemäß möglich, in kurzer Zeit neue Spezialbausteine ohne untragbar hohe Entwicklungskosten zu realisieren.According to the invention, the first chip is preferably a high-volume semiconductor component, i. H. High-volume chip, which is combined with the second chip, which can be referred to as a functionality modification chip, in a relatively inexpensive multi-chip housing in order to implement a changed application functionality. In this way it is possible according to the invention to realize new special components in a short time without prohibitively high development costs.
Erfindungsgemäß kann es sich bei dem Multichipgehause um ein existierendes und relativ kostengünstiges Multichipgehause handeln, das genormte Abmessungen und Anschlußanordnungen aufweisen kann. Die Wirkverbindung des Funktionalitätsmodifi- kationschips mit dem ersten Chip erfolgt vorzugsweise über eine erste Schnittstelle, die mit Anschlüssen des erstenAccording to the invention, the multichip housing can be an existing and relatively inexpensive multichip housing that can have standardized dimensions and connection arrangements. The functional connection of the functionality modification chip to the first chip preferably takes place via a first interface, which is connected to connections of the first
Chips gekoppelt ist, und über eine zweite Schnittstelle, die mit zumindest einem Teil der äußeren Anschlüsse des Multi- chipgehäuses gekoppelt ist. Der zweite Chip kann daher als ein Schnittstellen-Chip bezeichnet werden. Ein solcher Schnittstellen-Chip kann mit heutigen Logikentwurfsverfahren in kürzester Zeit kostengünstig realisiert werden, so daß durch eine Kombination eines solchen Schnittstellen-Chips und eines Hochvolumenchips, beispielsweise eines Hochvolumenhalbleiterspeichers, beispielsweise unter Verwendung einer existierenden und relativ kostengünstigen Multichipgehäusetechno- logie, kostengünstig Spezialbausteine realisiert werden kön- nen.Chips is coupled, and via a second interface, which with at least part of the external connections of the multi chip housing is coupled. The second chip can therefore be referred to as an interface chip. Such an interface chip can be realized inexpensively in a very short time using today's logic design methods, so that special modules can be inexpensively realized by combining such an interface chip and a high-volume chip, for example a high-volume semiconductor memory, for example using an existing and relatively inexpensive multichip housing technology can.
Hinsichtlich der Modifikation der Funktionalität eines Hochvolumenchips, die durch einen erfindungsgemäßen elektronischen Baustein geliefert werden kann, ist die vorliegende Er- findung nicht auf spezielle Modi ikationen begrenzt. Beispiele einer modifizierten Funktionalität sind beispielsweise unterschiedliche Frequenzen, mit denen der Schnittstellen-Chip zum einen mit dem Hochvolumenchip und zum anderen mit der Außenwelt kommuniziert. Ferner kann durch den Spezial- Schnittstellen-Chip eine modifizierte Funktionalität im Sinne einer geänderten Speichertechnologie implementiert werden, wobei der Hochvolumenchip beispielsweise die Funktion eines synchronen DRAM-Speichers liefert, während durch den SpezialSchnittstellen-Chip an den äußeren Anschlüssen des Multichip- gehäuses die Funktionalität eines EDO-Speichers geliefert wird. Daneben kann die Modifikation der Funktionalität unterschiedliche Auf rischmethoden, unterschiedliche Übertragungsbandbreiten, unterschiedliche Buszyklen und dergleichen betreffen.With regard to the modification of the functionality of a high-volume chip, which can be supplied by an electronic component according to the invention, the present invention is not limited to special modifications. Examples of a modified functionality are, for example, different frequencies with which the interface chip communicates on the one hand with the high-volume chip and on the other hand with the outside world. Furthermore, the special interface chip can be used to implement modified functionality in the sense of a modified memory technology, the high-volume chip, for example, providing the function of a synchronous DRAM memory, while the special interface chip on the outer connections of the multichip housing provides the functionality of a EDO memory is supplied. In addition, the modification of the functionality can relate to different refreshing methods, different transmission bandwidths, different bus cycles and the like.
Die vorliegende Erfindung ermöglicht somit die Verwendung von Hochvolumenchips, die in dem erfindungsgemäßen elektronischen Baustein ihre vorbestimmte Funktionalität beibehalten, zur Realisierung von Spezialbausteinen, beispielsweise für Ni- schenmärkte, die bisher eine Erschließung aufgrund der langwierigen und kostspieligen Entwicklung nicht rechtfertigten. Erfindungsgemäß ist zur Erzeugung derartiger Spezialbausteine ein Schnittstellenchip zusammen mit dem Hochvolumenchip in einem Multichipgehause realisiert, wobei ein solcher Schnittstellenchip mit heutigen Logikentwurfsverfahren in kürzester Zeit kostengünstig implementiert und ferner in einer anderen Technologie als der Hochvolumenchip implementiert werden kann. Dieser Schnittstellenchip liefert die Funktionalität des Spezialbausteins an den äußeren Anschlüssen des Multichipgehauses .The present invention thus enables the use of high-volume chips, which retain their predetermined functionality in the electronic component according to the invention, for realizing special components, for example for niche markets which have so far not justified tapping due to the lengthy and costly development. According to the invention for the production of such special building blocks realizes an interface chip together with the high-volume chip in a multichip housing, such an interface chip can be implemented inexpensively in a very short time using today's logic design methods and can also be implemented in a different technology than the high-volume chip. This interface chip provides the functionality of the special module on the external connections of the multichip housing.
Da bei dem erfindungsgemäßen elektronischen Baustein derSince in the electronic module of the invention
Hochvolumenchip weiterhin nach seiner vorbestimmten Funktionalität arbeitet und der Schnittstellenchip auf das „Ergebnis" der vorbestimmten Funktionalität zurückgreift, um an den äußeren Anschlüssen eines Multichipgehauses eine modifizierte Funktionalität zu liefern, kann durch die vorliegende Erfindung ein Hochvolumenchip, der eine komplizierte und langwierige Produktentwicklung durchlaufen hat, zur Herstellung einer Vielzahl von Spezialbausteinen mit beispielsweise jeweils leicht unterschiedlicher Funktionalität verwendet werden.High-volume chip continues to work according to its predetermined functionality and the interface chip uses the “result” of the predetermined functionality in order to provide modified functionality at the external connections of a multichip housing. The present invention can provide a high-volume chip that has undergone a complicated and lengthy product development. can be used to manufacture a large number of special components, each with slightly different functionality, for example.
Bevorzugte Ausführungsbeispiele der vorliegenden Erfindung werden nachfolgend bezugnehmend auf die beiliegenden Zeichnungen näher erläutert. Es zeigen:Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the accompanying drawings. Show it:
Fig. 1 eine schematische, isometrische Darstellung einesFig. 1 is a schematic, isometric representation of a
Ausführungsbeispiels eines erfindungsgemäßen elektronischen Bausteins; undEmbodiment of an electronic module according to the invention; and
Fig. 2 eine schematische Darstellung zur Erläuterung der vorliegenden Erfindung.Fig. 2 is a schematic representation for explaining the present invention.
Wie in Fig. 1 gezeigt ist, umfaßt ein erfindungsgemäßer e- lektronischer Baustein ein Multichipgehause 10. An dieser Stelle sei angemerkt, daß das Multichipgehause 10 in Fig. 1 „durchsichtig" dargestellt ist, so daß die Darstellung einen Blick auf die relevanten, in dem Multichipgehause 10 angeordneten Komponenten ermöglicht . In dem Multichipgehause 10 sind ein erster Chip 12, der einen Hochvolumenchip darstellt, und ein zweiter Chip 14, der einen Funktionsmodifikationschip bzw. Schnittstellenchip darstellt, angeordnet. Die Chips 12 und 14 können auf eine beliebige Weise unter Verwendung bekannter Techniken in dem Multichipgehause 10 angeordnet und gehaust sein, beispielsweise unter Verwendung einer Trägerplatine oder dergleichen. Bei dem gezeigten Ausführungsbeispiel ist der Schnittstellenchip 14 auf dem Hochvolumenchip 12 montiert, unter Hochvolumenchip wird dabei ein solcher Chip verstanden, dessen Fertigungsstückzahl eine komplizierte und langwierige Entwicklung rechtfertigt.As shown in FIG. 1, an electronic component according to the invention comprises a multi-chip housing 10. At this point it should be noted that the multi-chip housing 10 is shown “transparently” in FIG. 1, so that the illustration shows a view of the relevant ones in FIG the multichip housing 10 arranged components allows. A first chip 12, which represents a high-volume chip, and a second chip 14, which represents a function modification chip or interface chip, are arranged in the multichip housing 10. The chips 12 and 14 may be arranged and packaged in the multi-chip package 10 in any manner using known techniques, for example using a carrier board or the like. In the exemplary embodiment shown, the interface chip 14 is mounted on the high-volume chip 12; high-volume chip is understood to be a chip whose number of production pieces justifies a complicated and lengthy development.
Der Hochvolumenchip 12 umfaßt eine Mehrzahl von Anschlüssen 16 in der Form von Anschlußflächen. Der Schnittstellenchip 14 umfaßt ebenfalls eine Mehrzahl von Anschlüssen 18 in der Form von Anschlußflächen. Bei dem gezeigten Ausführungsbeispiel, das lediglich darstellenden Zwecken dient, sind fünf Anschlüsse 16 über Bonddrähte 20 mit in dem Multichipgehause 10 angeordneten Verbindungsleitungen 22 verbunden. Die Verbindungsleitungen 22 können beispielsweise auf der oben erwähnten Trägerplatine in dem Multichipgehause 10 vorgesehen sein. Drei Anschlüsse des Hochvolumenchips 12 sind bei dem gezeigten Beispiel über Bonddrähte 24 mit Anschlüssen 18 des Schnittstellenchips 14 verbunden. Ferner sind bei dem gezeigten Ausführungsbeispiel zwei Anschlußflächen des Schnittstellenchips 14 über Bonddrähte 25 mit in dem Multichipgehause 10 vorgesehenen Verbindungsleitungen 26, die ebenfalls auf der angesprochenen Trägerplatine vorgesehen sein können, verbun- den. Die inneren Verbindungsleitungen 22 und 26 sind mit äußeren Anschlüssen 28 bzw. 30 des Multichipgehauses verbunden. Die äußeren Anschlüsse 28 und 30 können unter Verwendung üblicher Techniken mit einem Kommunikationsbus (nicht gezeigt) verbunden sein, um eine Kommunikation des erfindungsgemäßen elektronischen Bausteins mit der Umgebung zu ermöglichen. Es ist klar, daß die in Fig. 1 gezeigten, durch Bonddrähte und Verbindungsleitungen bewirkten elektrischen Verbindungen durch andere Kontaktiermethoden ersetzt sein können, beispielsweise Flip-Chip-Kontaktierungen und dergleichen. Ferner ist die Darstellung von Fig. 1 sowohl hinsichtlich der Anzahl von Anschlußflächen und Anschlüssen als auch bezüglich dessen, welche Anschlüsse jeweils miteinander verbunden sind, als rein schematisch anzusehen. Dabei ist festzustellen, daß abhängig von der Funktionalitätsmodifikation, die durch den erfindungsgemäßen Schnittstellenchip 14 geliefert werden soll, bestimmte oder alle Anschlüsse der Chips miteinander und mit den äußeren Anschlüssen verbunden sind, so dass an den äußeren Anschlüssen die modifizierte Funktionalität geliefert wird.The high-volume chip 12 comprises a plurality of connections 16 in the form of connection surfaces. The interface chip 14 also comprises a plurality of connections 18 in the form of connection surfaces. In the exemplary embodiment shown, which is only used for illustrative purposes, five connections 16 are connected via bonding wires 20 to connecting lines 22 arranged in the multichip housing 10. The connecting lines 22 can be provided, for example, on the above-mentioned carrier board in the multichip housing 10. In the example shown, three connections of the high-volume chip 12 are connected to connections 18 of the interface chip 14 via bond wires 24. Furthermore, in the exemplary embodiment shown, two connection surfaces of the interface chip 14 are connected via bonding wires 25 to connecting lines 26 provided in the multichip housing 10, which can also be provided on the carrier board mentioned. The inner connecting lines 22 and 26 are connected to outer connections 28 and 30 of the multichip housing. The outer connections 28 and 30 can be connected to a communication bus (not shown) using conventional techniques in order to enable the electronic component according to the invention to communicate with the surroundings. It is clear that the electrical connections shown in FIG. 1 caused by bonding wires and connecting lines can be replaced by other contacting methods, for example flip-chip contacts and the like. Furthermore, the illustration of FIG. 1 is to be regarded as purely schematic both with regard to the number of connection areas and connections and also with regard to which connections are connected to one another. It should be noted that, depending on the functionality modification that is to be provided by the interface chip 14 according to the invention, some or all of the connections of the chips are connected to one another and to the outer connections, so that the modified functionality is delivered to the outer connections.
An dieser Stelle sei angemerkt, daß es sich bei dem Multichipgehause 10 um ein herkömmliches Standardmultichipgehäuse handeln kann, das sowohl genormte Abmessungen als auch genormte externe Anschlüsse bzw. Anschlussanordnungen aufweisen kann, so daß der erfindungsgemäße elektronische Baustein ohne weiteres in elektronische Schaltungen integrierbar ist.At this point it should be noted that the multichip housing 10 can be a conventional standard multichip housing which can have both standardized dimensions and standardized external connections or connection arrangements, so that the electronic component according to the invention can be easily integrated into electronic circuits.
Wie in Fig. 2 gezeigt ist, weist der Schnittstellenchip 14 somit eine erste Schnittstelle 32 auf, über die er unter Ver- wendung einer geeigneten Koppeleinrichtung 34 mit dem Hochvolumenchip 12 bzw. Anschlüssen desselben gekoppelt ist. Über eine zweite Schnittstelle 36 ist der Schnittstellenchip 14 wiederum über eine geeignete Koppeleinrichtung 38 mit den äußeren Anschlüssen (in Fig. 2 nicht gezeigt) des Multichipge- häuses 10 gekoppelt. Über die äußeren Anschlüsse ist der erfindungsgemäße elektronische Baustein mit einem Kommunikationsbus (nicht gezeigt) und damit einer externen Schaltung 40 bzw. einem Betriebsinterface verbindbar.As shown in FIG. 2, the interface chip 14 thus has a first interface 32, via which it is coupled to the high-volume chip 12 or connections thereof using a suitable coupling device 34. Via a second interface 36, the interface chip 14 is in turn coupled to the external connections (not shown in FIG. 2) of the multichip housing 10 via a suitable coupling device 38. The electronic module according to the invention can be connected to a communication bus (not shown) and thus to an external circuit 40 or an operating interface via the external connections.
Der Hochvolumenchip 12 liefert eine vorbestimmte Funktionalität an seinen Anschlüssen 16. Diese vorbestimmte Funktionali- tat ist bei dem gezeigten Ausführungsbeispiel die eines 128- Mb-DRAM-Speichers .The high-volume chip 12 provides a predetermined functionality at its connections 16. This predetermined functionality tat is that of a 128 Mb DRAM memory in the embodiment shown.
Der Schnittstellenchip 14 liest nun mit einer ersten Fre- quenz, für die der Hochvolumenchip 12 konfiguriert und entwickelt ist, mehrere Bit parallel von den Anschlüssen 16 des DRAM-Speichers. In dem Schnittstellenchip 14 erfolgt dann eine Parallel/Seriell-Wandlung der gelesenen Bits, um einen seriellen Bitstrom zu erzeugen. Dieser serielle Bitstrom kann dann mit einer, verglichen zu der Frequenz, mit der die Bits parallel von den Anschlüssen 16 des Hochvolumenchips gelesen werden, höheren Frequenz zu den externen Anschlüssen des Multichipgehauses und somit einem Kommunikationsbus einer externen Schaltung ausgegeben werden. Dadurch wird durch den Schnittstellenchip 14 eine Modifikation der von dem Hochvolumenchip gelieferten Funktionalität geliefert. Diese Modifikation bezieht sich bei diesem Ausführungsbeispiel auf den Unterschied zwischen der Frequenz, mit der der Schnittstellenchip 14 über die Schnittstelle 32 mit dem Hochvolumenchip 12 kommuniziert, und der Frequenz, mit der der Schnittstellen- chip 14 über die Schnittstelle 36 mit einer externen Schaltung kommuniziert.The interface chip 14 now reads several bits in parallel from the connections 16 of the DRAM memory at a first frequency for which the high-volume chip 12 has been configured and developed. A parallel / serial conversion of the read bits then takes place in the interface chip 14 in order to generate a serial bit stream. This serial bit stream can then be output at a higher frequency compared to the frequency at which the bits are read in parallel from the connections 16 of the high-volume chip to the external connections of the multichip housing and thus to a communication bus of an external circuit. As a result, the interface chip 14 provides a modification of the functionality provided by the high-volume chip. In this exemplary embodiment, this modification relates to the difference between the frequency with which the interface chip 14 communicates with the high-volume chip 12 via the interface 32 and the frequency with which the interface chip 14 communicates with an external circuit via the interface 36.
Neben den oben beschriebenen Beispiel einer Frequenzumwand- lung können durch den erfindungsgemäßen Schnittstellenchip andere Funktionalitätsmodifikationen implementiert werden. Wenn beispielsweise der Hochvolumenchip einen synchronen DRAM-Speicher darstellt, kann der Schnittstellenchip entworfen sein, um an den äußeren Anschlüssen des erfindungsgemäßen elektronischen Bausteins die Funktionalität eines EDO- Speichers zu liefern.In addition to the example of frequency conversion described above, other functionality modifications can be implemented by the interface chip according to the invention. If, for example, the high-volume chip represents a synchronous DRAM memory, the interface chip can be designed in order to provide the functionality of an EDO memory on the external connections of the electronic module according to the invention.
Die in Fig. 2 gezeigte Schnittstelle 32, die zur Kommunikation mit dem Hochvolumenchip 12 dient, kann für verschiedene Anwendungen, d. h. Hochvolumenchipimplementierungen, vorentwickelt werden. Zur Realisierung verschiedener Applikationen, d. h. Funktionalitäten von Spezialbausteinen, muß lediglich noch die jeweilige Applikationsschnittstelle 36, durch die die Modifikation der Funktionalität bewirkt wird, realisiert werden. Vorteilhaft dabei ist, daß der Schnittstellenchip in anderen Technologien implementiert werden kann als der Hoch- volumenchip, d. h. Hochvolumenbaustein, so daß der Schnittstellenchip mit heutigen Logikentwurfsverfahren in kürzester Zeit kostengünstig realisiert werden kann. Durch den Schnittstellenchip sehen externe Schaltungen dann an den externen Anschlüssen nur die durch den Schnittstellenchip modifizierte Funktionalität, so daß an den externen Anschlüssen nur noch die modifizierte Funktionalität zur Verfügung steht. Für externe Schaltungen erscheint der erfindungsgemäße Baustein somit als ein Baustein, der lediglich die modifizierte Funktionalität liefert, wobei auf die eigentliche Funktionalität des ersten Chips nach Häusung in dem Multichip-Gehäuse nicht mehr zugegriffen werden kann. The interface 32 shown in FIG. 2, which is used for communication with the high-volume chip 12, can be pre-developed for various applications, ie high-volume chip implementations. To implement various applications, ie functionalities of special components, all that is required the respective application interface 36 through which the functionality is modified can also be implemented. The advantage here is that the interface chip can be implemented in other technologies than the high-volume chip, ie high-volume module, so that the interface chip can be implemented inexpensively in a very short time using today's logic design methods. Through the interface chip, external circuits then only see the functionality modified by the interface chip at the external connections, so that only the modified functionality is available at the external connections. For external circuits, the module according to the invention thus appears as a module that only supplies the modified functionality, the actual functionality of the first chip after being housed in the multichip housing no longer being accessible.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
10 Multichipgehause10 multichip housing
12 Hochvolumenchip 14 Schnittstellenchip12 high-volume chip 14 interface chip
16 Anschlüsse des Hochvolumenchips16 connections of the high-volume chip
18 Anschlüsse des Schnittstellenchips18 connections of the interface chip
20 Bonddrähte20 bond wires
22 Verbindungsleitungen 24 Bonddrähte22 connecting lines 24 bonding wires
26 Verbindungsleitung26 connecting line
28 äußere Anschlüsse28 external connections
30 äußere Anschlüsse30 external connections
32 erste Schnittstelle 34 Koppeleinrichtung32 first interface 34 coupling device
36 zweite Schnittstelle36 second interface
38 Koppeleinrichtung38 coupling device
40 externe Schaltung 40 external circuit

Claims

Patentansprüche claims
1. Elektronischer Baustein mit folgenden Merkmalen:1. Electronic component with the following features:
einem Multichipgehause (10);a multichip housing (10);
einem ersten, in dem Multichipgehause (10) gehäusten Chip (12), der eine vorbestimmte Funktionalität liefert; unda first chip (12) housed in the multichip housing (10) which provides a predetermined functionality; and
einem zweiten, in dem Multichipgehause (10) gehäusten Chip (14) in Wirkverbindung mit dem ersten Chip (12) und äußeren Anschlüssen (28, 30) des Multichipgehauses (10), wobei der zweite Chip (14) eine Modifikation der von dem ersten Chip (12) gelieferten, vorbestimmten Funktionalität an den äußeren Anschlüssen (28, 30) liefert, so dass an den äußeren Anschlüssen nur die modifizierte Funktionalität zur Verfügung steht.a second chip (14) housed in the multichip housing (10) in operative connection with the first chip (12) and external connections (28, 30) of the multichip housing (10), the second chip (14) being a modification of that of the first The chip (12) delivers predetermined functionality at the outer connections (28, 30), so that only the modified functionality is available at the outer connections.
2. Elektronischer Baustein gemäß Anspruch 1, bei dem der erste Chip (12) ein einer komplizierten und langwierigen Produktentwicklung unterworfener, in Massenfertigung hergestellter Hochvolumenchip ist.2. Electronic module according to claim 1, wherein the first chip (12) is a complex and lengthy product development subject to mass-produced high-volume chip.
3. Elektronischer Baustein gemäß Anspruch 1 oder 2, bei dem der erste Chip (12) ein Speicherbaustein ist.3. Electronic component according to claim 1 or 2, wherein the first chip (12) is a memory component.
4. Elektronischer Baustein gemäß einem der Ansprüche 1 bis 3, bei dem der zweite Chip über eine erste Schnittstelle (32) mit Anschlüssen des ersten Chips (12) gekoppelt ist und über eine zweite Schnittstelle (36) mit zumindest einem Teil der äußeren Anschlüsse (28, 30) des Multichipgehauses (10) gekoppelt ist.4. Electronic component according to one of claims 1 to 3, in which the second chip is coupled via a first interface (32) to connections of the first chip (12) and via a second interface (36) to at least some of the external connections ( 28, 30) of the multichip housing (10) is coupled.
5. Elektronischer Baustein gemäß Anspruch 4, bei dem die vorbestimmte Funktionalität eine erste Frequenz ist, mit der der zweite Chip (14) über die erste Schnittstelle (32) mit dem ersten Chip (12) kommuniziert, und bei dem die modifi- zierte Funktionalität eine zweite Frequenz ist, mit der der zweite Chip (14) über die zweite Schnittstelle (36) mit einer externen Schaltung (40) kommuniziert.5. Electronic module according to claim 4, wherein the predetermined functionality is a first frequency with which the second chip (14) communicates with the first chip (12) via the first interface (32), and in which the modifi- decorated functionality is a second frequency with which the second chip (14) communicates with an external circuit (40) via the second interface (36).
6. Elektronischer Baustein gemäß Anspruch 4, bei dem die vorbestimmte Funktionalität der eines synchronen DRAM- Speichers entspricht und bei dem die modifizierte Funktionalität der eines EDO-Speichers entspricht.6. Electronic component according to claim 4, in which the predetermined functionality corresponds to that of a synchronous DRAM memory and in which the modified functionality corresponds to that of an EDO memory.
7. Elektronischer Baustein gemäß einem der Ansprüche 1 bis 6, bei dem der zweite Chip (14) auf einer anderen Herstellungstechnologie basiert als der erste Chip (12) . 7. Electronic component according to one of claims 1 to 6, wherein the second chip (14) is based on a different manufacturing technology than the first chip (12).
PCT/EP2002/009706 2001-09-20 2002-08-30 Modification of the function of a chip using a multi-chip housing WO2003028102A2 (en)

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