WO2003028087A2 - Manufacturing process of integrated circuits in flip-chip technology - Google Patents

Manufacturing process of integrated circuits in flip-chip technology Download PDF

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Publication number
WO2003028087A2
WO2003028087A2 PCT/IT2002/000389 IT0200389W WO03028087A2 WO 2003028087 A2 WO2003028087 A2 WO 2003028087A2 IT 0200389 W IT0200389 W IT 0200389W WO 03028087 A2 WO03028087 A2 WO 03028087A2
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WO
WIPO (PCT)
Prior art keywords
process according
contact areas
electrical
tracks
anyone
Prior art date
Application number
PCT/IT2002/000389
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French (fr)
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WO2003028087A3 (en
Inventor
Domenico Lo Verde
Giuseppe Sances
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Silena International S.P.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Silena International S.P.A. filed Critical Silena International S.P.A.
Priority to AU2002317478A priority Critical patent/AU2002317478A1/en
Priority to CA002466882A priority patent/CA2466882A1/en
Priority to EP02745789A priority patent/EP1446830A2/en
Publication of WO2003028087A2 publication Critical patent/WO2003028087A2/en
Publication of WO2003028087A3 publication Critical patent/WO2003028087A3/en

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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions

  • the present invention relates to a process for manufacturing integrated circuits in flip-chip technology.
  • Flip-chip technology provides for manufacturing contact elements (“bumps”)/ generally made of a tin/lead alloy or of another conductive metallic material, on the connecting structures (pads) with the specific function of generating projections suitable for connecting welds between the pads of the silicon devices and the bases that house them.
  • the silicon layer is thus mounted upside down, i.e. with the active side bearing on the base that houses it, in such a way that the electrical contacts are directly in contact.
  • the external connector generally, metal wires
  • Bumps are currently generated according to different methodologies that range from the laying of conductive pastes (tin/lead or other materials) in liquid form, to the galvanic plating of the alloy onto the pads of the chip destined to contact (pads) .
  • the same silicon wafer normally comprises multiple devices, and for each device numerous pads are normally provided, in order to treat them galvanically, they must necessarily be mutually connected to form a single conductor.
  • a currently used technology provides for the connection between the pads of a same device to be effected through the laying of a whole layer of conductive material which achieves the electrical contact between the pads and of a subsequent masking of the areas not involved in the galvanic plating.
  • the masking layer and the underlying conductive layer are removed (normally with a chemical method) .
  • the aim of the present invention is to solve the aforesaid problems, providing a process for manufacturing integrated circuits, in particular of the "flip-chip" type presenting contact elements realised on predetermined contact areas, characterised in that it comprises the following steps:
  • the main advantage of the method according to the present invention is given by the fact that it allows to effect the galvanic plating of the bumps with no need to provide the additional layers of the prior art, achieving an electrical contact between the pads in innovative fashion.
  • figures 1A to ID are section views of a flip-chip device that show a prior art method of galvanic plating of the bumps ;
  • figures 2A to 2F are section views of a flip-chip device that show the method according to the present invention;
  • figure 3 is a top view of a flip-chip device according to a first embodiment of the present invention;
  • figure 4 is a top view of a flip-chip device according to a second embodiment of the present invention;
  • figure 5A is a partial section view of the device of figure 4 before the cut;
  • figure 5B is a partial section view of the device of figure 4 after the cut;
  • figures 6A and 6B are partial section views of a flip-chip device according to a third embodiment of the present invention.
  • Figures 1A to ID show one of the prior art methods currently used to manufacture an integrated circuit 1 in flip-chip technology by means of galvanic plating of the contact elements (bumps) .
  • the silicon layer 2 comprising the active devices, are realised a multiplicity of pads 3 to effect the external connections of such devices.
  • a conductive layer 8 is laid on the whole flip-chip. The layer 8, in correspondence with the uncovered parts 7, is in electrical contact with the area of the pads 5. Subsequently a masking layer 9 is obtained, to define regions 10, within which contact elements 11 (bumps) are to be laid.
  • the conductive layer 8 is used as a cathodic electrode in the subsequent galvanic plating phase of the contact elements 11. Lastly, by prior art technologies, the masking 9 and the underlying portions of conductive layer 8 not involved with the galvanic plating process are removed.
  • Figure ID shows the final product of the described method.
  • the subsequent figures 2A to 2F illustrate the method for manuf cturing a flip-chip 21 according to the present invention.
  • a first step of the method according to the present invention provides for readying electrical connections 30 in such a way as mutually to connect all the contact areas (pads) 23 provided on the integrated circuit 21, obtaining a single electrical body.
  • connections are obtained, in the form of electrical connecting tracks 30, during the construction of the circuit through diffusion processes, for instance during the photolithographic aluminium metallisation process used to manufacture the pads 23 themselves .
  • the tracks 30, preferably made of aluminium, shall be so dimensioned as to allow the flow of an anodic plating current during a subsequent galvanisation step.
  • a passivation layer 24 of insulating material shall be laid, over the electrical body constituting by the pads 23 and by the tracks 30.
  • Said passivation layer 24 is preferably made of silicon dioxide (Si0 2 ) or of other generic passivating materials such as nitrides or epoxy resins in order to protect and electrically insulate the metallic parts of the chip and to prevent, in subsequent galvanic growth phases, the alloy used from growing on the connecting tracks of the circuit components.
  • the insulating material of the passivation layer 24, will then be eliminated in correspondence with the contact areas, for instance through a photo-technical process that will not be described herein because it is well known to a person skilled in the art.
  • a subsequent step of the method provides the galvanic growth of an interfacing layer 25 on the uncovered portions of the pads 23.
  • Such layer 25 is made of metallic material, for instance gold, nickel, silver or others, and it substantially has the function of favouring the electrical contact between the aluminium of the pads 23 and the overlying contact elements 31.
  • the plating of the bumps 31 is executed with a traditional galvanic plating technique in which the electric of the wafer will be connected to the cathode of the galvanic tanks, thereby allowing the growth of the bumps 31 in the area of the pads 24 electrically in contact with the galvanic solution.
  • the alloy used for manufacturing the bumps is Sn/Pb in the respective percentages of 90% and 10%, however it is readily understood that other metals and/or alloys can be used effectively, provided their characteristics are suitable for being galvanically plated .
  • a phase of melting the Sn/Pb deposits can be executed at a temperature of about 300 °C, to cause the deposited bumps assume a spherical profile.
  • An additional step of the method is that of interrupting the electrical connections 30 between the contact areas 23, to allow the correct operation of the active devices comprising the integrated circuit.
  • This step of interrupting the connecting track 30 is executed through the so-called ⁇ fuse technique' which consists of letting an electrical melting current If, having such intensity as to cause the melting of the corresponding tracks 30, flow through the tracks themselves .
  • a voltage generator generates a voltage V f whose value preferably ranging between 0. IV and 0.68V, in such a way as to be in any case below the threshold voltage of the semiconductor junctions comprising the active devices of the integrated circuits. In this way it is possible to assure that the applied voltage does not damage the integrated circuit in any way at all .
  • the voltage V f applied between two consecutive bumps, will cause the flow of a melting current I f which, thanks to a correct dimensioning of the tracks 30, is greater than the current that the track itself can withstand before reaching the melting temperature and hence being interrupted, thereby electrically insulating the two corresponding pads .
  • the melting current I anyway has a modest value of intensity, in the order of 10*10 "3 A. A current of such intensity is sufficient to melt the tracks 30 that short circuit the pads without, however, risking to damage the devices present on the chip.
  • the subsequent figure 3 is a top view of a flip-chip device in the realisation phase by means of a method according to the present invention, which shows the procedure for manufacturing the electrical connection tracks between the pads according to a first embodiment of the invention.
  • connections between the pads may be achieved according to different paths from the one shown in the figure, without thereby altering the inventive concept constituting the basis for the method according to the present invention.
  • the subsequent figure 4 is a top view of a flip-chip device according to a second embodiment of the present invention.
  • the electrical contact tracks between the pads are realised according to a different disposition.
  • each pad of each of the devices present on the wafer to be processed is electrically connected by means of an electrical track with a corresponding pad of an adjacent device.
  • the electrical tracks thus formed contact the cutting lines L t of the wafer, which are also conductive.
  • a single electric body is defined, substantially composed by the set of all pads present on the wafer, electrically connected to each other through tracks 30 that are in electrical contact with conductors 29 present along the cutting lines L t , in such a way as to obtain a single electric body.
  • the method as described heretofore is naturally still applicable, i.e. using a melting current to interrupt the electrical connections between the pads after the galvanic plating of the bumps . Therefore this technology, already amply described above, will not be described in detail again hereafter.
  • a disposition of the type seen above is particularly advantageous because it allows to achieve the interruption of the electrical connections between the pads, simultaneously with the cutting of the wafer to obtain the individual devices .
  • the disposition of the electrical tracks is such that they are all astride corresponding cutting lines L t , provided between the various devices present on the wafer.
  • the connecting tracks 30 are automatically interrupted, leaving the individual pads insulated.
  • the connecting tracks and/or the wafer can be cut by means of a laser device.
  • Figures 5A and 5B are section views of a portion of the wafer of figure 4, which show how the connecting track 30 between the pads 23 is interrupted along the cutting line L .
  • figure 5A is a section view taken along the line A-A of figure 4, which shows the realisation of the area around the cutting line L t , with the conducting portion 29 and a connecting electrical track 30 between the pads that is at the same time in contact with the conductor 29.
  • Figure 5B is a section view of the same area of figure 5A, after the cutting operation conducted along the cutting line L t , which interrupts the electrical connections 30 between the pads.
  • the subsequent figures 6A and 6B refer to a third embodiment of the present invention.
  • FIG 6A shows a section view of an embodiment of a portion of integrated circuit.
  • semiconductor devices 41, 42 are present for protecting the integrated circuit against any electrostatic charges that may reach the active devices through the pads 23.
  • This characteristic can advantageously be exploited to provide electrical connections between all the pads of the device, towards a common ground constituted by the substrate of the device, during the galvanic plating of the bumps .
  • the device to be treated is connected to a current generator G.
  • One of the poles of the generator shall be connected to the substrate of the device, while the other one shall be in contact with all the pads 23 through the solution in the galvanisation tank.
  • the polarity of the generator and hence the direction of the current will be selected in such a way that the protection diodes are inversely polarised.
  • the voltage at the ends of the current generator G will increase until it exceeds the avalanche breakdown threshold of the diodes, which will thus start to conduct .
  • the current generator is disconnected from the device and the current Id stops flowing therein.
  • the junctions that constitute the protection diodes will naturally return to their normal cut-off state, without having been harmed in any way, and hence interrupting the electrical connections that had temporarily been realised between the pads during the galvanic plating phase.

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Abstract

A process for manufacturing integrated circuits in flip-chip technology having contact elements (31) realised on predetermined contact areas (23), comprises the steps of readying electrical connections (30) in such a way as mutually to connect all the contact areas (23) of said integrated circuit (21), galvanically depositing a contact element (31) in correspondence with each of said contact areas (23) and interrupting said electrical connections (30) between the contact areas (23).

Description

1VLANUFACTURING PROCESS OF INTEGRATED CIRCUITS IN FLIP-CHIP
TECHNOLOGY DESCRIPTION The present invention relates to a process for manufacturing integrated circuits in flip-chip technology.
Flip-chip technology provides for manufacturing contact elements ("bumps")/ generally made of a tin/lead alloy or of another conductive metallic material, on the connecting structures (pads) with the specific function of generating projections suitable for connecting welds between the pads of the silicon devices and the bases that house them.
In flip-chip technology, the silicon layer is thus mounted upside down, i.e. with the active side bearing on the base that houses it, in such a way that the electrical contacts are directly in contact. In this way, all need for physical connection between the chip and the external connector (generally, metal wires) disappears, making the whole set more economical and less subject to breakage and/or failures.
Bumps are currently generated according to different methodologies that range from the laying of conductive pastes (tin/lead or other materials) in liquid form, to the galvanic plating of the alloy onto the pads of the chip destined to contact (pads) .
Since the same silicon wafer normally comprises multiple devices, and for each device numerous pads are normally provided, in order to treat them galvanically, they must necessarily be mutually connected to form a single conductor.
Different techniques are known, used to obtain said connection that anyway will subsequently have to be removed once the galvanic treatment is complete. A currently used technology provides for the connection between the pads of a same device to be effected through the laying of a whole layer of conductive material which achieves the electrical contact between the pads and of a subsequent masking of the areas not involved in the galvanic plating.
After galvanically treating the device, the masking layer and the underlying conductive layer are removed (normally with a chemical method) .
However, this technology has many important disadvantages, foremost among them that of requiring the laying of an additional passivation layer, of a conductive layer, the making of a masking layer and additionally an operation of removing the superfluous layers at the end of the galvanic treatment.
All these operations make the entire process of manufacturing the integrated circuit longer and more complex, increasing its costs as well.
The aim of the present invention is to solve the aforesaid problems, providing a process for manufacturing integrated circuits, in particular of the "flip-chip" type presenting contact elements realised on predetermined contact areas, characterised in that it comprises the following steps:
- readying electrical connections in such a way as mutually to connect all the contact areas of said integrated circuit, obtaining a single electric body; - laying a passivation layer made of insulating material over said electric body;
- eliminating said insulating material in correspondence with said contact areas;
- simultaneously galvanically laying a contact element in correspondence with each of said contact areas; and
- interrupting said electrical connections between the contact areas .
The main advantage of the method according to the present invention is given by the fact that it allows to effect the galvanic plating of the bumps with no need to provide the additional layers of the prior art, achieving an electrical contact between the pads in innovative fashion.
Consequently, an extremely simple, fast and economical flip-chip manufacturing method is obtained, maintaining all the advantages given by the method of galvanically laying the bumps.
Additional advantages, characteristics and employment modes of the present invention shall become more readily apparent from the following detailed description of preferred embodiments thereof, provided by way of example and not with limitative purposes, with reference to the figures of the accompanying drawings, in which: figures 1A to ID are section views of a flip-chip device that show a prior art method of galvanic plating of the bumps ; figures 2A to 2F are section views of a flip-chip device that show the method according to the present invention; figure 3 is a top view of a flip-chip device according to a first embodiment of the present invention; figure 4 is a top view of a flip-chip device according to a second embodiment of the present invention; figure 5A is a partial section view of the device of figure 4 before the cut; figure 5B is a partial section view of the device of figure 4 after the cut; and figures 6A and 6B are partial section views of a flip-chip device according to a third embodiment of the present invention.
Figures 1A to ID show one of the prior art methods currently used to manufacture an integrated circuit 1 in flip-chip technology by means of galvanic plating of the contact elements (bumps) . In particular on the silicon layer 2 comprising the active devices, are realised a multiplicity of pads 3 to effect the external connections of such devices. A conductive layer 8 is laid on the whole flip-chip. The layer 8, in correspondence with the uncovered parts 7, is in electrical contact with the area of the pads 5. Subsequently a masking layer 9 is obtained, to define regions 10, within which contact elements 11 (bumps) are to be laid.
The conductive layer 8 is used as a cathodic electrode in the subsequent galvanic plating phase of the contact elements 11. Lastly, by prior art technologies, the masking 9 and the underlying portions of conductive layer 8 not involved with the galvanic plating process are removed.
Figure ID shows the final product of the described method. The subsequent figures 2A to 2F illustrate the method for manuf cturing a flip-chip 21 according to the present invention.
A first step of the method according to the present invention provides for readying electrical connections 30 in such a way as mutually to connect all the contact areas (pads) 23 provided on the integrated circuit 21, obtaining a single electrical body.
In particular, said connections are obtained, in the form of electrical connecting tracks 30, during the construction of the circuit through diffusion processes, for instance during the photolithographic aluminium metallisation process used to manufacture the pads 23 themselves .
The tracks 30, preferably made of aluminium, shall be so dimensioned as to allow the flow of an anodic plating current during a subsequent galvanisation step.
In a subsequent step of the method, a passivation layer 24 of insulating material shall be laid, over the electrical body constituting by the pads 23 and by the tracks 30.
Said passivation layer 24 is preferably made of silicon dioxide (Si02) or of other generic passivating materials such as nitrides or epoxy resins in order to protect and electrically insulate the metallic parts of the chip and to prevent, in subsequent galvanic growth phases, the alloy used from growing on the connecting tracks of the circuit components.
The insulating material of the passivation layer 24, will then be eliminated in correspondence with the contact areas, for instance through a photo-technical process that will not be described herein because it is well known to a person skilled in the art.
In this way will remain uncovered only the metallic areas in correspondence with the pads whereon the contact elements 31 (bumps) are to be grown.
A subsequent step of the method provides the galvanic growth of an interfacing layer 25 on the uncovered portions of the pads 23.
Such layer 25 is made of metallic material, for instance gold, nickel, silver or others, and it substantially has the function of favouring the electrical contact between the aluminium of the pads 23 and the overlying contact elements 31.
The plating of the bumps 31 is executed with a traditional galvanic plating technique in which the electric of the wafer will be connected to the cathode of the galvanic tanks, thereby allowing the growth of the bumps 31 in the area of the pads 24 electrically in contact with the galvanic solution.
Preferably, the alloy used for manufacturing the bumps is Sn/Pb in the respective percentages of 90% and 10%, however it is readily understood that other metals and/or alloys can be used effectively, provided their characteristics are suitable for being galvanically plated .
Advantageously, after the plating, a phase of melting the Sn/Pb deposits can be executed at a temperature of about 300 °C, to cause the deposited bumps assume a spherical profile. An additional step of the method is that of interrupting the electrical connections 30 between the contact areas 23, to allow the correct operation of the active devices comprising the integrated circuit. This step of interrupting the connecting track 30 is executed through the so-called Λ fuse technique' which consists of letting an electrical melting current If, having such intensity as to cause the melting of the corresponding tracks 30, flow through the tracks themselves .
In particular, a voltage generator generates a voltage Vf whose value preferably ranging between 0. IV and 0.68V, in such a way as to be in any case below the threshold voltage of the semiconductor junctions comprising the active devices of the integrated circuits. In this way it is possible to assure that the applied voltage does not damage the integrated circuit in any way at all .
The voltage Vf, applied between two consecutive bumps, will cause the flow of a melting current If which, thanks to a correct dimensioning of the tracks 30, is greater than the current that the track itself can withstand before reaching the melting temperature and hence being interrupted, thereby electrically insulating the two corresponding pads .
The melting current I anyway has a modest value of intensity, in the order of 10*10"3 A. A current of such intensity is sufficient to melt the tracks 30 that short circuit the pads without, however, risking to damage the devices present on the chip.
Naturally, this procedure will have to be repeated for each pair of pads electrically connected to each other by means of a track.
The subsequent figure 3 is a top view of a flip-chip device in the realisation phase by means of a method according to the present invention, which shows the procedure for manufacturing the electrical connection tracks between the pads according to a first embodiment of the invention.
It is understood that the connections between the pads may be achieved according to different paths from the one shown in the figure, without thereby altering the inventive concept constituting the basis for the method according to the present invention.
An additional considerable advantage of the proposed technological solution relative to the traditional technique described above, is given by the fact that it provides the capability of generating bumps whose dimensions are considerably smaller than those of the standard flip-chip technology with consequent recovery of active area on the chip itself and reduction of the dimensions of the final integrated circuit .
Through the proposed process, it is possible to obtain bumps even below 20μm allowing an ever greater miniaturisation of the components, which is currently a highly interesting aspect . The subsequent figure 4 is a top view of a flip-chip device according to a second embodiment of the present invention.
In particular, according to this second embodiment, the electrical contact tracks between the pads are realised according to a different disposition.
In this case each pad of each of the devices present on the wafer to be processed is electrically connected by means of an electrical track with a corresponding pad of an adjacent device. The electrical tracks thus formed, contact the cutting lines Lt of the wafer, which are also conductive. In this way a single electric body is defined, substantially composed by the set of all pads present on the wafer, electrically connected to each other through tracks 30 that are in electrical contact with conductors 29 present along the cutting lines Lt, in such a way as to obtain a single electric body. For a wafer realised with such a disposition of electrical connections, the method as described heretofore is naturally still applicable, i.e. using a melting current to interrupt the electrical connections between the pads after the galvanic plating of the bumps . Therefore this technology, already amply described above, will not be described in detail again hereafter.
However, a disposition of the type seen above is particularly advantageous because it allows to achieve the interruption of the electrical connections between the pads, simultaneously with the cutting of the wafer to obtain the individual devices .
It should be noted that the disposition of the electrical tracks is such that they are all astride corresponding cutting lines Lt, provided between the various devices present on the wafer.
Consequently, at the moment of the cut, which can occur for instance through the use of a mechanical cutting device which can be a diamond-coated blade, the connecting tracks 30 are automatically interrupted, leaving the individual pads insulated.
Alternatively, the connecting tracks and/or the wafer can be cut by means of a laser device.
Figures 5A and 5B are section views of a portion of the wafer of figure 4, which show how the connecting track 30 between the pads 23 is interrupted along the cutting line L .
In particular, the figure 5A is a section view taken along the line A-A of figure 4, which shows the realisation of the area around the cutting line Lt, with the conducting portion 29 and a connecting electrical track 30 between the pads that is at the same time in contact with the conductor 29.
Figure 5B is a section view of the same area of figure 5A, after the cutting operation conducted along the cutting line Lt, which interrupts the electrical connections 30 between the pads. The subsequent figures 6A and 6B refer to a third embodiment of the present invention.
In particular, the figure 6A shows a section view of an embodiment of a portion of integrated circuit. In this embodiment, semiconductor devices 41, 42 are present for protecting the integrated circuit against any electrostatic charges that may reach the active devices through the pads 23.
For this purpose, most of the integrated circuits is realised in such a way that, in correspondence with each pad, a diode is formed, constituted by a junction of the N+/P or P+/N type which in normal operation is cut off.
This characteristic can advantageously be exploited to provide electrical connections between all the pads of the device, towards a common ground constituted by the substrate of the device, during the galvanic plating of the bumps .
To execute said plating operation, the device to be treated is connected to a current generator G. One of the poles of the generator shall be connected to the substrate of the device, while the other one shall be in contact with all the pads 23 through the solution in the galvanisation tank.
The polarity of the generator and hence the direction of the current will be selected in such a way that the protection diodes are inversely polarised.
For a current Id to be able to flow in the device, the voltage at the ends of the current generator G will increase until it exceeds the avalanche breakdown threshold of the diodes, which will thus start to conduct .
Once the galvanic plating phase is complete, the current generator is disconnected from the device and the current Id stops flowing therein. At the same time the junctions that constitute the protection diodes will naturally return to their normal cut-off state, without having been harmed in any way, and hence interrupting the electrical connections that had temporarily been realised between the pads during the galvanic plating phase.
This latter embodiment is naturally particularly advantageous from a point of view of economics and of its simplicity of application, since it is not necessary physically to realise additional electrical connections between the pads other than those already provided through the protection junctions. The present invention has been heretofore described according to preferred embodiments thereof, presented purely by way of non limiting example.
It is understood that there may be other embodiments, all falling within the scope of protection of the invention, as defined in the accompanying claims.

Claims

CLAIMS 1. Process for manufacturing integrated circuits (21) , in particular of the "flip-chip" type presenting contact elements (31) realised on predetermined contact areas (23) , characterised in that it comprises the following steps :
- readying electrical connections (30; 41, 42, 43) in such a way as mutually to connect all the contact areas (23) of said integrated circuit (21) , obtaining a single electric body;
- laying a passivation layer (24) made of insulating material over said electric body;
- eliminating said insulating material in correspondence with said contact areas (23) ; - simultaneously laying galvanically a contact element (31) in correspondence with each of said contact areas (23) ; and
- interrupting said electrical connections (30; 41, 42) between the contact areas (23) .
2. Process according to claim 1, wherein said electrical connections are realised in the form of electrical tracks (30) able to allow an electrical plating current to flow, each track (30) being able to connect two contact areas (23) .
3. Process according to claim 2, wherein said step of interrupting said connections (30) is carried out by means of a device for mechanically cutting said tracks along cutting lines (Lt) .
4. Process according to claim 3, wherein said mechanical cutting device is a diamond coated blade.
5. Process according to claim 2, wherein said step of interrupting said connections (30) is carried out by means of a laser device able to cut said tracks (30) .
6. Process according to claim 2, wherein said step of interrupting said connections is carried out making an electrical melting current (If) flow through each of said tracks (30) , said current (If) having such an intensity as to cause the melting of the electrical tracks through which it flows .
7. Process according to claim 6, wherein said electrical melting current (If) is generated applying a voltage (Vf) between two contact areas (23) connected by an electrical track (30) .
8. Process according to claim 7, wherein said voltage (Vf) has a value of 0. IV to 0.68V.
9. Process according to claim 1, wherein said electrical connections are realised in the form of semiconductor devices (41, 42) positioned in such a way as to electrically connect said contact areas (23) with a conductive substrate (43) .
10. Process according to claim 9, wherein each of said semiconductor devices comprises at least a junction of the N+/P or P+/N type able to realise a diode, normally cut off, for the protection of the integrated circuit against electrostatic discharges.
11. Process according to claim 10, wherein said step of galvanically laying said contact elements (31) comprises a step of letting an electrical plating current (Id) flow through said electric body, said current (Id) being able to inversely polarise said protection diodes in their avalanche breakdown region.
12. Process according to claim 11, wherein said step of interrupting said electrical connections (41, 42) between the contact areas (23) is performed interrupting said plating current (Id) , in such a way as to return said diode to their normal operating condition.
13. Process according to anyone of the preceding claims, further comprising a step of laying an interfacing layer (25) made of metallic material on said contact areas (23) .
14. Process according to claim 13, wherein said interfacing layer (25) is galvanically laid.
15. Process according to anyone of the preceding claims, wherein said contact elements (31) are made of an alloy of Sn/Pb.
16. Process according to anyone of the preceding claims, wherein said connecting tracks (30) are made of aluminium.
17. Process according to anyone of the preceding claims, wherein said insulating material of said passivation layer (24) is a silicon dioxide (Si02) .
18. Process according to anyone of the claims 1 to
16, wherein said insulating material of said passivation layer (24) is a nitride.
19. Process according to anyone of the claims 1 to 16, wherein said insulating material of said passivation layer (24) is an epoxy resin.
20. Process according to anyone of the preceding claims, wherein said step of eliminating said insulating material in correspondence with said contact areas (23) is effected by a photo-technical process.
PCT/IT2002/000389 2001-09-27 2002-06-13 Manufacturing process of integrated circuits in flip-chip technology WO2003028087A2 (en)

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IT2001RM000585A ITRM20010585A1 (en) 2001-09-27 2001-09-27 PROCEDURE FOR THE CREATION OF INTEGRATED CIRCUITS IN FLIP-CHIP TECHNOLOGY.

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Citations (2)

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Publication number Priority date Publication date Assignee Title
US3760238A (en) * 1972-02-28 1973-09-18 Microsystems Int Ltd Fabrication of beam leads
US4134801A (en) * 1976-05-17 1979-01-16 U.S. Philips Corporation Terminal connections on microcircuit chips

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JP2949072B2 (en) * 1996-03-26 1999-09-13 進工業株式会社 Manufacturing method of ball grid array type parts
JP3119352B2 (en) * 1998-04-15 2000-12-18 日本電気株式会社 Method for forming plated structure of semiconductor device

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Publication number Priority date Publication date Assignee Title
US3760238A (en) * 1972-02-28 1973-09-18 Microsystems Int Ltd Fabrication of beam leads
US4134801A (en) * 1976-05-17 1979-01-16 U.S. Philips Corporation Terminal connections on microcircuit chips

Non-Patent Citations (2)

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Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 02, 30 January 1998 (1998-01-30) -& JP 09 260531 A (SUSUMU KOGYO KK), 3 October 1997 (1997-10-03) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 01, 31 January 2000 (2000-01-31) -& JP 11 297737 A (NEC CORP), 29 October 1999 (1999-10-29) *

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WO2003028087A3 (en) 2004-03-25

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