CN113644040B - Package structure and method for forming the same - Google Patents

Package structure and method for forming the same Download PDF

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Publication number
CN113644040B
CN113644040B CN202010346530.7A CN202010346530A CN113644040B CN 113644040 B CN113644040 B CN 113644040B CN 202010346530 A CN202010346530 A CN 202010346530A CN 113644040 B CN113644040 B CN 113644040B
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China
Prior art keywords
substrate
layer
conductive bump
forming
under bump
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CN202010346530.7A
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Chinese (zh)
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CN113644040A (en
Inventor
熊鹏
肖代兵
王瑜彬
李斌
施维
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010346530.7A priority Critical patent/CN113644040B/en
Publication of CN113644040A publication Critical patent/CN113644040A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03914—Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]

Abstract

The embodiment of the invention provides a packaging structure and a forming method thereof, wherein the packaging structure comprises: the substrate comprises an interlayer dielectric layer; a bonding pad positioned on the surface of the substrate; an under bump metal layer on the bonding pad; the conductive bump is positioned on the under bump metal layer, and the extension line of the conductive bump along the extension direction of the conductive bump is projected on the central point of the substrate, which is projected on the surface of the substrate, so that the area of the area where the conductive bump bears stress is maximized, the pressure of the area when the conductive bump is stressed is reduced, the interlayer dielectric layer in the substrate is prevented from being broken or stripped, the maximum stress which can be borne by the packaging structure is improved, and the reliability of the packaging structure is further improved.

Description

Package structure and method for forming the same
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a package structure and a method for forming the same.
Background
In forming semiconductor devices, electrical connection between the semiconductor devices needs to be achieved through metal interconnect structures. With the continuous progress of semiconductor integrated circuit technology, as semiconductor devices shrink to deep submicron ranges, the density of metal interconnect structures between semiconductor devices is also increasing. Parasitic resistance and parasitic capacitance are easily generated between high-density metal interconnection structures, so that parasitic effects occur, and time delay of signal transmission between devices is caused.
To overcome the parasitic effects of metal interconnect structures, an interlayer dielectric layer having an Ultra-low dielectric constant (ULK) is typically formed between the metal interconnect structures. Among them, the typical ultra-low dielectric constant material used to form the interlayer dielectric layer is a porous material (such as porous silicon oxide), and since the pores in the material have a dielectric constant as low as 1, the dielectric constant of the porous material as a whole is lower than that of the substrate.
However, the reliability of the package structure formed by the existing semiconductor device is to be improved.
Disclosure of Invention
The invention solves the problem of providing a packaging structure and a forming method thereof, so as to improve the performance of a packaged device.
In order to solve the above problems, the present invention provides a package structure, comprising:
the substrate comprises an interlayer dielectric layer;
a bonding pad positioned on the surface of the substrate;
an under bump metal layer on the bonding pad;
and the conductive bump is positioned on the under bump metal layer, and an extension line of the conductive bump along the extension direction of the conductive bump is arranged at the center point of the substrate projected through the surface of the substrate.
Correspondingly, the invention also provides a forming method of the packaging structure, which comprises the following steps:
providing a substrate, wherein the substrate comprises an interlayer dielectric layer;
forming a welding pad on the surface of the substrate;
and forming an under bump metal layer positioned on the welding pad and a conductive bump positioned on the under bump metal layer, wherein an extension line of the conductive bump along the extension direction of the conductive bump is projected on a central point of the substrate, which is projected through the substrate.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in an embodiment of the present invention, a package structure and a forming method thereof are provided, where the package structure includes: the substrate comprises an interlayer dielectric layer; a plurality of bonding pads positioned on the surface of the substrate; an under bump metal layer on the bonding pad; the conductive bump is positioned on the under bump metal layer, and the extension line of the conductive bump along the extension direction of the conductive bump is projected on the central point of the substrate, which is projected on the surface of the substrate, so that the area of the area where the conductive bump bears stress is maximized, the pressure of the area when the conductive bump is stressed is reduced, the interlayer dielectric layer in the substrate is prevented from being broken or stripped, the maximum stress which can be borne by the packaging structure is improved, and the reliability of the packaging structure is further improved.
Drawings
Fig. 1 to 2 are schematic structural views of a package structure;
fig. 3 to 5 are schematic structural views of a package structure according to an embodiment of the invention;
FIG. 6 is a schematic view of a conductive bump projected onto the substrate in an alternative embodiment of the invention;
fig. 7 to 11 are schematic structural views corresponding to each step in a method for forming a package structure according to an embodiment of the present invention;
fig. 12 to 16 are schematic structural views corresponding to steps in another method for forming a package structure according to an embodiment of the present invention.
Detailed Description
As known from the background art, the reliability of the package structure formed by the existing semiconductor device needs to be improved.
The inventors have found that, to overcome the parasitic effect of the metal interconnect structures, an interlayer dielectric layer having an Ultra-low dielectric constant (ULK) is generally formed between the metal interconnect structures, and such an interlayer dielectric layer is easily broken or peeled off when an external stress is encountered. Particularly, when a typical porous material with ultralow dielectric constant is adopted, since the interlayer dielectric layer is a porous material with ultralow dielectric constant (hereinafter referred to as ULK material), the ULK material is easily broken or peeled off when external stress is encountered, or even when external stress is not present, due to different expansion coefficients of different materials in the package structure, the temperature change in the external environment can cause the ULK material to bear certain tensile stress and compressive stress, so that the ULK material is broken or even peeled off under the stress.
Further, the inventors performed stress analysis on a package structure provided with ULK material, specifically as follows:
referring to fig. 1, there is shown a schematic diagram of a package structure, the package structure including: a base 1 formed with an interlayer dielectric layer and a package substrate 3 electrically contacted with the base 1, wherein the package substrate is electrically contacted with the base through a conductive bump 2 on the base.
In the package structure, the conductive bump is used as a connection structure between the package substrate and the substrate, and bears stress conduction between the package substrate and the substrate, referring to a layout schematic diagram of the conductive bump on the substrate shown in fig. 2, the inventor further studies that, based on a regular shape of a conventional substrate, stress borne by the conductive bump 2, whether tension or compression, is converted into a force directed to a center point O of a plane of the substrate, so that the stress borne by the conductive bump 2 is concentrated in a specific area of the substrate, that is, an area (such as an area outlined by a dotted line) where a straight line passing through the center point O of the plane of the substrate and the center point O' of the conductive bump 2 projected on the substrate intersects with the projection of the conductive bump 2 on the substrate.
In the prior art, the extending direction of the conductive bump 2 is generally disordered, so that the area of a specific area of some conductive bumps bearing stress is too small, and the pressure of the area is too high, so that the interlayer dielectric layer corresponding to the area is easy to break or peel.
Based on this, in an embodiment of the present invention, there is provided a package structure and a method of forming the same, the package structure including: the substrate comprises an interlayer dielectric layer; a bonding pad positioned on the surface of the substrate; an under bump metal layer on the bonding pad; the conductive bump is positioned on the under bump metal layer, and the extension line of the conductive bump along the extension direction of the conductive bump is projected on the central point of the substrate, which is projected on the surface of the substrate, so that the area of the area where the conductive bump bears stress is maximized, the pressure of the area when the conductive bump is stressed is reduced, the interlayer dielectric layer in the substrate is prevented from being broken or stripped, the maximum stress which can be borne by the packaging structure is improved, and the reliability of the packaging structure is further improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 3 to 5, wherein fig. 4 is a schematic diagram illustrating a structure of an area within a dashed frame in fig. 3, fig. 5 is a schematic diagram illustrating a layout of conductive bumps in the package structure in a top view, and referring to fig. 3 to 4, the package structure includes a substrate 150, and the substrate 150 includes an interlayer dielectric layer 120; a bonding pad 102 located on the surface of the substrate; an under bump metallization layer 103 on the bond pad; and the conductive bump 104 is positioned on the under bump metal layer, and an extension line of the conductive bump 104 along the extension direction of the conductive bump is at a center point O of the substrate projected through the surface of the substrate.
The base may include a substrate 100, an active device 110, and an interlayer dielectric layer 120 covering the active device 110, and a metal interconnect structure 130 within the interlayer dielectric layer 120. In the embodiment of the present invention, the substrate is in a regular shape, such as a square shape, a round shape, etc., and this embodiment is illustrated by taking a square shape as an example.
The substrate 100 may be a semiconductor substrate such as silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like. Alternatively, the substrate 100 can be a silicon substrate on an insulator or a germanium substrate on an insulator, which can be selected by those skilled in the art according to practical requirements. The active device 110 is a semiconductor device disposed on a surface of a substrate, and may be specifically a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse, or the like, and is formed on the surface of the substrate through a corresponding semiconductor process. The interlayer dielectric layer 120 is disposed on the side of the substrate 100 where the active device 110 is disposed, and covers the active device 110. The metal interconnect structure 130 is disposed within the interlayer dielectric layer 120 for electrically connecting the active devices 110. The metal interconnect structure 130 may be a conductive member (e.g., conductive line and via of copper, aluminum, tungsten, etc.) disposed in an interlayer dielectric layer 120 (ILD), and electrically connects the active devices 110 to form a functional circuit in the substrate.
In the embodiment of the present invention, the material of the interlayer dielectric layer 120 is an ultralow dielectric constant material, and the ultralow dielectric constant material may be a material with a dielectric constant less than 2.6. Specifically, the interlayer dielectric layer 120 may be a porous material, such as porous silicon oxide. It should be noted that, due to the pore structure of the porous material, the brittleness of the material is high, so that the material is easy to fracture.
A plurality of pads 102 are disposed on the surface of the substrate, and in particular, the pads 102 are disposed on the metal interconnect structure 130 for electrically connecting the active devices 110 through the metal interconnect structure 130 in the substrate.
The pad 102 may be a metal material such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), or an alloy material of a plurality of metal materials, and may have a single-layer structure or a stacked structure of a plurality of layers.
In this embodiment of the present invention, a patterned passivation layer 101 is further disposed on the substrate, where the passivation layer 101 is used for protecting the substrate, and a plurality of openings are formed to expose a partial area of the bonding pad 102, so that the under bump metal layer 103 may cover the opening to cover the exposed bonding pad 102, and achieve electrical connection between the under bump metal layer 103 and the bonding pad 102. In this embodiment, the passivation layer 101 may be a material such as silicon oxide, silicon nitride, silicon oxynitride, or polyimide.
It should be noted that, the Under Bump Metal (UBM) layer 103 is disposed on the bonding pad 102 exposed by the passivation layer 101, and the Under Bump Metal layer 103 is used to electrically connect with the Metal interconnection structure 130 in the substrate through the bonding pad 102, and further electrically connect with the active device 110 in the substrate.
The under bump metal layer 103 is used as a transition layer between the bonding pad 102 and the conductive bump 104, so that each structure has good physical property matching, and the under bump metal layer 103 is ensured to form firm physical connection with the bonding pad 102 and the conductive bump 104. The projection of the under bump metal layer on the surface of the substrate can be coincident with the projection of the conductive bump on the surface of the substrate. The under bump metal layer 103 may be one or more of chromium (Cr), copper (Cu), titanium (Ti), nickel (Ni), or tantalum (Ta), and when a plurality of materials are selected, the under bump metal layer 103 may have a stacked structure.
On the under bump metal layer 103, a conductive bump 104 is provided for making electrical connection with the under bump metal layer 103. Specifically, the conductive bump 104 covers the under bump metal layer 103.
Referring to fig. 5, the projection OO' of the conductive bump 104 along the extending direction thereof on the substrate passes through the center point O of the substrate surface, so as to increase the maximum stress that the package structure can withstand. In this embodiment of the present invention, the extending direction is a length direction of the projection of the corresponding structure on the surface of the substrate. Specifically, taking the conductive bump located below the center point O of the substrate in fig. 5 as an example, when the conductive bump 104 is stressed, the projection OO' of the extension line of the conductive bump 104 along the extension direction of the conductive bump on the substrate passes through the center point O of the surface of the substrate, so that the area of the area (the area in the dashed frame) where the conductive bump 104 is stressed is maximized, the pressure in the area is correspondingly reduced, the interlayer dielectric layer in the substrate is prevented from being broken or stripped, the maximum stress that the package structure can bear is improved, and the reliability of the package structure is further improved.
It will be appreciated that the placement of the conductive bump 104 is limited by the location of the bonding pad 102 in the substrate and the shape of the surface of the bonding pad 102, and in an embodiment of the present invention, the length of the conductive bump 104 in the extending direction may be set to be the maximum length of the bonding pad 102 in the extending direction, so that the area of the conductive bump 104 subjected to stress is maximized to the greatest extent, so as to reduce the corresponding pressure of the area when subjected to stress.
In an alternative example, a plurality of conductive bumps may be disposed on the substrate, where each of the conductive bumps has the same shape, so as to promote the stress balance of the substrate under the stress effect, and further promote the maximum stress that can be borne by the package structure.
The projection of the conductive bump on the substrate may be an ellipse (refer to fig. 5), and the extending direction of the major axis of the ellipse is the extending direction of the under bump metal layer, or in another alternative example, the projection of the conductive bump on the substrate may also be a rounded square (refer to fig. 6), and the length direction of the rounded square is the extending direction of the under bump metal layer.
In this embodiment, the conductive bump 104 may be one or more of nickel, tin, copper, silver, gold, or palladium, and in particular, the conductive bump 104 may be a solder bump, and the solder bump 104 may be formed of a Sn-Ag alloy, a Sn-Cu alloy, a Sn-Ag-Cu alloy, or the like. Alternatively, in other embodiments, the conductive bump may be a copper bump, and the surface layer of the copper bump is covered with a cap layer (cap layer) formed of a nickel layer, a Sn-Ag alloy layer, a Sn-Cu alloy layer, a Sn-Ag-Cu alloy layer, a palladium layer, or a silver layer.
In an embodiment of the present invention, referring to fig. 3, the package structure may further include a package substrate 140, where the package substrate 140 covers a side of the base 150 where the conductive bump 104 is disposed, and is in electrical contact with the conductive bump 104.
The package substrate 140 is used for supporting and protecting the electrical structure on the base, and is electrically connected with the electrical structure on the base. The material of the package substrate 140 may be epoxy, polyimide, or the like. Specifically, in the embodiment of the present invention, the material of the package substrate 140 is epoxy. Wherein the package substrate is typically further provided with a circuit structure to enable electrical connection with the electrical structure on the base.
In the embodiment of the invention, the extending line of the conductive bump along the extending direction passes through the center point of the surface of the substrate, so that when the conductive bump is stressed, the area of the region where the conductive bump bears stress is maximized, the pressure of the region is correspondingly reduced, the interlayer dielectric layer in the substrate is prevented from being broken or stripped, the maximum stress which can be borne by the packaging structure is improved, and the reliability of the packaging structure is further improved.
Referring to fig. 7 to 11, the embodiment of the invention further provides a method for forming the package structure. The method comprises the following steps:
referring to fig. 7, a substrate 250 is provided, the substrate 250 including an interlayer dielectric layer 220.
The substrate 250 is used to provide a process basis for the subsequent formation of the package structure.
The base 250 may include a substrate 200, an active device 210, and an interlayer dielectric layer 220 covering the active device 210, and a metal interconnect structure 230 within the interlayer dielectric layer 220.
The material of the interlayer dielectric layer 220 is an ultralow dielectric constant material, and the ultralow dielectric constant material may be a material with a dielectric constant less than 2.6. Specifically, the interlayer dielectric layer 220 may be a porous material, such as porous silicon oxide.
It should be noted that, the number of active devices disposed on the substrate may be one or more, and the number of metal interconnection structures corresponds to the number of active devices, and the schematic structural diagram of fig. 7 is only a schematic illustration of a corresponding active device on the substrate. Typically, the substrate is provided with a plurality of active devices, which may be distributed over different areas of the substrate.
Referring to fig. 8, a pad 202 is formed on a surface of the substrate 250;
the bond pad 202 is used to electrically connect the metal interconnect structure 230 in the substrate 250, and thus the active device 210 in the substrate 250. Specifically, in the present embodiment, the pad 202 is disposed on the metal interconnection structure 230.
The pad 202 may be a metal material such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), or an alloy material of a plurality of metal materials, and may have a single-layer structure or a stacked structure of a plurality of layers.
In this embodiment, the bonding pad 202 may be formed by deposition and etching. Specifically, a pad material layer (not shown) may be deposited on the substrate 250, and at least the pad material layer on the metal interconnection structure is covered by a patterned mask, and the pad material layer that is not covered by the mask is further etched to remove, and then the remaining pad material layer is used as the pad 202.
Referring to fig. 9, a passivation layer 201 is formed to cover the surface of the substrate 250, the passivation layer 201 exposing the pads 202.
The passivation layer 201 is used to protect the substrate 250 and expose the bonding pad 202.
In this embodiment, the passivation layer 201 covers the interlayer dielectric layer 220 of the substrate 250 and covers the edge portion of the pad 202. The passivation layer 201 may be made of a non-organic material such as silicon oxide, silicon nitride, or silicon oxynitride, or may be made of an organic material such as polyimide, and in this embodiment, the passivation layer 201 is silicon oxide.
In this embodiment, the specific step of forming the patterned passivation layer 201 may include: forming a passivation material layer (not shown) covering the surface of the substrate 250; a first opening W1 is formed on the passivation material layer, and at least a portion of the bonding pad 202 is exposed by the first opening W1, where the remaining passivation material layer is a passivation layer 201.
Wherein, the passivation material layer can be formed by adopting a deposition process. The specific step of forming the opening on the passivation material layer may include: forming a first mask layer on the passivation material layer, wherein the passivation material layer at the position of the welding pad is exposed by the first mask layer, and other parts of the passivation material layer are covered by the first mask layer; and etching to remove the exposed passivation material layer by taking the first mask layer as a mask, forming a first opening exposing the bonding pad, and taking the rest passivation material layer as a passivation layer 201.
It should be noted that, the location of the bonding pad may be the whole area where the bonding pad is located, or may be a partial area where the bonding pad is located.
When the layout of the conductive bump (including the extending direction of the conductive bump and the length of the conductive bump in the extending direction thereof) is preset, the shape of the first opening in this step is matched with the preset layout of the conductive bump, for example, the shape of the first opening is the same as the projected shape of the conductive bump on the substrate, or the shape of the first opening is the shape obtained by shrinking the projected shape of the conductive bump on the substrate by a preset distance.
In an alternative example, the length of the conductive bump in the extending direction is the maximum length of the pad in the extending direction, and correspondingly, the length of the first opening in the extending direction is the maximum length of the pad in the extending direction, or the length of the first opening in the extending direction is the difference between the maximum length of the pad in the extending direction and 2 times of the preset distance.
Referring to fig. 10, fig. 10 is a schematic structural diagram of forming an under bump metal layer and a conductive bump according to an embodiment of the present invention, forming an under bump metal layer 203 on the pad 202 and a conductive bump 204 on the under bump metal layer 203, where an extension line of the conductive bump 204 along an extension direction thereof is projected on a center point of the substrate passing through the substrate.
The under bump metal layer 203 is used to electrically connect with the metal interconnection structure 230 in the substrate 250 through the bonding pad 202, and further electrically connect with the active device 210 in the substrate 250. The conductive bump 204 is used for electrically connecting the under bump metal layer 203 and a package substrate of a subsequent process.
In this embodiment, the under bump metallurgy 203 covers the first opening of the passivation layer.
Specifically, the step of forming the under bump metal layer 203 and the conductive bump 204 includes: forming an under bump metal material layer on the substrate; forming a conductive bump on a preset position of the under bump metal material layer, wherein the preset position corresponds to the position of the welding pad; and removing the under bump metal material layer exposed by the conductive bump by taking the conductive bump as a mask, and taking the rest under bump metal material layer as an under bump metal layer.
The under bump metal material layer is used for forming an under bump metal layer, and may be one or more of chromium (Cr), copper (Cu), titanium (Ti), nickel (Ni) or tantalum (Ta), and when a plurality of materials are selected, the under bump metal material layer may be a stacked structure, and it should be noted that when a stacked material is selected, each of the layers has good physical property matching, including having similar thermal expansion coefficient and conductivity, etc., and no eutectic phenomenon occurs between adjacent layers, so as to ensure that the under bump metal layer 203 forms a firm physical connection with the subsequent conductive structure at the substrate 250. The under bump metal material layer may be formed using a deposition process.
In this embodiment, the conductive bump 204 may be one or more of nickel, tin, copper, silver, gold, or palladium, and in particular, the conductive bump may be a solder bump, which may be formed of a Sn-Ag alloy, a Sn-Cu alloy, a Sn-Ag-Cu alloy, or the like. The specific step of forming the conductive bump may include: forming a second mask layer on the under bump metal material layer, wherein the second mask layer exposes the under bump metal material layer at the position of the welding pad and covers other areas of the under bump metal material layer; depositing a conductive material layer on the second mask layer by taking the second mask layer as a mask; and removing the third mask layer, and reserving the conductive material layer remained on the exposed under-bump metal material layer as the conductive bump.
The conductive bump is arranged on the substrate, and the conductive bump extends along the extending direction of the conductive bump at the central point of the substrate projected through the surface of the substrate, so that the maximum stress which can be borne by the packaging structure can be improved. In an alternative example, a plurality of conductive bumps may be disposed on the substrate, where each of the conductive bumps has the same shape, so as to promote the stress balance of the substrate under the stress effect, and further promote the maximum stress that can be borne by the package structure.
In the embodiment of the invention, the length of the conductive bump in the extending direction is set to be the maximum length of the welding pad in the extending direction, so that the area of the region of the conductive bump bearing stress is maximized to the greatest extent, and the corresponding pressure of the region bearing stress is reduced.
The projection of the conductive bump on the substrate may be an ellipse, and the extending direction of the major axis of the ellipse is the extending direction of the under bump metal layer, or in another alternative example, the projection of the conductive bump on the substrate may also be a rounded square, and the length direction of the rounded square is the extending direction of the under bump metal layer.
In the embodiment of the invention, a packaging substrate can be further arranged on the substrate. Specifically, referring to fig. 11, the method for forming the package structure further includes:
a package substrate 240 is provided, and the package substrate 240 is disposed on a side of the base on which the conductive bumps are disposed, and the package substrate 240 is electrically contacted with the conductive bumps 204.
The package substrate 240 is used for supporting, protecting and electrically connecting the electrical structure on the base. The material of the package substrate 240 may be epoxy, polyimide, or the like. Specifically, in the embodiment of the present invention, the material of the package substrate 240 is epoxy. Wherein, the package substrate 240 is further typically provided with a circuit structure to achieve an electrical connection with the circuit structure on the base.
The packaging substrate is electrically contacted with the conductive bump and is used for realizing the electrical connection between the packaging substrate and the substrate. The package substrate is electrically contacted with the conductive bump by soldering, i.e. soldering the conductive bump to the circuit structure of the package substrate.
Specifically, the substrate and the package substrate may be connected only by an electrical contact, or may be further fixedly connected on the basis of the electrical contact. For example, an adhesive is injected between the base and the package substrate, so that the base and the package substrate are fixedly connected.
Referring to fig. 12 to 16, the embodiment of the invention further provides a method for forming the package structure. The method further provides a detailed description of the steps of providing a substrate, including:
referring to fig. 12, a substrate 200 is provided;
the substrate 200 is used to provide a process basis for subsequent processes.
The substrate 200 may be a semiconductor substrate such as silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like. Alternatively, the substrate can be a silicon substrate on an insulator or a germanium substrate on an insulator, and other types of substrates, and those skilled in the art can choose the substrate according to actual requirements. In the embodiment of the present invention, a silicon substrate may be used as the substrate.
Referring to fig. 13, an active device 210 is formed on the substrate;
the active device 210 is a semiconductor device disposed on the surface of the substrate 200, and may be a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse, or the like, and is formed on the surface of the substrate by a corresponding semiconductor process.
Referring to fig. 14, an interlayer dielectric layer 220 is formed on the substrate 200 on the side where the active device 210 is disposed;
the interlayer dielectric layer 220 is disposed on the side of the substrate 200 where the active device 210 is disposed, and covers the active device 210.
In the embodiment of the present invention, the interlayer dielectric layer 220 is an ultralow dielectric constant material, and the ultralow dielectric constant material may be a material with a dielectric constant less than 2.6. Specifically, the interlayer dielectric layer 220 may be a porous material, such as porous silicon oxide. It should be noted that, due to the pore structure of the porous material, the brittleness of the material is high, so that the material is easy to fracture.
In the embodiment of the invention, the interlayer dielectric layer can be formed by adopting a chemical vapor deposition process.
Referring to fig. 15, a second opening W2 is formed in the interlayer dielectric layer 220, the second opening W2 exposing at least an electrical connection region of the active device 210;
the second opening W2 is used to provide a process space for the subsequent formation of the metal interconnection structure.
Specifically, the forming of the second opening W2 may include: forming a third mask layer on the interlayer dielectric layer, wherein the third mask layer exposes the interlayer dielectric layer at a preset position, and the preset position corresponds to an electric connection area of the active device; and etching to remove the exposed interlayer dielectric layer by taking the third mask layer as a mask to form the second opening.
The step of removing the exposed interlayer dielectric layer by etching can adopt wet etching, dry etching or a combination of wet etching and dry etching.
Referring to fig. 16, a metal interconnection structure 230 is formed in the second opening, and the metal interconnection structure 230 is electrically connected to the active device 210.
The metal interconnection structure is used for electrically connecting the active device.
The metal interconnect structure 230 may be conductive features (e.g., conductive lines and vias of copper, aluminum, tungsten, etc.) disposed in an interlayer dielectric layer (ILD) to electrically connect the active devices and thereby form functional circuits within the substrate 250.
In the embodiment of the invention, a deposition or sputtering process can be adopted to form the metal interconnection structure.
In the embodiment of the invention, the central point of the substrate surface of the formed conductive bump along the extending line of the extending direction of the conductive bump passes through the central point of the substrate surface, so that the area of the region where the conductive bump bears stress is maximized, the pressure of the region when the conductive bump is stressed is reduced, the interlayer dielectric layer in the substrate is prevented from being broken or stripped, the maximum stress which the package structure can bear is improved, and the reliability of the package structure is further improved.
It should be noted that, the package structure in the embodiment of the present invention may be formed by using the method for forming the package structure in the embodiment, or may be formed by using other forming methods. The specific descriptions of the package structure and the forming method thereof in this embodiment may be referred to each other, and are not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (17)

1. A package structure, comprising:
the substrate comprises an interlayer dielectric layer;
a bonding pad positioned on the surface of the substrate;
an under bump metal layer on the bonding pad;
and the conductive bump is positioned on the under bump metal layer, and an extension line of the conductive bump along the extension direction of the conductive bump is arranged at the center point of the substrate projected through the surface of the substrate.
2. The package structure of claim 1 wherein the interlayer dielectric layer is an ultra low dielectric constant material.
3. The package structure according to claim 1 or 2, wherein a length of the conductive bump in an extending direction thereof is a maximum length of the pad in the extending direction.
4. The package structure of claim 1 or 2, wherein the plurality of conductive bumps are the same shape.
5. The package structure of claim 1 or 2, wherein the projection of the conductive bump on the substrate is elliptical, and the extending direction of the major axis of the ellipse is the extending direction of the under bump metal layer.
6. The package structure of claim 1 or 2, wherein the projection of the conductive bump on the substrate is a rounded square, and the length direction of the rounded square is the extending direction of the under bump metal layer.
7. The package structure of claim 1, further comprising a passivation layer on the substrate, the passivation layer having a plurality of openings, the under bump metal layer covering the openings of the passivation layer.
8. The package structure of claim 1, wherein the substrate further comprises: and the metal interconnection structure is positioned in the interlayer dielectric layer and is electrically connected with the welding pad.
9. The package structure of claim 1, wherein the package structure further comprises: and the packaging substrate covers one side of the substrate provided with the conductive bump and is electrically contacted with the conductive bump.
10. The package structure of claim 1 or 2, wherein a projection of the under bump metal layer on the substrate surface coincides with a projection of the conductive bump on the substrate surface.
11. The package structure of claim 1, wherein the under bump metal layer is one or more of chromium, copper, titanium, nickel, or tantalum.
12. The package structure of claim 1, wherein the conductive bump is one or more of nickel, tin, copper, silver, gold, or palladium.
13. The method for forming the packaging structure is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises an interlayer dielectric layer;
forming a welding pad on the surface of the substrate;
and forming an under bump metal layer positioned on the welding pad and a conductive bump positioned on the under bump metal layer, wherein an extension line of the conductive bump along the extension direction of the conductive bump is projected on a central point of the substrate, which is projected through the substrate.
14. The method of claim 13, wherein forming an under bump metal layer on the bond pad and a conductive bump on the under bump metal layer on the substrate comprises:
forming an under bump metal material layer on the substrate;
forming a conductive bump on a preset position of the under bump metal material layer, wherein the preset position corresponds to the position of the welding pad;
and removing the under bump metal material layer exposed by the conductive bump by taking the conductive bump as a mask, and taking the rest under bump metal material layer as an under bump metal layer.
15. The method of claim 14, wherein after the step of forming a bond pad on the surface of the substrate, the step of forming an under bump metal layer on the bond pad and a conductive bump on the under bump metal layer on the substrate is preceded by the step of:
forming a passivation material layer covering the surface of the substrate;
forming a first opening on the passivation material layer, wherein the first opening at least exposes part of the welding pad, and the rest passivation material layer is a passivation layer;
in the step of forming an under bump metal layer on the bonding pad, each under bump metal layer covers the first opening of the passivation layer.
16. The method of claim 13, wherein the interlayer dielectric layer is an ultra-low dielectric constant material, and the step of providing a substrate comprises:
providing a substrate;
forming an active device on the substrate;
forming an interlayer dielectric layer on one side of the substrate where the active device is arranged;
forming a second opening in the interlayer dielectric layer, wherein the second opening at least exposes an electric connection area of the active device;
forming a metal interconnection structure in the second opening, wherein the metal interconnection structure is electrically connected with the active device;
in the step of forming a plurality of bonding pads on the surface of the substrate, the bonding pads are electrically connected with the metal interconnection structure.
17. The method as recited in claim 13, further comprising:
providing a packaging substrate;
and arranging the packaging substrate on one side of the substrate provided with the conductive bump, and enabling the packaging substrate to be in electrical contact with the conductive bump.
CN202010346530.7A 2020-04-27 2020-04-27 Package structure and method for forming the same Active CN113644040B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1492707A (en) * 1975-04-17 1977-11-23 Agency Ind Science Techn Pressure contact type semiconductor devices
EP0685886A1 (en) * 1994-05-31 1995-12-06 Kabushiki Kaisha Toshiba MOS composite type semiconductor device
CN103311224A (en) * 2012-03-16 2013-09-18 台湾积体电路制造股份有限公司 Contact test structure and method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4311376B2 (en) * 2005-06-08 2009-08-12 セイコーエプソン株式会社 Semiconductor device, semiconductor device manufacturing method, electronic component, circuit board, and electronic apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1492707A (en) * 1975-04-17 1977-11-23 Agency Ind Science Techn Pressure contact type semiconductor devices
EP0685886A1 (en) * 1994-05-31 1995-12-06 Kabushiki Kaisha Toshiba MOS composite type semiconductor device
CN103311224A (en) * 2012-03-16 2013-09-18 台湾积体电路制造股份有限公司 Contact test structure and method

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