WO2003027767A3 - Mittel und verfahren zur strukturierung eines substrates mit einer maske - Google Patents

Mittel und verfahren zur strukturierung eines substrates mit einer maske Download PDF

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Publication number
WO2003027767A3
WO2003027767A3 PCT/DE2001/003519 DE0103519W WO03027767A3 WO 2003027767 A3 WO2003027767 A3 WO 2003027767A3 DE 0103519 W DE0103519 W DE 0103519W WO 03027767 A3 WO03027767 A3 WO 03027767A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
mask
structuring
etching
wet
Prior art date
Application number
PCT/DE2001/003519
Other languages
English (en)
French (fr)
Other versions
WO2003027767A2 (de
Inventor
Robert Kachel
Gerhard Franz
Original Assignee
Infineon Technologies Ag
Robert Kachel
Gerhard Franz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Robert Kachel, Gerhard Franz filed Critical Infineon Technologies Ag
Priority to US10/489,632 priority Critical patent/US20050020072A1/en
Priority to PCT/DE2001/003519 priority patent/WO2003027767A2/de
Priority to EP01978136A priority patent/EP1425790A2/de
Publication of WO2003027767A2 publication Critical patent/WO2003027767A2/de
Publication of WO2003027767A3 publication Critical patent/WO2003027767A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

Mittel und Verfahren zur Strukturierung eines Substrates mit einer mehrlagigen MaskeMittel und Verfahren zur Strukturierung eines Substrates mit einer mehrlagigen Maske (1, 2, 3, 4), dadurch gekennzeichnet, dass die Maske mindestens eine Schicht (1) aus einem naßstrukturierbaren und gegenüber einer Trockenätzung resistenten Dielektrikum aufweist. Damit wird ein unerwünschtes Anätzen des Substrates vermieden.
PCT/DE2001/003519 2001-09-11 2001-09-11 Mittel und verfahren zur strukturierung eines substrates mit einer maske WO2003027767A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/489,632 US20050020072A1 (en) 2001-09-11 2001-09-11 Means and method for patterning a substrate with a mask
PCT/DE2001/003519 WO2003027767A2 (de) 2001-09-11 2001-09-11 Mittel und verfahren zur strukturierung eines substrates mit einer maske
EP01978136A EP1425790A2 (de) 2001-09-11 2001-09-11 Mittel und verfahren zur strukturierung eines substrates mit einer maske

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/DE2001/003519 WO2003027767A2 (de) 2001-09-11 2001-09-11 Mittel und verfahren zur strukturierung eines substrates mit einer maske

Publications (2)

Publication Number Publication Date
WO2003027767A2 WO2003027767A2 (de) 2003-04-03
WO2003027767A3 true WO2003027767A3 (de) 2003-07-17

Family

ID=5648285

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/003519 WO2003027767A2 (de) 2001-09-11 2001-09-11 Mittel und verfahren zur strukturierung eines substrates mit einer maske

Country Status (3)

Country Link
US (1) US20050020072A1 (de)
EP (1) EP1425790A2 (de)
WO (1) WO2003027767A2 (de)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125402A (ja) * 1990-09-17 1992-04-24 Canon Inc 微小プローブの製造方法
US6054391A (en) * 1998-01-16 2000-04-25 Samsung Electronics Co., Ltd. Method for etching a platinum layer in a semiconductor device
WO2000049651A1 (en) * 1999-02-17 2000-08-24 Applied Materials, Inc. Improved masking methods and etching sequences for patterning electrodes of high density ram capacitors

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5871886A (en) * 1996-12-12 1999-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Sandwiched middle antireflection coating (SMARC) process
JP3373147B2 (ja) * 1998-02-23 2003-02-04 シャープ株式会社 フォトレジスト膜及びそのパターン形成方法
US6136511A (en) * 1999-01-20 2000-10-24 Micron Technology, Inc. Method of patterning substrates using multilayer resist processing
US6410453B1 (en) * 1999-09-02 2002-06-25 Micron Technology, Inc. Method of processing a substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125402A (ja) * 1990-09-17 1992-04-24 Canon Inc 微小プローブの製造方法
US6054391A (en) * 1998-01-16 2000-04-25 Samsung Electronics Co., Ltd. Method for etching a platinum layer in a semiconductor device
WO2000049651A1 (en) * 1999-02-17 2000-08-24 Applied Materials, Inc. Improved masking methods and etching sequences for patterning electrodes of high density ram capacitors

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
DEVOLDER T ET AL: "SUB-50 NM PLANAR MAGNETIC NANOSTRUCTURES FABRICATED BY ION IRRADIATION", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 74, no. 22, 31 May 1999 (1999-05-31), pages 3383 - 3385, XP000847308, ISSN: 0003-6951 *
MACKSEY H M: "GAAS POWER FET'S HAVING THE GATE RECESS NARROWER THAN THE GATE", IEEE ELECTRON DEVICE LETTERS, IEEE INC. NEW YORK, US, vol. EDL-7, no. 2, February 1986 (1986-02-01), pages 69 - 70, XP000818908, ISSN: 0741-3106 *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 386 (P - 1404) 18 August 1992 (1992-08-18) *

Also Published As

Publication number Publication date
US20050020072A1 (en) 2005-01-27
EP1425790A2 (de) 2004-06-09
WO2003027767A2 (de) 2003-04-03

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