WO2003025770A3 - Reconfigurable system - Google Patents

Reconfigurable system Download PDF

Info

Publication number
WO2003025770A3
WO2003025770A3 PCT/EP2002/010084 EP0210084W WO03025770A3 WO 2003025770 A3 WO2003025770 A3 WO 2003025770A3 EP 0210084 W EP0210084 W EP 0210084W WO 03025770 A3 WO03025770 A3 WO 03025770A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
vpu
cpu
designed
created
Prior art date
Application number
PCT/EP2002/010084
Other languages
German (de)
French (fr)
Other versions
WO2003025770A2 (en
Inventor
Martin Vorbach
Original Assignee
Pact Xpp Technologies Ag
Martin Vorbach
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pact Xpp Technologies Ag, Martin Vorbach filed Critical Pact Xpp Technologies Ag
Priority to EP02779326A priority Critical patent/EP1449109A2/en
Priority to AU2002342668A priority patent/AU2002342668A1/en
Priority to US10/487,681 priority patent/US7577822B2/en
Priority to PCT/EP2002/010479 priority patent/WO2003025781A2/en
Priority to AU2002338729A priority patent/AU2002338729A1/en
Priority to US10/490,081 priority patent/US8429385B2/en
Priority to EP02791644A priority patent/EP1472616B8/en
Priority to JP2003538928A priority patent/JP4456864B2/en
Priority to AU2002357982A priority patent/AU2002357982A1/en
Priority to AT02791644T priority patent/ATE533111T1/en
Priority to PCT/EP2002/010572 priority patent/WO2003036507A2/en
Publication of WO2003025770A2 publication Critical patent/WO2003025770A2/en
Priority to AU2003286131A priority patent/AU2003286131A1/en
Priority to EP03776856.1A priority patent/EP1537501B1/en
Priority to PCT/EP2003/008081 priority patent/WO2004021176A2/en
Priority to JP2005506110A priority patent/JP2005535055A/en
Priority to EP03784053A priority patent/EP1535190B1/en
Priority to PCT/EP2003/008080 priority patent/WO2004015568A2/en
Priority to AU2003260323A priority patent/AU2003260323A1/en
Priority to US10/523,764 priority patent/US8156284B2/en
Publication of WO2003025770A3 publication Critical patent/WO2003025770A3/en
Priority to US12/247,076 priority patent/US8209653B2/en
Priority to US12/570,943 priority patent/US8914590B2/en
Priority to US12/621,860 priority patent/US8281265B2/en
Priority to JP2009271120A priority patent/JP2010079923A/en
Priority to US12/947,167 priority patent/US20110238948A1/en
Priority to US13/023,796 priority patent/US8686475B2/en
Priority to US14/923,702 priority patent/US10579584B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Abstract

The invention relates to a reconfigurable processor (VPU) which is designed to be integrated into a technical environment comprising a standard processor (CPU), such as a DSP, RISC, or CISC processor or a (micro)controller. Said processor must be designed in such a way that a connection is created which is as simple and as efficient as possible. According to another aspect of the invention, the system created is easy to programme. The invention takes into account the continued use of existing programmes of the CPU, the code compatibility and the simple integration of the VPU into the existing programmes.
PCT/EP2002/010084 2001-09-03 2002-09-09 Reconfigurable system WO2003025770A2 (en)

Priority Applications (26)

Application Number Priority Date Filing Date Title
EP02779326A EP1449109A2 (en) 2001-09-07 2002-09-09 Reconfigurable system
AU2002342668A AU2002342668A1 (en) 2001-09-07 2002-09-09 Reconfigurable system
US10/487,681 US7577822B2 (en) 2001-12-14 2002-09-09 Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
PCT/EP2002/010479 WO2003025781A2 (en) 2001-09-19 2002-09-18 Router
AU2002338729A AU2002338729A1 (en) 2001-09-19 2002-09-18 Router
US10/490,081 US8429385B2 (en) 2001-09-03 2002-09-19 Device including a field having function cells and information providing cells controlled by the function cells
EP02791644A EP1472616B8 (en) 2001-09-19 2002-09-19 Reconfigurable elements
JP2003538928A JP4456864B2 (en) 2001-09-19 2002-09-19 Reconfigurable element
AU2002357982A AU2002357982A1 (en) 2001-09-19 2002-09-19 Reconfigurable elements
AT02791644T ATE533111T1 (en) 2001-09-19 2002-09-19 RECONFIGURABLE ELEMENTS
PCT/EP2002/010572 WO2003036507A2 (en) 2001-09-19 2002-09-19 Reconfigurable elements
EP03776856.1A EP1537501B1 (en) 2002-08-07 2003-07-23 Method and device for processing data
PCT/EP2003/008081 WO2004021176A2 (en) 2002-08-07 2003-07-23 Method and device for processing data
AU2003286131A AU2003286131A1 (en) 2002-08-07 2003-07-23 Method and device for processing data
JP2005506110A JP2005535055A (en) 2002-08-07 2003-07-24 Data processing method and data processing apparatus
EP03784053A EP1535190B1 (en) 2002-08-07 2003-07-24 Method of operating simultaneously a sequential processor and a reconfigurable array
PCT/EP2003/008080 WO2004015568A2 (en) 2002-08-07 2003-07-24 Data processing method and device
AU2003260323A AU2003260323A1 (en) 2002-08-07 2003-07-24 Data processing method and device
US10/523,764 US8156284B2 (en) 2002-08-07 2003-07-24 Data processing method and device
US12/247,076 US8209653B2 (en) 2001-09-03 2008-10-07 Router
US12/570,943 US8914590B2 (en) 2002-08-07 2009-09-30 Data processing method and device
US12/621,860 US8281265B2 (en) 2002-08-07 2009-11-19 Method and device for processing data
JP2009271120A JP2010079923A (en) 2001-09-19 2009-11-30 Processing chip, system including chip, multiprocessor device, and multi-core processor device
US12/947,167 US20110238948A1 (en) 2002-08-07 2010-11-16 Method and device for coupling a data processing unit and a data processing array
US13/023,796 US8686475B2 (en) 2001-09-19 2011-02-09 Reconfigurable elements
US14/923,702 US10579584B2 (en) 2002-03-21 2015-10-27 Integrated data processing core and array data processor and method for processing algorithms

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US31787601P 2001-09-07 2001-09-07
US60/317,876 2001-09-07
EP01129923 2001-12-14
EP01129923.7 2001-12-14
DE10206856 2002-02-18
DE10206856.9 2002-02-18

Publications (2)

Publication Number Publication Date
WO2003025770A2 WO2003025770A2 (en) 2003-03-27
WO2003025770A3 true WO2003025770A3 (en) 2004-02-26

Family

ID=27214707

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/010084 WO2003025770A2 (en) 2001-09-03 2002-09-09 Reconfigurable system

Country Status (3)

Country Link
EP (1) EP1449109A2 (en)
AU (1) AU2002342668A1 (en)
WO (1) WO2003025770A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994006077A1 (en) * 1992-08-28 1994-03-17 Siemens Aktiengesellschaft Computer system with at least one microprocessor and at least one coprocessor, and a method of operating the system
US5970254A (en) * 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994006077A1 (en) * 1992-08-28 1994-03-17 Siemens Aktiengesellschaft Computer system with at least one microprocessor and at least one coprocessor, and a method of operating the system
US5970254A (en) * 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
DONANDT J: "Improving response time of programmable logic controllers by use of a Boolean coprocessor", COMPEURO '89., 'VLSI AND COMPUTER PERIPHERALS. VLSI AND MICROELECTRONIC APPLICATIONS IN INTELLIGENT PERIPHERALS AND THEIR INTERCONNECTION NETWORKS', PROCEEDINGS. HAMBURG, WEST GERMANY 8-12 MAY 1989, WASHINGTON, DC, USA,IEEE COMPUT. SOC. PR, US, 8 May 1989 (1989-05-08), pages 4 - 167-4-169, XP010016181, ISBN: 0-8186-1940-6 *
HAUSER J R ET AL: "Garp: a MIPS processor with a reconfigurable coprocessor", FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, 1997. PROCEEDINGS., THE 5TH ANNUAL IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 16-18 APRIL 1997, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 16 April 1997 (1997-04-16), pages 12 - 21, XP010247463, ISBN: 0-8186-8159-4 *
KOCH A ET AL: "PRACTICAL EXPERIENCES WITH THE SPARXIL CO-PROCESSOR", CONFERENCE RECORD OF THE 31ST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS. PACIFIC GROVE, CA., NOV. 2 - 5, 1997, ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, LOS ALAMITOS, CA.: IEEE, US, vol. 1, 2 November 1997 (1997-11-02), pages 394 - 398, XP000883965, ISBN: 0-8186-8317-1 *
TENCA A F ET AL: "A variable long-precision arithmetic unit design for reconfigurable coprocessor architectures", FPGAS FOR CUSTOM COMPUTING MACHINES, 1998. PROCEEDINGS. IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 15-17 APRIL 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 15 April 1998 (1998-04-15), pages 216 - 225, XP010298173, ISBN: 0-8186-8900-5 *

Also Published As

Publication number Publication date
EP1449109A2 (en) 2004-08-25
AU2002342668A1 (en) 2003-04-01
WO2003025770A2 (en) 2003-03-27

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