WO2003025770A2 - Systeme reconfigurable - Google Patents

Systeme reconfigurable Download PDF

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Publication number
WO2003025770A2
WO2003025770A2 PCT/EP2002/010084 EP0210084W WO03025770A2 WO 2003025770 A2 WO2003025770 A2 WO 2003025770A2 EP 0210084 W EP0210084 W EP 0210084W WO 03025770 A2 WO03025770 A2 WO 03025770A2
Authority
WO
WIPO (PCT)
Prior art keywords
vpu
data processing
cpu
processor
data
Prior art date
Application number
PCT/EP2002/010084
Other languages
German (de)
English (en)
Other versions
WO2003025770A3 (fr
Inventor
Martin Vorbach
Original Assignee
Pact Xpp Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pact Xpp Technologies Ag filed Critical Pact Xpp Technologies Ag
Priority to EP02779326A priority Critical patent/EP1449109A2/fr
Priority to AU2002342668A priority patent/AU2002342668A1/en
Priority to US10/487,681 priority patent/US7577822B2/en
Priority to AU2002338729A priority patent/AU2002338729A1/en
Priority to PCT/EP2002/010479 priority patent/WO2003025781A2/fr
Priority to AT02791644T priority patent/ATE533111T1/de
Priority to AU2002357982A priority patent/AU2002357982A1/en
Priority to PCT/EP2002/010572 priority patent/WO2003036507A2/fr
Priority to JP2003538928A priority patent/JP4456864B2/ja
Priority to EP02791644A priority patent/EP1472616B8/fr
Priority to US10/490,081 priority patent/US8429385B2/en
Publication of WO2003025770A2 publication Critical patent/WO2003025770A2/fr
Priority to EP03776856.1A priority patent/EP1537501B1/fr
Priority to AU2003286131A priority patent/AU2003286131A1/en
Priority to PCT/EP2003/008081 priority patent/WO2004021176A2/fr
Priority to JP2005506110A priority patent/JP2005535055A/ja
Priority to US10/523,764 priority patent/US8156284B2/en
Priority to PCT/EP2003/008080 priority patent/WO2004015568A2/fr
Priority to EP03784053A priority patent/EP1535190B1/fr
Priority to AU2003260323A priority patent/AU2003260323A1/en
Publication of WO2003025770A3 publication Critical patent/WO2003025770A3/fr
Priority to US12/247,076 priority patent/US8209653B2/en
Priority to US12/570,943 priority patent/US8914590B2/en
Priority to US12/621,860 priority patent/US8281265B2/en
Priority to JP2009271120A priority patent/JP2010079923A/ja
Priority to US12/947,167 priority patent/US20110238948A1/en
Priority to US13/023,796 priority patent/US8686475B2/en
Priority to US14/923,702 priority patent/US10579584B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Definitions

  • the present invention relates to what is claimed in the preamble.
  • the present invention thus addresses the question of how a reconfigurable processor can be connected to a standard processor in a particularly favorable manner.
  • a reconfigurable architecture is understood to mean modules (VPU) with configurable function and / or networking, in particular integrated modules with a plurality of arithmetic and / or logical and / or logical and / or analog and / or storing and / or internal / external arranged in one or more dimensions networking modules that are connected to each other directly or through a bus system.
  • the category of these modules includes, in particular, systolic arrays, neural networks, multiprocessor systems, processors with a plurality of arithmetic units and / or logical cells and / or communicative / peripheral cells (10), networking and network components such as crossbar switches, as well as known ones Modules of the genus FPGA, DPGA, Chameleon, XPUTER, etc.
  • the above Architecture is used as an example for clarification and is referred to below as the VPU.
  • the architecture consists of any arithmetic, logical (also memory) and / or memory cells and / or network cells and / or communicative / peripheral (IO) cells (PAEs), which can be arranged in a one- or multi-dimensional matrix (PAC), whereby the matrix can have different, arbitrarily designed cells; the bus systems are also understood as cells.
  • a configuration unit (CT) is assigned to the matrix as a whole or parts thereof, which influences the networking and function of the PA.
  • the object of the invention is to provide something new for commercial use.
  • a reconfigurable processor is therefore designed into a technical environment that has a standard processor (CPU), such as a DSP, RISC, CISC processor or (micro) controller.
  • CPU such as a DSP, RISC, CISC processor or (micro) controller.
  • the design is such that there is a connection that is as simple as possible and yet very powerful.
  • VPUs Reconfigurable modules
  • PACT XPP technology a technical environment and programming methods.
  • Morphics a technical environment in which a prosthesis is atypically atypically atypically atypically atypically atypically atypically atypically atypically atypically atypically atypically atypically atypically atypically atypically atypically atypicallybstructive XPP technology, Morphics, Morphosys, Chameleon
  • VPUs Reconfigurable modules of different types (such as PACT XPP technology, Morphics, Morphosys, Chameleon) are largely incompatible with existing technical environments and programming methods.
  • the programs of the blocks are further incompatible with existing programs from CPUs.
  • a considerable development effort for programming is required, eg. B. especially for building blocks of the genera Morphics, Morphosys.
  • Chameleon already integrates a standard processor (ARC) on the reconfigurable modules. This means that programming tools are available.
  • ARC standard processor
  • a VPU (or, without being specifically mentioned, several VPUs) is coupled to a preferred CPU in such a way that it takes the place and function of a coprocessor there.
  • the function as a coprocessor enables simple integration into existing program codes in accordance with the already existing methods for handling coprocessors according to the prior art.
  • the system can in particular be designed as a (standard) processor or assembly and / or be integrated in a semiconductor (system on chip SoC).
  • CPU and VPU In order to provide the coprocessor connection between CPU and VPU, data or information exchange between CPU and VPU is necessary.
  • the processor must typically convey data and instructions to the coprocessor unit as to what must be done with them.
  • the data exchange between CPU and VPU can now take place by means of memory coupling and / or IO coupling.
  • the CPU and VPU can share all resources; in special configurations, on the other hand, it is also possible for the CPU and VPU to use only a part of the resources together, while other resources are explicitly and exclusively available for the CPU or VPU.
  • the question of which variant is preferred will typically depend, among other things, on the overall design of the system, the possible costs, available resources, the expected data load, etc. It should be noted that, where reference has been made to a single CPU, several CPUs can also be addressed together.
  • data records and / or configurations can be copied or written / read into memory areas specially provided for this purpose and / or corresponding base addresses can be set so that they point to the respective data areas.
  • Variant provided a record that, for example, the
  • Basic settings of a VPU includes, such as certain base addresses. Furthermore, status variables to control and function control of a VPU by a CPU in the data record or for separate transmission and be exchanged with or separately from data.
  • the addresses can be flexibly distributed and assigned. Preferably, therefore, only a basic address in the I / O or memory address space needs to be firmly agreed in order to serve with its data record as a pointer to the flexibly defined addresses.
  • the data record can be exchanged via a common memory (RAM) and / or via a common peripheral address space (10).
  • RAM common memory
  • the addresses can be flexibly distributed and assigned.
  • one-sided or mutual interrupt procedures e.g. interrupt lines
  • Interrupts can also be used to synchronize data and / or DMA transfers.
  • a VPU is started by a CPU and then independently processes the started or instructed application.
  • a preferred structure is particularly powerful, in which the VPU used provides its own mechanisms for loading and checking configurations.
  • the genus of these VPUs include, for example, PACT XPP and Chameleon.
  • the circuits according to the invention enable a method of operation in such a way that all configurations of the VPU or part of the VPU configurations are loaded into a memory together with the program to be executed by the CPU.
  • the CPU can refer the VPU to the memory locations during the execution of the program (e.g. by specifying the addresses or Pointer) that contain the configurations to be executed.
  • the VPU can then load the configurations independently and without further influence from the CPU.
  • the processor issues the instruction to the CPU to load a specific configuration.
  • the reconfigurable processor which then serves as a coprocessor, can therefore preferably be called up via a single command to the loading logic.
  • prior agreement between the VPU and CPU that is, the calling host processor, can be used to determine exactly which configuration is to be carried out by which call.
  • corresponding control means can be provided in the charging logic unit, be it dedicated, implemented or formed by one or more reconfigurable cells of the reconfigurable processor. Execution starts immediately or if necessary with additional information (eg interrupt and / or start command) from the CPU.
  • the VPU can read and write data independently within one or more memories, some of which can be together with or independent of the CPU.
  • the VPU can also independently load new configurations from the memory and, if necessary, reconfigure itself without the need for further influence by the CPU.
  • sequence control of a VPU can be carried out directly by a program running on the CPU, which is basically the main program that outsources certain subroutines to the VPU. This is a particularly easy to implement variant.
  • Mechanisms controlled by the operating system are preferably used for synchronization and sequence control.
  • a simple scheduler can, after transfer of the function to the VPU, especially where possible,
  • the task scheduler switches over to another task (for example another main program).
  • the VPU can continue to work in the background regardless of the current CPU task.
  • Each newly activated task if it uses the VPU, is typically checked before use to determine whether it is available for data processing or is currently still processing data in a way that blocks the required VPU resources; then either the termination of the data transfer work or, if preferred, the task can be changed.
  • descriptor tables which can be implemented as follows, for example:
  • each task To call up the VPU, each task generates one or more tables (VPUPROC) with a suitable defined data format in the memory area assigned to it.
  • This table contains all tax information for a VPU, e.g. the program / configuration to be executed (or pointer to the corresponding memory locations) and / or memory location (s) (or pointer to it) and / or data sources (or pointer to it) of the input data and / or the memory location (s) (or pointers to them) of the operands or the result data.
  • a table or linked list (LINKLIST), which points to all VPUPROC tables in the order in which they were created and / or called, can be located in the memory area of the operating system, for example.
  • the data processing on the VPU is now preferably carried out in such a way that a main program creates a VPUPROC and calls the VPU via the operating system.
  • the operating system creates an entry in the LINKLIST.
  • the VPU processes the LINKLIST and executes the referenced VPUPROC.
  • the termination of a respective data processing is then preferably indicated in each case by a corresponding entry in the LINKLIST and / or VPUCALL table, which the CPU z. B. can poll by regular pollen.
  • the VPU works largely independently of the CPU.
  • the CPU and the VPU can perform independent and different tasks per time unit.
  • the operating system and / or the respective tasks only have to monitor the tables (LINKLIST or VPUPROC).
  • the LINKLIST can also be dispensed with by linking the VPUPROCs to one another using pointers, as is the case, for example, with B. is known from lists. Processed VPUPROCs are removed from the list, new ones are added to the list. The method is known to programmers and therefore does not have to be carried out further.
  • FIG. 1 shows a section from an exemplary CPU system, for example a DSP of the type C6000 from Texas Instruments or a microcontroller from ARM (0201).
  • Program memory (0202), data memory (0203), any peripherals (0204) and EMIF (0205) are shown.
  • a VPU is integrated as a coprocessor (0208) via a memory bus (0206) and a peripheral bus (0207).
  • a DMA controller (EDMA) (0209) can perform any DMA transfers, for example between memory (0203) and VPU (0208) or memory (0203) and peripherals (0204).
  • the VPU and / or CPU can also access the memory independently without the aid of a DMA.
  • the shared memory can in particular also be designed as a dual-port or multi-port memory.
  • Additional modules can be assigned to the system, in particular reconfigurable FPGAs can be used to enable fine-grained processing of individual signals or data bits and / or flexible adaptable interfaces (eg various serial interfaces (V24, USB, etc.), various parallel interfaces , Hard disk interfaces, Ethernet, telecommunications interfaces (a / b, T0, ISDN, DSL, etc)).
  • reconfigurable FPGAs can be used to enable fine-grained processing of individual signals or data bits and / or flexible adaptable interfaces (eg various serial interfaces (V24, USB, etc.), various parallel interfaces , Hard disk interfaces, Ethernet, telecommunications interfaces (a / b, T0, ISDN, DSL, etc)).
  • FIG 3 shows a more abstract system definition.
  • a CPU (0301) is assigned memory (0302), to which it has write and / or read access.
  • a VPU (0303) is coupled to the memory.
  • the VPU is divided into a CT part (0309) and the reconfigurable elements for data processing (0310).
  • the memory can have several independent access busses that can possibly be used simultaneously (multiport).
  • the memory is segmented into a number of independent segments (memory banks), with each bank being able to be accessed independently. All segments are preferably within a uniform address space.
  • one segment is mainly available for the CPU (0304), another segment is mainly available for data processing of the VPU (0305), another segment is mainly available for configuration data of the VPU (0306).
  • a fully configured VPU typically and preferably has its own address generators and / or DMAs in order to carry out data transfers.
  • a DMA (0307) is provided within the system (FIG. 3) for data transfers with the VPU.
  • the system contains IO means (0308) to which the CPU and VPU can have access. Both the CPU and the VPU can each have dedicated memory areas and IO areas to which the other has no access.
  • a data record (0311) which, as shown graphically, can be in the memory area and / or in the IO area and / or partially in one of the two is used for communication between CPU and VPU, e.g. B. for the exchange of basic parameters and control information.
  • the data record can contain the following information, for example, and thus represents a basic setting data record:
  • the CPU and VPU are synchronized by polling status data and / or information and / or preferably by interrupt control (0312).
  • the basic setting data record can be a LINKLIST and / or
  • Contain VPUCALLs or alternatively point to the LINKLIST and / or VPUCALLs or the first entry of each by pointer.
  • FIG. 4 shows a possible configuration of the interface structure of a VPU for integration into a system similar to FIG. 3.
  • the VPU is assigned a memory / DMA and / or IO interface for data transfer (0401); another system interface (0402) takes over the sequential control such as B. managing interrupts, starting / stopping processing, exchanging error states, etc.
  • the memory / DMA and / or IO interface is connected to a memory bus and / or IO bus.
  • the system interface is preferably connected to an IO bus, but can alternatively or additionally be connected to a memory in accordance with 0311.
  • the interfaces (0401, 0402) can be designed to adapt different operating frequencies of the CPU and / or VPU and / or system and can have a clock adaptation circuit, for example the system or the CPU can
  • the interfaces can carry out a translation of the bus protocols with a protocol adaptation circuit, for example
  • the VPU internal protocol can be converted to an external AMBA bus protocol and vice versa.
  • the memory / DMA and / or IO interface supports the memory access of the CT to an external memory, which is preferably done directly (memory mapped).
  • the data transfer of the CT (s) and / or PAC (s) can be buffered e.g. B. via FIFO stages.
  • External memory e.g. 0308, 0203
  • DMA internal and / or external DMA transfers can also be carried out.
  • the data processing is controlled via the system interface, such as the initialization and / or the start of configurations. Status and / or error states are also exchanged. Interrupts for the control and synchronization between the CT's and a CPU can be supported.
  • the system interface can convert internal VPU protocols in such a way that they are converted to external (standard) protocols (e.g. AMBA).
  • AMBA external (standard) protocols
  • bus interfaces RAM cells, I / O cells and the like as parts (PAEs) of a VPU. This also applies if these units are to be used for the processor-coprocessor coupling.
  • a preferred method for code generation for the system described is described in the patent application PACT20, which is fully incorporated for the purposes of disclosure.
  • the method describes a compiler that divides program code into code for a CPU and code for a VPU. Disassembly is carried out on the different processors using different methods. In a particularly preferred embodiment, the respective disassembled The interface codes for communication between the CPU and the VPU have been added to the codes. The expansion can be done automatically by the compiler.
  • An advantage according to the invention is that administration and / or interface expenditure and programming of the system according to the invention are inexpensive and simple.
  • the following tables show exemplary communications between a CPU and a VPU.
  • the respective active units are assigned to the columns: CPU, system DMA and DMA interface (EDMA) or memory interface (memory I / F), system interface (system I / F, 0402), CT's , as well as the PAC.
  • EDMA system DMA and DMA interface
  • memory I / F system interface
  • system I / F system interface
  • CT's system interface
  • the execution cycles of the individual cycles are entered in the lines.
  • Kl references a configuration to be executed 1.
  • the first table shows, for example, a sequence when using the system DMA (EDMA) for data transfer.
  • EDMA system DMA
  • Each line shows a sequential control process; the columns show the respective activity in the corresponding assembly:
  • a second table shows, for example, a preferred, optimized process.
  • the VPU itself has direct access to the configuration memory (0306). Furthermore, the data transfers are carried out by DMA circuitry within the VPU, which can, for example, be permanently implemented (PACT03) and / or arise from the configuration of configurable parts of the PAC.
  • PACT03 permanently implemented
  • the work and synchronization effort for the CPU is minimal, which means maximum performance.
  • the method can provide for several configurations to be carried out on different areas of the VPU, that is to say on different PAEs at the same time, or to be time-multiplexed on the same resources.
  • a type of "double buffering" can be used for particularly simple and at the same time fast reconfiguration, in which a plurality of VPUs are provided, one part being able to be reconfigured at a time of the VPUs, while another part is computing and possibly another is inactive can be.
  • the data, trigger, status connections etc. are suitably exchanged between the plurality of VPUs and, if necessary, interconnected by addressed buses and / or multiplexers / demultiplexers in accordance with the currently active and / or reconfigurable VPUs.
  • the query as to whether the CPU can then process the program parts to be executed by it finished, can in turn via polling or the like. happen.
  • all of the methods described can be used both for coupling a CPU to a VPU as a coprocessor and vice versa. What is important here is the type of coupling for which the operating system is designed. It should be pointed out that it is in particular possible to provide an operating system which enables mutual coupling, that is to say in particular optionally couples the CPU to the VPU or parts thereof and vice versa.
  • the latter is particularly advantageous, for example, if entire program blocks with predominantly sequential parts are to be delivered by the VPU as the host to the CPU as coprocessor and these program blocks still have partially strong vectorial or parallel code that can be quasi retransmitted by the CPU, in particular in response to a determined current or forecasted VPU load.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

La présente invention concerne un processeur reconfigurable (VPU) conçu pour être intégré dans un environnement technique qui comprend un processeur standard (CPU), tel qu'un processeur DSP, RISC ou CISC ou un (micro)contrôleur. Ce processeur doit être conçu pour être connecté de la manière la plus simple et performante possible. Selon un autre aspect de cette invention, le système résultant doit être facilement programmable. Cette invention tient compte du fait de pouvoir continuer à utiliser des programmes existants du CPU, ainsi que de la compatibilité de code et l'intégration aisée du VPU dans les programmes existants.
PCT/EP2002/010084 2001-09-03 2002-09-09 Systeme reconfigurable WO2003025770A2 (fr)

Priority Applications (26)

Application Number Priority Date Filing Date Title
EP02779326A EP1449109A2 (fr) 2001-09-07 2002-09-09 Systeme reconfigurable
AU2002342668A AU2002342668A1 (en) 2001-09-07 2002-09-09 Reconfigurable system
US10/487,681 US7577822B2 (en) 2001-12-14 2002-09-09 Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
AU2002338729A AU2002338729A1 (en) 2001-09-19 2002-09-18 Router
PCT/EP2002/010479 WO2003025781A2 (fr) 2001-09-19 2002-09-18 Routeur
AT02791644T ATE533111T1 (de) 2001-09-19 2002-09-19 Rekonfigurierbare elemente
AU2002357982A AU2002357982A1 (en) 2001-09-19 2002-09-19 Reconfigurable elements
PCT/EP2002/010572 WO2003036507A2 (fr) 2001-09-19 2002-09-19 Elements reconfigurables
JP2003538928A JP4456864B2 (ja) 2001-09-19 2002-09-19 リコンフィギュアブル素子
EP02791644A EP1472616B8 (fr) 2001-09-19 2002-09-19 Elements reconfigurables
US10/490,081 US8429385B2 (en) 2001-09-03 2002-09-19 Device including a field having function cells and information providing cells controlled by the function cells
AU2003286131A AU2003286131A1 (en) 2002-08-07 2003-07-23 Method and device for processing data
PCT/EP2003/008081 WO2004021176A2 (fr) 2002-08-07 2003-07-23 Procede et dispositif de traitement de donnees
EP03776856.1A EP1537501B1 (fr) 2002-08-07 2003-07-23 Procede et dispositif de traitement de donnees
JP2005506110A JP2005535055A (ja) 2002-08-07 2003-07-24 データ処理方法およびデータ処理装置
US10/523,764 US8156284B2 (en) 2002-08-07 2003-07-24 Data processing method and device
PCT/EP2003/008080 WO2004015568A2 (fr) 2002-08-07 2003-07-24 Procede et dispositif de traitement de donnees
EP03784053A EP1535190B1 (fr) 2002-08-07 2003-07-24 Procédé d'exploiter simultanément un processeur séquentiel et un réseau reconfigurable
AU2003260323A AU2003260323A1 (en) 2002-08-07 2003-07-24 Data processing method and device
US12/247,076 US8209653B2 (en) 2001-09-03 2008-10-07 Router
US12/570,943 US8914590B2 (en) 2002-08-07 2009-09-30 Data processing method and device
US12/621,860 US8281265B2 (en) 2002-08-07 2009-11-19 Method and device for processing data
JP2009271120A JP2010079923A (ja) 2001-09-19 2009-11-30 処理チップ、チップを含むシステム、マルチプロセッサ装置およびマルチコアプロセッサ装置
US12/947,167 US20110238948A1 (en) 2002-08-07 2010-11-16 Method and device for coupling a data processing unit and a data processing array
US13/023,796 US8686475B2 (en) 2001-09-19 2011-02-09 Reconfigurable elements
US14/923,702 US10579584B2 (en) 2002-03-21 2015-10-27 Integrated data processing core and array data processor and method for processing algorithms

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US31787601P 2001-09-07 2001-09-07
US60/317,876 2001-09-07
EP01129923.7 2001-12-14
EP01129923 2001-12-14
DE10206856 2002-02-18
DE10206856.9 2002-02-18

Publications (2)

Publication Number Publication Date
WO2003025770A2 true WO2003025770A2 (fr) 2003-03-27
WO2003025770A3 WO2003025770A3 (fr) 2004-02-26

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EP (1) EP1449109A2 (fr)
AU (1) AU2002342668A1 (fr)
WO (1) WO2003025770A2 (fr)

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Publication number Priority date Publication date Assignee Title
EP2043000A2 (fr) 2002-02-18 2009-04-01 PACT XPP Technologies AG Systèmes de bus et procédé de reconfiguration

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AU2002342668A1 (en) 2003-04-01
WO2003025770A3 (fr) 2004-02-26

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