WO2003025737A1 - Appareil d'exploitation et systeme d'exploitation - Google Patents

Appareil d'exploitation et systeme d'exploitation Download PDF

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Publication number
WO2003025737A1
WO2003025737A1 PCT/JP2002/008681 JP0208681W WO03025737A1 WO 2003025737 A1 WO2003025737 A1 WO 2003025737A1 JP 0208681 W JP0208681 W JP 0208681W WO 03025737 A1 WO03025737 A1 WO 03025737A1
Authority
WO
WIPO (PCT)
Prior art keywords
outputting
inputs
result
input
predetermined
Prior art date
Application number
PCT/JP2002/008681
Other languages
English (en)
French (fr)
Inventor
Takatoshi Nakamura
Akihiro Yokota
Original Assignee
Nti, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nti, Inc. filed Critical Nti, Inc.
Priority to EP02760770A priority Critical patent/EP1467279A4/en
Priority to US10/505,681 priority patent/US20060064449A1/en
Publication of WO2003025737A1 publication Critical patent/WO2003025737A1/ja

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Control Of Multiple Motors (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
PCT/JP2002/008681 2001-08-29 2002-08-28 Appareil d'exploitation et systeme d'exploitation WO2003025737A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP02760770A EP1467279A4 (en) 2001-08-29 2002-08-28 OPERATING APPARATUS AND OPERATING SYSTEM
US10/505,681 US20060064449A1 (en) 2001-08-29 2002-08-28 Operation apparatus and operation system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-259644 2001-08-29
JP2001259644A JP3548142B2 (ja) 2001-08-29 2001-08-29 演算装置及び演算システム

Publications (1)

Publication Number Publication Date
WO2003025737A1 true WO2003025737A1 (fr) 2003-03-27

Family

ID=19086985

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/008681 WO2003025737A1 (fr) 2001-08-29 2002-08-28 Appareil d'exploitation et systeme d'exploitation

Country Status (5)

Country Link
US (1) US20060064449A1 (ja)
EP (1) EP1467279A4 (ja)
JP (1) JP3548142B2 (ja)
TW (1) TWI238351B (ja)
WO (1) WO2003025737A1 (ja)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7860915B2 (en) 2003-12-29 2010-12-28 Xilinx, Inc. Digital signal processing circuit having a pattern circuit for determining termination conditions
US7840627B2 (en) * 2003-12-29 2010-11-23 Xilinx, Inc. Digital signal processing circuit having input register blocks
US7849119B2 (en) * 2003-12-29 2010-12-07 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit
US7853636B2 (en) * 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit for convergent rounding
US7882165B2 (en) 2003-12-29 2011-02-01 Xilinx, Inc. Digital signal processing element having an arithmetic logic unit
US7844653B2 (en) * 2003-12-29 2010-11-30 Xilinx, Inc. Digital signal processing circuit having a pre-adder circuit
US7853632B2 (en) * 2003-12-29 2010-12-14 Xilinx, Inc. Architectural floorplan for a digital signal processing circuit
US7853634B2 (en) * 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a SIMD circuit
US7870182B2 (en) * 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US7865542B2 (en) 2003-12-29 2011-01-04 Xilinx, Inc. Digital signal processing block having a wide multiplexer
US7840630B2 (en) * 2003-12-29 2010-11-23 Xilinx, Inc. Arithmetic logic unit circuit
US20050216517A1 (en) * 2004-03-24 2005-09-29 Calpont Corporation Graph processor for a hardware database management system
US8479133B2 (en) * 2009-01-27 2013-07-02 Xilinx, Inc. Method of and circuit for implementing a filter in an integrated circuit
US8543635B2 (en) * 2009-01-27 2013-09-24 Xilinx, Inc. Digital signal processing block with preadder stage

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450557A (en) 1989-11-07 1995-09-12 Loral Aerospace Corp. Single-chip self-configurable parallel processor
JPH08106375A (ja) * 1994-10-03 1996-04-23 Ricoh Co Ltd 信号処理演算器
JPH1124890A (ja) * 1997-07-09 1999-01-29 Matsushita Electric Ind Co Ltd プログラマブル演算回路および装置
JPH11232079A (ja) * 1998-02-16 1999-08-27 Fuji Xerox Co Ltd 情報処理システム

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4967340A (en) * 1985-06-12 1990-10-30 E-Systems, Inc. Adaptive processing system having an array of individually configurable processing components
US4760544A (en) * 1986-06-20 1988-07-26 Plessey Overseas Limited Arithmetic logic and shift device
KR0142803B1 (ko) * 1993-09-02 1998-07-15 모리시다 요이치 신호처리장치
US6112288A (en) * 1998-05-19 2000-08-29 Paracel, Inc. Dynamic configurable system of parallel modules comprising chain of chips comprising parallel pipeline chain of processors with master controller feeding command and data
EP1059580A1 (de) * 1999-06-10 2000-12-13 Siemens Aktiengesellschaft Programmgesteuerte Einheit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450557A (en) 1989-11-07 1995-09-12 Loral Aerospace Corp. Single-chip self-configurable parallel processor
JPH08106375A (ja) * 1994-10-03 1996-04-23 Ricoh Co Ltd 信号処理演算器
JPH1124890A (ja) * 1997-07-09 1999-01-29 Matsushita Electric Ind Co Ltd プログラマブル演算回路および装置
JPH11232079A (ja) * 1998-02-16 1999-08-27 Fuji Xerox Co Ltd 情報処理システム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1467279A4

Also Published As

Publication number Publication date
JP3548142B2 (ja) 2004-07-28
TWI238351B (en) 2005-08-21
EP1467279A4 (en) 2007-03-21
US20060064449A1 (en) 2006-03-23
JP2003067180A (ja) 2003-03-07
EP1467279A1 (en) 2004-10-13

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