WO2003012985A2

WO2003012985A2 - Method and apparatus for analog multipliers employed in analog filtering system

Info

Publication number: WO2003012985A2
Application number: PCT/US2002/024093
Authority: WO
Inventors: Peter Capofreddi
Original assignee: Santel Networks, Inc.
Priority date: 2001-08-01
Filing date: 2002-07-29
Publication date: 2003-02-13
Also published as: AU2002324560A1; WO2003012985A3

Abstract

An analog multiplier multiplying one analog signal factor with one coefficient factor by decomposing the coefficient factor into a sign signal and a magnitude signal is disclosed.

Description

METHOD AND APPARATUS FOR ANALOG MULTIPLIERS EMPLOYED IN ANALOG FILTERING SYSTEMS

BACKGROUND

1. FIELD OF THE INVENTION

[0001] The invention relates generally to signal processing. More specifically, the invention relates to the implementation of analog multiplier circuits employed in analog filtering and signal processing.

2. RELATED ART

[0002] The art of filtering as applied to signal processing involves modifying an input signal or signals in order to derive a desired response, such as extracting particular features of a signal. There are two well-known types of filtering: digital and analog. In systems processing signals with very high bandwidth, such as those employed optical networking, analog filtering is often more desirable from a cost/complexity standpoint than digital filtering. Furthermore, there are applications where analog filtering may be the only viable method for performing the needed signal processing functions. More specific examples of high-bandwidth signals that may require analog filtering include disk drive read channels, radio communication channels, certain wireline communication channels and fiber-optic communication channels. Some types of filtering that are performed on such signals include channel response equalization and channel phase compensation.

[0003] Filtering is often accomplished by multiplying one or more inputs by coefficients and then summing the products. In most applications, the filter characteristics (which are defined in order achieve a desired response), such as the filter coefficients or type of mathematical transform employed, need to be programmable. This programmability is accomplished in analog filters through the use of analog multiplier circuits. A programmable analog filter typically comprises two or more analog multiplier circuits. The performance of the analog multiplier circuits is in some cases the primary factor limiting the overall performance of the filter.

[0004] An analog multiplier circuit multiplies two "factors", at least one of which is represented by an analog input. The implementation of analog multipliers used in filters differ from those of the analog multipliers used in other applications such as instrumentation circuits and radio mixers due to the difference in dynamic characteristics of the factors used therein. Analog multipliers used in instrumentation systems typically have two low frequency factors while analog multipliers used for mixing signals in radio systems typically have two high frequency factors. Analog multipliers used in analog filters typically have one high frequency factor, referred to as the "signal" factor, and one constant or slowly changing factor, referred to as the "coefficient" factor.

[0005] Conventional analog multiplier circuits suitable for use in analog filters can be broadly classified into two categories based on the form in which the coefficient factor is represented. In one these categories, in for instance a "Gilbert-Cell" multiplier, the coefficient factor is represented by an analog input. In the second category, for instance in the multiplying used in digital-to-analog converters, the coefficient factor is represented by a digital input.

[0006] Figure 1(a) illustrates a conventional Gilbert-Cell multiplier 100. Multiplier 100 determines the product of one high-frequency signal factor, represented by analog input voltage V_ΓNI, and one constant or slowly changing coefficient factor, represented by analog input voltage V_IN2 The product of V_ΓNI and V_{Γ 2} is represented by a current, designated as I_OUT. The inputs and outputs to the multiplier 100 are differential in nature. The V_INI factor is the difference of two voltage inputs designated as V_ΓNIP and V_ININ- Similarly, the V_ΓN2 factor is the difference of two voltage inputs designated as VΓN₂P and VΓN N- The product I_OU_T is the difference of two current outputs designated as I_OU_T and I_OUTN-

[0007] The operation of Gilbert-Cell multiplier 100 is well-known in the art of analog circuitry but will be summarized for convenience as follows. Transistors 101 and 102 in collaboration with resistors 103 and 104 and a current source 105 (shown and described below with respect to Figure 1(b)) together form a "transconductance" cell. In general, a transconductance cell is a mechanism which converts a voltage signal to a current signal providing a signal gain in units of current divided by voltage. The transconductance cell shown in Figure 1(a) converts differential input voltage signal Vnvii, into a proportional differential current signal Iχ (not shown). Differential current Iχ is the difference of the currents designated as Iχp and I_TN in Figure 1(a). The differential pair comprising transistors 106 and 107 divides I_TN into two current paths, where the fraction of the current that goes into each path is a function of the coefficient input V_ΓN2. Similarly, the differential transistor pair comprising transistors 108 and 109 divides current I_TP into two current paths, where the fraction of the current that goes into each path is the same as the corresponding fraction in the pair comprising transistors 106 and 107.

[0008] In order that the fraction of current I_TP passing through transistor 107 (and also the fraction of current I_TP passing through transistor 109) be proportional to the coefficient factor VΓ_N2,V_ΠM2 is first be passed through a predistortion circuit 110. The transistor pairs 106/107 and 108/109 have a non-linear characteristic, given by the following relation:

Ii06 - 1107 = IτN*tanh ( (VXP-VXN) /V_T),

where I₁₀₆ and I₁₀ are collector currents through transistors 106 and 107, respectively, and V_XP and V_X are outputs at the terminals of the predistortion circuit 110 and tanh is the hyperbolic tangent function. The above assumes that the transistors are large enough such that the base and emitter parasitic resistances are small. For instance, transistor sizes of 10 micros by 0.5 microns would make this approximation accurate. The predistortion circuit 110 compensates for the nonlinear characteristic of the differential pairs 106/107 and 108/109 by approximating the inverse of this characteristic. Predistortion circuit 110 has a transfer function that approximates the inverse hyperbolic tangent function which is of the form f (x)

= ln(x + vx² + 1 j. Accordingly, predistortion circuit 110 can be designed to generate the following inverse characteristic:

Vxp - VXN = V_τ*arctanh [ - VI_N2N) / (RPRE*IPRE)],

where arctanh is the inverse hyperbolic tangent function, and R_PRE and I_PRE are parameter values of the predistortion circuit described below. An exemplary implementation of predistortion circuit 110 is shown and described with respect to Figure 1(c) below. Considering an analysis of the entire multiplier 100, it can be readily shown and observed that the output current of multiplier 100 can be expressed as the following function of the input voltages:

IOUT ⁼ IOUTP-IOUTN = [ (VΓNIP - ^IN) * (Vp^p - VΓ 2N)] / [RPRE*IPRE*R]_>

where R_PRE and I_PRE are parameter values of the predistortion circuit and R is the resistance of each of the resisters 103 and 104. [0009] Figure 1(b) illustrates an exemplary implementation of the current source 105 in Gilbert-Cell multiplier 100 of Figure 1(a). This implementation of current source 105 provides an approximately constant current I modeled by I = (V_BIAS - V_BE) /R_B, where VBE is the voltage drop across the base to emitter junction of transistor 121, and R_B is the resistance of resistor 122. The bias voltage V_BIAS is generated by a bias generator circuit (not shown) which is well-known in the art.

[00010] Figure 1(c) illustrates an exemplary implementation of predistortion circuit 110 in Gilbert-Cell multiplier 100 of Figure 1(a). Transistors 131 and 132 in collaboration with resistors 133 and 134 and current source 135 form a transconductance cell that converts differential input voltage signal V_ΓN into a proportional differential current signal I_PP-I_PN according to

IPP - IPN = (VINP - VΓN ) /RPRE

where R _RE is the resistance of each of resistors 133 and 134. Currents I p and I_P are connected to diode-connected transistors 136 and 137. Considering an analysis of the circuit of Figure 1(c), it can be shown that transistors 136 and 137 generate a differential voltage V_OU_TP - V_OUTN proportional to the inverse hyperbolic tangent (equation discussed above) of the differential input signal V_ΓN_P - V_INN divided by the total voltage drop on resistors 133 and 134, RpRE*IpRE.

[00011] The multiplier circuit 100 of Figure 1(a) exhibits several significant non- ideal characteristics that seriously limit the performance of filters that incorporate it. First, multiplier circuit 100 generates a significant amount of noise, even when the value of the coefficient factor V_IN2 is zero or close to zero.^' This is significant in analog filters that incorporate a large number of Gilbert-cell multipliers because the noise generated by each multiplier is passed to the filter output unattenuated. Also, the effect of noise generated by a given multiplier (and consequently, the whole set of multipliers) is proportional to the bandwidth of the system, and is therefore more significant in higher bandwidth systems. Second, multiplier circuit 100 is very sensitive to offsets in transistors 106, 107, 108 and 109. Offsets in these transistors can cause the output current to differ from its ideal value and thus introduce errors that limit the performance of filters or other circuits incorporating this type of multiplier. The sensitivity to offset is greatest when the coefficient factor represented by VΓN2_> represented by VIN2P -VΠM2N, is close to zero. [00012] Designs other than Gilbert-Cell multipliers have their own disadvantages as well. For instance, a "multiplying" digital-to-analog converter circuit uses a pair of current steering transistors and a pair of control transistors for every digital bit in the coefficient factor. Depending on the resolution desired in the coefficient, this may lead to a very large number of transistors. For instance, if eight bits are desired for representing the coefficient, then more than 32 transistors would be required in order to implement the multiplying circuit. Because the circuit is digitally controlled, there may not be the same level or type of noise as that of the Gilbert-Cell multiplier.

[00013] Although the multiplying digital-to-analog converter overcomes some of the disadvantages of the Gilbert-Cell multiplier 100, it also suffer from several significant disadvantages. First, the number of transistors required by the multiplying digital-to-analog converter circuit is much larger than that required by the Gilbert-Cell multiplier to achieve a comparable level of resolution. The additional transistors require additional die area, which results in reduced yield. This yield reduction is particularly significant is advanced compound semiconductor integrated circuit technologies (e.g. Silicon-Germanium), which are not able to attain the same levels of integration as simple silicon technologies. Since advanced compound semiconductor technologies are often used for applications with signal frequencies above 5 Gigahertz, certain high-bandwidth communications systems will suffer these added costs if using multiplying digital-to-analog converters. Additionally, as a result of the large number of transistors connected to the outputs, the parasitic capacitance associated with the outputs becomes large. This large parasitic capacitance limits the frequency of operation of the circuit, and hence makes it unsuitable for high frequency applications.

[00014] Therefore, there is a need for an improved analog multiplier that can be used in high frequency and/or high bandwidth applications which does not suffer from the cost, complexity and inaccuracies of conventional multipliers.

3. SUMMARY

[00015] The invention consists of enabling an analog multiplier to programmably controlled. The programmability of the multiplier is implemented by separating out the sign and magnitude components of one of the factors being multiplied. The sign component is used to control the polarity of the output of the multiplier, while the magnitude component allows steering of current through the multiplier such that zero factors being multiplied are more effectively represented than in conventional multipliers. The multiplier of the invention uses both digital and analog signals to control the current flow within.

[00016] In one embodiment, the multipliers can be utilized to implement an analog filter, and in another embodiment, the analog filter can be used in a communications system which utilizes a feedback mechanism to control the coefficients being multiplied.

4. BRIEF DESCRIPTION OF THE DRAWINGS

[00017] Figure 1(a) illustrates a conventional Gilbert-Cell multiplier 100.

[00018] Figure 1(b) illustrates an exemplary implementation of the current source 105 in Gilbert-Cell multiplier 100 of Figure 1 (a) .

[00019] Figure 1(c) illustrates an exemplary implementation of predistortion circuit 110 in Gilbert-Cell multiplier 100 of Figure 1(a) .

[00020] Figure 2 illustrates an analog multiplier circuit in accordance with at least one embodiment of the invention.

[00021] Figure 3 illustrates an exemplary Discrete-Time Finite Impulse Response

(FIR) filter implemented using one or more embodiments of the invention.

[00022] Figure 4 illustrates an exemplary Discrete-Time Finite Impulse Response (FIR) filter implemented using one or more embodiments of the invention.

[00023] Figure 5 shows a communication system incorporating a programmable filter according to one or more embodiments of the invention.

[00024] Figure 6 illustrates an adaptation controller circuit including separation of sign and magnitude controls.

5. DETAILED DESCRIPTION OF THE INVENTION

[00025] In brief, the invention consists of a multiplier implemented by considering independently the sign and magnitude components of the second of two factors (i.e. the coefficient factor) to be multiplied. The sign and magnitude of the coefficient factor are generated by a control circuit and fed to an improved multiplier circuit. In one embodiment, the sign input is a digital signal while the magnitude input is an analog signal. The control circuit can be implemented in either digital or analog, and if implemented digitally, a digital- to-analog converter would additionally be needed to generate the analog magnitude control voltage.

[00026] Decomposing and then using the sign and magnitude components to represent the coefficient factor results in several significant advantages as compared with the conventional Gilbert-Cell multiplier 100 shown in Figure 1(a). First, when the coefficient is near zero, its magnitude will be small. Under this condition, most of the resulting current (see below) can be diverted out of the improved multiplier so that it does not affect the output product. Most of the noise associate with this current will therefore also be diverted out of the improved multiplier, and thus will have no effect on the improved multiplier's performance. Further, in comparison to multiplying digital-to-analog converters there are far fewer transistors and less parasitic capacitance.

[00027] Figure 2 illustrates an analog multiplier circuit in accordance with at least one embodiment of the invention. Multiplier 200 generates a product output of two input factors Fj and F₂. The first input factor Fi is the differential analog voltage V_ΓNI = V^p - V_ININ In filtering applications, V_INI represents the signal factor (high frequency factor). The second input factor, F₂, to multiplier 200 is decomposed into its magnitude and sign components. In filtering applications, the sign and magnitude components of factor F₂ together represent the coefficient factor (low frequency factor). The sign component of factor F₂ is represented by a digital input, which exhibits a "high" value if F₂ is positive and a "low" value if F₂ is negative. In the embodiment shown in Figure 2, the sign component is a differential digital input SIGN_P-SIGN_N- The magnitude component of factor F₂ is- represented by an analog signal. In the embodiment shown in Figure 2, the magnitude component is represented by a differential analog voltage MAG_P-MAG_N- Multiplier 200 generates a product output of Fi and F₂ which is represented by a difference between two current signals IOUTP and I_OUTN-

[00028] Transistors 201 and 202 in collaboration with resistors 203 and 204 and current source 205 form a transconductance cell that converts differential input voltage signal VΓ_NI into a proportional differential current signal I_T = I_TP-I_TN- The differential current I generated by the transconductance cell is governed approximately by:

where g_m is the transconductance or gain due to the cell. The transconductance g_m can be expressed approximately as:

g_m = l/(R_M + V_T/lM), (2)

where R is the resistance of each of the resistors 203 and 204, V_T = k*T/q is the thermal voltage, and I_m is the current generated by current source 205. In order to maintain the linearity of the transconductance cell, the resistance R_M should be much greater than the V_T/I_M term. Another transform multiplier 200 undertakes involves a predistortion circuit 210. The predistortion circuit 210 compensates for any nonlinear characteristics of the differential voltage pair MAG_P-MAG_N and has a transfer function approximating the inverse hyperbolic tangent function (given above). The output of the pre-distortion circuit 210 is an intermediate differential voltage pair Vχp-Vχ_N. The relationship between the input and output of predistortion circuit 210 is, approximately:

1 + (MAG - MAG_N)/V_PRE

Vχ_P - V = V_τ * In — ^p- ^{N PRE} , (3)

^XP ™ ^τ 1 -(MAG_P - MAG_N)/V_PRE

where "In" is the natural logarithmic function, V_T is the thermal voltage (given by Vτ=k*T/q, where k is the Boltzmann's constant, T is the absolute temperature and q is the electron charge) and VPRE = RPRE*I_PRE is a voltage determined by the specific component parameters in the predistortion circuit 210, discussed with reference to Figure 1 (c) above.

[00029] The currents, I_TN and I_TP can be expressed in terms of I_M of the current source 205 and resistance R_M by:

I_Tp = IM + (VΓNIP-VΓNIN) /RM, and

ITN ⁼ IM - (VrNip-Vr m) / (4)

The differential pair comprising transistors 206 and 207 divides current I_TP into two current paths, where the fraction of the current that goes into each path is controlled by the intermediate differential voltage V_XP-V_XN. Similarly, the differential transistor pair comprising transistors 208 and 209 divides current I_TN into two current paths under the control of intermediate differential voltage Vχp-Vχ». The fraction of current I_TP that goes into transistor 206 is the same as the fraction of current I_TN that goes into transistor 208. This fraction Δ is given approximately by:

^{Δ =} _{1 + e}(Vχ_P - V_XN)/V_τ ' (⁵)

where "e" denotes the natural exponential function and V_T denotes the thermal voltage (k*T/q) in the transistor pairs. Thus, the collector current from transistor 206 (I₂₀₆) is given by:

I₂₀₆ = Δ*I_Tp (6)

Likewise, the collector current from transistor 208 (l₂₀₈) is given by:

I₂₀₈ = Δ*I™ (7)

[00030] Simple substitution of the equations (4) and (5) above shows that the fraction Δ of current I_TP that goes into transistor 206 (and equivalently the fraction of current I_TN that goes into transistor 208) is given by

Λ = 1

, V_PRE - (MAG_P - MAG_N) ^* (8)

V_PRE + (MAGP - MAGN)

Further reduction yields:

[00031] Thus, although the relationship of Δ to Vχp-Vχ_N is nonlinear, the addition of the predistortion circuit compensates for this nonlinearity and makes the relationship of Δ to MAG_P-MAG_N linear. Combining equations (9) and (4) with (6) and (7)gives for currents I₂₀₆ and l₂₀₈:

As a differential pair, hence:

, _ _τ _ _? . VΓNIP ^~ V«IN * VpRE + (MAG_P - MAG_N)

¹206 ^X208 ^"~ p ? * V

^KM ^ ^VPRE

! _ τ ₌ ^V^IP ^{~ V} .N * pRE + (MAG_P - MAG_N)

206 208 T^ -T T ^* *_* /

^^■M PRE

[00032] The portion of current I_TP flowing through transistor 207 and the portion of current I_TN flowing through transistor 209 are discarded into a DUMP node 250. When the coefficient factor is near zero, its magnitude will be small, and the MAG_P-MAG_N input will be negative (biased toward MAG_N being higher than MAGp). Under this condition, most of the current I_TP and most of the current I_TN will be steered into the DUMP node since transistors 207 and 209, respectively, will be active. This has the effect of multiplying zero coefficient factors with much greater accuracy.

[00033] The transistor pairs 211/212 and 213/214 are not greatly affected by offsets and thus can be small, and do not need a common centroid layout. The inputs SIGNp and SIGN_N, which represent the sign of the coefficient factor, control the switching of transistor pairs 211/212 and 213/214. When SIGN_P-SIGN_N is positive (i.e. the coefficient factor has a positive sign) transistors 211 and 214 switch on (become active) and transistors 212 and 213 remain or are switched off. When SIGN_P-SIGN_N is negative (i.e. the coefficient factor has a negative sign) transistors 211 and 213 switch on (become active) and transistors 211 and 214 remain or are switched off. The signal SIGN_P-SIGN_N switches the polarity of the output current I_OU_T and thus, controls the sign accorded to the output current. The output current is given by:

lour = _" I_OUT = ^ ^" ^ * ^V∞ + ( AG_P - MAG_N) , _{sgn (SIGNp} _ ^

^• -M ^VPRE where sgn denotes the signum function, taking a value of +1 when its argument is positive, and -1 when its operand is negative.

[00034] Figure 3 illustrates an exemplary Discrete-Time Finite Impulse Response (FIR) filter implemented using one or more embodiments of the invention. FIR filter 300 is an analog filter which is programmable, as will be described below. FIR filter 300 receives a differential input voltage signal VΓ_NN-V_ΓNP, which would represent the first, or signal factor in a signal processing system. Filter 300 utilizes for its taps a series of nine improved multipliers 301, 302 ... 308 and 309, which are similar in configuration and operation to that described with respect to Figure 2. For convenience, five other improved multipliers within the series are not depicted but operate in a similar manner to those described and shown. Likewise, a series of eight delay elements 322 ... 328, 329 are utilized to provide time- delayed input samples in a pipeline to various ones of the improved multipliers. For convenience, five of the eight delay elements are not depicted but operate in a similar manner to those described and shown.

[00035] The operation of filter 300 can be described as follows. Filter 300 employs the series of delay elements 322 ... 329 to generate a sequence of delayed versions of the differential input signal VΓN_P-V_ΓNN- Filter 300 employs the improved multipliers 301, 302, ... 309 to generate currents proportional to the delayed versions of the input signal. The currents generated by improved multipliers 301, 302, ... 309 are tied to differential output nodes I_OUTP and I_OUTN- The differential output current I_OUTP-I_OUTN is equal to the sum of the differential multiplier output currents by virtue of Kirchoff s current law. A summation circuit 321 wires together each of the output currents of improved multipliers 301, 302...309. Hence,

309

^OUTP ^_ OUTN ⁼ 2_^1 i ' j=301

where I_j is the output current of each improved multiplier j.

[00036] Each filter tap, i.e. coefficient , is decomposed into its magnitude M, and sign Sj components. The sign of each bit is represented by the differential signal (S_JP-S_JN), while the magnitude Mi is represented by the differential signal (M_JP-M_JN). In the filter 300, "i" ranges from 1 to 9, such that there are nine (9) filter taps C ... C₉ and consequently, nine sets of sign and magnitude component differential signals. For instance, a first tap Ci has a sign component (Sjp-Sm) and a magnitude component (M_JP-M_JN) which are input to the first improved multiplier 301.

[00037] The digital sign input and the analog magnitude input of each coefficient are generated by a control circuit. A typical example of a control circuit is a field- programmable gate array integrated circuit (FPGA IC) in which an adaptive algorithm is implemented for controlling the filter to achieve a desired response. The control circuit can be implemented in either digital or analog, and if implemented digitally, a digital-to-analog converter would additionally be needed to generate the analog magnitude control voltage.

[00038] Ideally, the differential output current should be given by:

IOUTP - IOUTN = k* (VΓNP-VΓN ) * (Ci + C2Z ¹ + C₃z ² + ... + C₃z^"2)

where z^"1 represents the delay provided by the delay elements 322 ... 329. For each filter tap Cj, the signal SJ_P-S_JN will be high if the sign of is positive and low if the sign of is negative. For each filter tap Cj, the signal M_JP-M_JN will be determined from the magnitude of the coefficient Cj as follows:

M_ip - M_iN = (abs (Ci) -l) * V_PRE

where "abs" is the absolute value function and V_PRE is a voltage internally generated by the predistortion circuits of the improved multipliers (see above). The coefficients are scaled by the algorithm in the control circuit such that they are less than one in magnitude.

[00039] Figure 4 illustrates an exemplary Discrete-Time Finite Impulse Response (FIR) filter implemented using one or more embodiments of the invention. FIR filter 400 is. an analog filter which is programmable, as will be described below. FIR filter 400 receives a differential input voltage signal VΓ_NN-V_ΓNP, which would represent the first, or signal factor in a signal processing system. Filter 400 utilizes for its taps a series of nine improved multipliers 401, 402 .... 408 and 409, which are similar in configuration and operation to that described with respect to Figure 2. For convenience, five other improved multipliers within the series are not depicted but operate in a similar manner to those described and shown. Likewise, a series of eight delay elements 422 ... 428, 429 are utilized to provide time- delayed input samples in a pipeline to various ones of the improved multipliers. For convenience, five of the eight delay elements are not depicted but operate in a similar manner to those described and shown.

[00040] The improved multipliers 401, 402 ... 408, 409 correspond to improved multipliers 301, 302 ... 308, 309 of Figure 3 and are similar in operation. Likewise, the delay elements 422 ... 428, 429 and the summation circuit (also referred to as summing nodes) 421 correspond to delay elements 322 ... 328, 329 and the summation circuit 321 of Figure 3. The operation of filter 400 is similar to the operation of filter 300 depicted in Figure 3 and described above as regards the differential output current I_OUTP-I_OUT_N-

[00041] The cascoded transresistance amplifier comprising transistors 451 and 452 and resistors 453 and 454 converts the differential current I_OU_TP-I_OU_TN to a differential voltage V_OU_TP-V_OUTN. Cascode transistors 451 and 452 are necessary to reduce the voltage swing on current summing nodes 421. These nodes have a large amount of parasitic capacitance due to the large number of multipliers connected to them. Isolating these nodes from the output node therefore improves the response time of the filter. Vcc is the positive supply voltage while Vcsc is a fixed reference voltage generated by a bias circuit (not shown). The differential output voltage is given by:

409

* OUTP^— VouTN ⁼ OUTP ^— IOUTN ⁼ 2-_ι i j=401

₌ * sgnCSIGN_j) .

[00042] Figure 5 shows a communication system incorporating a programmable filter according to one or more embodiments of the invention. Communication system 500 shows both the transmission and reception sub-systems, as well as the actual channel 520 linking the two. A digital bit sequence 505 is fed in to a channel transmitter 510 which encodes the bit sequence 505 into a signal suitable for transmission on the channel medium. The channel transmitter transmits encoded symbols as either analog or digital signals and places them on channel 520. Channel 520 may be a wireline medium (such as fiber or copper) or wireless medium (such as air), depending upon the nature of the system 500. A channel receiver 530 which is also coupled to the channel 520 detects and receives the transmitted signals. [00043] Channel receiver 530 generates an analog received signal which is then applied to a programmable filter 540. Programmable filter 540 helps extract certain signal features such that they can be decoded into symbols in order to reconstruct the original digital bit sequence 505. Examples of filter 540 are filters 300 and 400 of Figures 3 and 4, respectively. Filter 540 receives sign and magnitude component inputs of the coefficient factors from an adaptation controller 570. The coefficient factors are used to multiply delayed inputs at taps within the filter 540. The coefficients of the taps within filter 540 are programmed by way of a feedback mechanism labeled "eye quality monitor" 560. The eye quality monitor 560 is a mixed signal integrated circuit which determines the error in encoding the signal generated by filter 540 into a valid digital bit sequence. The measure of error is sent from eye quality monitor 560 to adaptation controller 570. Adaptation controller 570 uses the measured error to modify the coefficient factors as needed, and thus "programs" the filter 540. The output of the programmable filter 540 at one cycle is fed to the eye quality monitor 560 to measure its error.

[00044] In accordance with the invention, the coefficient factors are separated into sign and magnitude components by a control circuit which can be integrated or contained in adaptation controller 570. Also, the programmable filter 540 uses improved multipliers such as multiplier 200 depicted in Figure 2 that accept separated sign and magnitude components. The use of separated sign and magnitude components in the improved multipliers aids the filter 540 in producing more accurate results, especially where communication system 500 is operating at high frequencies. Each improved multiplier (and thus filter 540 itself) uses fewer transistors than certain types of conventional multipliers and hence, exhibits less parasitic capacitance, which can also degrade the performance of the system 500, especially at higher frequencies.

[00045] A clock/data recovery circuit 550 decodes the symbols extracted from the signals processed by filter 540. The result is a sequence of digital output bits 555. The accuracy of the filter 540 is enhanced by the use of the improved multiplier with separated sign and magnitude coefficient components. The decoded sequence 555 will therefore more often exactly match the digital bit sequence 505 that was transmitted ever the channel 520. The error rate between bits of the sequence 555 and the sequence 505 would effectively be lower using the improved multiplier than using a conventional multiplier. [00046] Figure 6 illustrates an adaptation controller circuit including separation of sign and magnitude controls. The adaptation controller 630 can be built, for instance, using one or more field-programmable gate arrays (FPGAs). The controller 630 includes control circuitry that generates separate signals for the sign and magnitude components of the coefficients going to the programmable filter. The error signal is sent from the eye quality monitor (see Figure 5) to the core 635 of the controller 630. The core contains all of the basic programmable logic elements that generate and adapt the coefficients. In a typical embodiment, the core implements the least mean square (LMS) algorithm or another algorithm that adaptively matches the filter characteristics to those of the channel. The core has logic to generate, for each filter coefficient to be programmed, a sequence of bits representing both the sign and magnitude of the coefficient. For instance, if 8-bit precision signed numbers need to be produced, this may be represented by core 635 as a sequence of 9 bits would be generated, 8 for the magnitude and 1 for the sign of the number. The sign bit, which is represented digitally can be directly output to the programmable filter. The 8 bits of the magnitude needs to be converted from digital to analog and is thus passed through a D/A converter. The input to the D/A converter is either: the lower 8 bits of coefficient, as-is, if the coefficient is positive, or the lower eight bits of the coefficient negated, if the coefficient is negative. Negation is accomplished by complementing all the bits and then adding one. The negation generates the absolute value in the case that the coefficient is negative.

[00047] Controller 630 shows an exemplary two coefficient configuration. Each coefficient emerges from the core as a sequence of 9 bits. The first sequence of 9 bits, representing the first of two depicted coefficients, has the leading sign bit split off from the 8 bits representing the magnitude. The 8 bits representing the magnitude of the first coefficient are sent both to a MUX (multiplexer) 632 and to a negater 631. MUX 632 is a two-to-one MUX, selecting one output from among two inputs. The first input to the MUX 632 is the 8- bit magnitude output of the controller core 635 and the second is the output of negates 631 which is the negative of the output of the controller core 635. The sign bit acts as the selector control for the MUX 632. If the sign bit is a 1, indicating a positive coefficient, then MUX 632 selects the output of the controller core 635. If the sign bit is 0 indicating a negative coefficient, then MUX 632 selects the output of negates 631 which is the negative of the output of core 635. The result is the absolute value (magnitude) of the coefficient. The second coefficient is processed in the same way. Third and additional coefficients (not shown) that would be present in a typical embodiment are processed in the same way. [00048] Although the present invention has been described in detail with reference to the disclosed embodiments thereof, those skilled in the art will appreciate that various substitutions and modifications can be made to the examples described herein while remaining within the spirit and scope of the invention as defined in the appended claims.

Claims

CLAIMSWhat is claimed is:

1. A method for multiplying a coefficient factor with a signal factor comprising: separating the sign and magnitude components of said coefficient factor; and feeding said components to an improved multiplier, the output of said multiplier a differential current I_OUT with a polarity varying with said sign component and an amplitude representing the product of said signal factor and said magnitude component.

2. A method according to claim 1 further comprising: representing said magnitude component as a differential of voltages Vxp and V_XN; representing said sign component as a differential of voltages SIGNp and SIGN_N; and representing said signal factor as a differential of currents I_TN and Iτp.

3. A method according to claim 2 wherein representing said magnitude includes: passing said magnitude component into a predistortion circuit, said predistortion circuit compensating for the non-linearity of said multiplier, the output of the predistortion circuit said voltages V_XP and V_X .

4. A method according to claim 2 wherein representing said signal factor includes: converting an input voltage signal initially representing said signal factor into said currents ITP and ITN-

5. A method according to claim 4 further comprising: dividing said current I_TN into currents l₂₀₈ and I₂₀ under the control of said voltages V_XP and V _N; and dividing said current ITP into currents I₂o₆ and I2₀₇ under the control of said voltages V_XP and V_X .

6. A method according to claim 5 further comprising: steering said current I₂₀₈ into one of two output current paths, a positive bias output current path and a negative bias output current path, said steering under control of said voltages SIGN_? and SIGN_N; and steering said current I₂₀₆ into one of said positive bias output current path and said negative bias output current path, said steering under control of said voltages SIGNp and SIGNN-

7. A method according to claim 6 further comprising: steering currents I₂₀₇ and I₂₀ into a dump node under the control of said voltages V_XN and V_XP.

8. A method according to claim 5 wherein the current in said positive bias output current paths comprises an output current I_OU_TP and the current in said negative bias output current paths comprises a current I_OUTN, the difference in currents I_OU_TP and IOUTN comprising the output current I_OUT-

9. A method according to claim 7 wherein said currents I₂₀₇ and I₂₀₉ are steered into said dump node if said magnitude component is small.

10. An apparatus for multiplying a signal factor with a coefficient factor said apparatus comprising: input ports configured to accept independently of each other the sign and magnitude components of said coefficient factor; a signal factor representation means coupled to said input ports accepting said signal factor, said signal factor representation means configured to represent said signal factor as the difference between two currents IT_N and I_TP; a magnitude component representation means coupled to said input ports accepting said magnitude component, said magnitude component representation means configured to represent said magnitude component as the difference of two voltages V_XP and V_XN; and an output current generation means configured to accept as inputs said voltages V_XP and V_XN and said currents I_TN and I_TP, and produce an output current I_OUT as a differential of two currents I_OUTN and I_OUTP, said output current representing the product of said coefficient factor and said signal factor.

11. An apparatus according to claim 10 wherein said magnitude representation means includes a predistortion circuit, said circuit configured to cancel non-linear effects in said output current generation means.

12. An apparatus according to claim 10 wherein said signal factor representation means includes a transconductance means.

13. An apparatus according to claim 10 wherein said output current representation means comprises: a first current divider means configured to divide said current I_TN into two currents I₂o₈ and I₂₀₉ under the control of voltages V_XN and V_XP; and a second current divider means configured to divide said current I_TP into two currents I₂₀₆ and I2₀₇ under the control of voltages V_XN and Vχ_P.

14. An apparatus according to claim 13 wherein said output current representation means further comprises: a first current steering means configured to steer, under the control of said sign component, said current I ₀₈ into one of a first path for differential output current I_OUTP and second path of said output current I_OU_TN; and a second current steering means configured to steer, under the control of said sign component, said current I₂₀ into one of a first path for differential output current I_OU_TP and second path of said output current I_OUTN-

15. An apparatus according to claim 13 wherein said first current dividing means is configured to direct, under control of said voltages V_XP and V_XN, said current I₂₀₉ to a dump node, said dump node not contributing to said output current.

16. An apparatus according to claim 13 wherein said second current dividing means is configured to direct, under control of said voltages V_XP and V_XN, said current I₂₀₇ to a dump node, said dump node not contributing to said output current.

17. An apparatus according to claim 12 wherein said transconductance means includes a current source.

18. An apparatus according to claim 10 wherein said magnitude component representation means includes a transconductance means.

19. An apparatus according to claim 13 wherein said first current divider means includes: a plurality of transistors, said transistors being configured as a differential pair, the emitters of said transistors connected to accept said current I_TN-

20. An apparatus according to claim 13 wherein said second current divider means includes: a plurality of transistors, said transistors being configured as a differential pair, the emitters of said transistors connected to accept said current Iτp.

21. An apparatus according to claim 14 wherein said first current steering means includes: a plurality of transistors, said transistors being configured as a differential pair, the emitters of said transistors connected to accept said current I₂₀₈.

22. An apparatus according to claim 14 wherein said second current steering means includes: a plurality of transistors, said transistors being configured as a differential pair, the emitters of said transistors connected to accept said current I₂₀₆.

23. An apparatus according to claim 10 wherein said sign component is represented as a digital voltage signal.

24. An apparatus according to claim 10 wherein said output current is an analog signal.

25. An apparatus according to claim 10 wherein said voltages Vxp and V_XN are analog signals.

26. A method for analog filtering of a signal factor by a plurality of coefficient factors, said signal factor represented as a differential of voltages Vx and V_XN, said method comprising: representing each said coefficient factor separately as sign and magnitudes components thereof; multiplying each coefficient factor by said signal factor in a time-delayed manner, said multiplying achieved by use of said separate sign and magnitude components; and summing the results of said multiplying together as the output of said filtering.

27. A method according to claim 26 wherein representing includes: extracting said sign and magnitude components from each said coefficient factor.

28. An analog filter comprising: a plurality of improved multipliers, each said multiplier being configured so as to receive as a signal factor and a corresponding coefficient factor, wherein said signal factor is represented as a differential of voltages Vxp and V_XN, and each said coefficient factor is represented by separate sign and magnitude components thereof.

29. An analog filter according to claim 28 further comprising: a plurality of delay elements coupled to said multipliers, configured to provide to each multiplier a selected signal factors from previous cycles; and a summation node coupled to receive and configured to sum together the outputs of said plurality of multipliers, the output of said summation node representing the output of said filter.

30. A system comprising: an analog filter that includes a plurality of improved multipliers, each said multiplier being configured so as to receive as a signal factor and a corresponding coefficient factor, wherein said signal factor is represented as a differential of voltages V_XP and V_X , and each said coefficient factor is represented by separate sign and magnitude components thereof; and a control circuit, said control circuit configured to extract said sign and magnitude components from said coefficient factors.

31. A system according to claim 30 wherein said coefficient factors are programmably altered based upon the response of said system.

32. A system according to claim 30 wherein said system forms part of a high frequency communications system.