WO2003001677A2

WO2003001677A2 - Digital-to-analog converter device and digital-to-analog conversion method

Info

Publication number: WO2003001677A2
Application number: PCT/EP2001/007041
Authority: WO
Inventors: Assaad Borjak; Ashkan Mashhour
Original assignee: Nokia Corporation
Priority date: 2001-06-21
Filing date: 2001-06-21
Publication date: 2003-01-03
Also published as: AU2002213958A1; WO2003001676A2; WO2003001676A3

Abstract

The present invention proposes a digital-to-analog converter device, comprising an input means for inputting a digital signal of n-bit width to said device, a digital-to-analog converter means (1) adapted to output an analog signal corresponding to the input n-bit signal, and is characterized by a signal processing means (4, 6) supplied with said n-bit digital signal and adapted to output an (m+1)-bit digital signal to said digital-to-analog converter means (1), with n > m+1, said digital-to-analog converter means (1) being designed for an (m+1)-bit digital-to-analog conversion. The present invention also proposes a corresponding method. Thus, the present invention adopts a feed forward arrangement for signal processing. This virtually increases the resolution of the used digital-to-analog conversion means to n-bits, although only (m+1)-bits are used, with n > m+1. No increase in DAC clocking frequency is needed. The reduction in the word size of a digital-to-analog converter means results in silicon area savings for integrated circuit implementation, and power consumption decrease.

Description

Digital-to-analog converter device and digital-to-analog conversion method

FIELD OF THE INVENTION

The present invention concerns a digital-to-analog converter device according to the preamble of claim 1, and a method for digital-to-analog conversion according to the preamble of claim 6.

BACKGROUND OF THE INVENTION

Fig. 1 shows a digital-to-analog converter device according to the preamble of claim 1, by means of which a method for digital-to-analog conversion according to the preamble of claim 6 is implemented.

As shown in Fig. 1, according to known prior art, a digital-to-analog converter device comprises an input means for inputting a digital signal of n-bit width to the device, and a digital-to-analog converter means 1 adapted to output an analog signal corresponding to the input n-bit signal. Furthermore, as shown in Fig. 1, the output signal of the digital-to-analog converter means DAC 1 yields an intermediate analog output signal, which thereafter is subjected to an adequate bandpass filtering using a bandpass filter BPF 2, by means of which, for example, high out of band quantization noise can be removed. The analog output of the digital-to-analog converter device is then obtained at the output of the bandpass filter BPF 2. Thus, this prior art digital-to-analog converter device and corresponding method substantially consists in supplying the n-bit digital signal directly into an n-bit digital-to- analog converter DAC 1, as shown in Fig. 1.

Generally, when converting an analog signal to a digital signal, the thus analog-to-digital converted (ADC) signal may have some inaccuracy in terms of (one or more) least significant bits (LSBs) being set or being not set. This inaccuracy is referred to as noise. Thus, when in turn subjecting the digital signal to a digital-to-analog conversion (DAC), this noise leads to an error in the analog signal, also referred to as quantization error/quantization noise.

Reduction of such errors due to noise in digital-to-analog conversion processing and/or devices is a main concern when designing digital-to-analog converter devices. Generally, the quantization error is the lower, the higher the resolution of the digital signal is, i.e. the more bits are used for coding the digital signal.

However, certain limitations such as available chip size for digital-to-analog converter devices implemented in integrated circuit technology may limit the number of bits used for coding a digital signal. Also costs accruing for increasing the number of used bits is a limiting factor in this regard.

Previous approaches to cope with this problem resided in using so called oversampling digital-to-analog converter means, which used sampling at much higher rates than the Nyquist frequency, thereby allowing to uniformly lower the quantization noise floor over frequency. However, this approach has a drawback that oversampling digital-to-analog converter means require to clock the digital-to-analog converter means at a much greater frequency than required. Furthermore, sig a-delta- (∑Δ) -digital-to-analog converter means were proposed to cope with this problem. Such ΣΔ- digital-to-analog converter means perform noise shaping by pushing quantization noise away from the frequency band of interest. However, this alternative approach of using ΣΔ- digital-to-analog converter means consists of a feedback system for the complete signal path, i.e. the signal of interest. Using feedback systems, however, requires to pay attention to feedback system specific issues such as stability of the system by avoiding oscillation of the system.

SUMMARY OF THE INVENTION

Hence, it is an object underlying the present invention to improve digital-to-analog converter devices and methods for digital-to-analog conversion known from the prior art.

More precisely, it is an object of the present invention to provide a digital-to-analog converter device and a corresponding method for digital-to-analog conversion which is free from the above mentioned drawbacks inherent to the prior art arrangements.

According to the present invention, this object is for example achieved by a digital-to-analog converter device, comprising an input means for inputting a digital signal of n-bit width to said device, a digital-to-analog converter means adapted to output an analog signal corresponding to the input n-bit signal, characterized by a signal processing means supplied with said n-bit digital signal and adapted to output an (m+1) -bit digital signal to said digital-to-analog converter means, with n > m+1, said digital-to-analog converter means being designed for an (m+1) -bit digital-to-analog conversion.

According to advantageous further developments of the digital-to-analog converter device

- said signal processing means comprises an adder means and a noise shaping means;

- the m most significant bits of said n-bit digital input signal are supplied to a first input of said adder means, the (n-m) least significant bits of said n-bit digital input signal are supplied to an input of said noise shaping means, and a p-bit output signal (p < (n-m) ) of said noise shaping means is supplied to a second input of said adder means, wherein said adder means adds said m-bit and said p- bit signal to obtain an (m+1) -bit output signal supplied to said digital-to-analog conversion means;

- said noise shaping means is a ΣΔ-modulation means; and

- said p-bit output signal has a width of p=l bit.

Still further, the above mentioned object of the present invention is for example achieved by a method for digital- to-analog conversion, comprising the steps of inputting a digital signal of n-bit width, performing a digital-to- analog conversion for output an analog signal corresponding to the input n-bit signal, characterized by performing a signal processing consisting of supplying said n-bit digital signal and outputting an (m+1) -bit digital signal subjected to said digital-to-analog conversion, with n > m+1, said digital-to-analog conversion being designed for performing an (m+1) -bit digital-to-analog conversion.

According to advantageous further developments of the method according to the present invention

- said signal processing comprises an adding step and a noise shaping step; - the m most significant bits of said n-bit digital input signal are used as a first argument in said adding step, the (n-m) least significant bits of said n-bit digital input signal are subjected to said noise shaping step, and said noise shaping step yields a p-bit output signal (p < (n-m) ) used as a second argument in said adding step, wherein said adding step adding said m-bit and said p-bit signal yields an (m+1) -bit output signal subjected to said digital-to-analog conversion;

- said noise shaping step performs a ΣΔ-modulation; and

- said p-bit output signal has a width of p=l bit.

Advantageously, with the present invention, noise / quantization noise due to a quantization error can be reduced by virtue of the performed signal processing using noise shaping techniques. No higher (but rather a significantly lower) sampling frequency is needed as compared to oversampling DACs. Also, no feedback system is needed, thereby preventing the occurrence of oscillation problems. Only minimal extra hardware consisting of only digital circuits is needed, as compared to ΣΔ-DACs.

The present invention can thus lead to significant cost savings allowing the manufacture of cheaper DACs, and/or an increased integration potential when implementing a DAC on an integrated circuit chip. The invention can be applied in all areas requiring a digital to analog converter such as digital modulators and/or frequency synthesizers. Thus, stated in other words, the present invention offers an advantage of lower quantization noise through noise shaping techniques. The invention makes use of part of an n-bit input signal (n-m least significant bits) as a quantization error which is subjected to shaping and added back to the remaining input signal (m most significant bits) . Thus, the present invention adopts a feed forward arrangement for signal processing. This virtually increases the resolution of the used digital-to-analog conversion means to n-bits, although only (m+1) -bits are used, with n > m+1. No increase in DAC clocking frequency is needed. The reduction in the word size of a digital-to-analog converter means results in silicon area savings for integrated circuit implementation, and power consumption decrease.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more readily understood upon referring to the subsequent detailed description of embodiments thereof as shown in the accompanying drawings, in which

Fig. 1 shows the prior art arrangement of a digital-to- analog converter device according to the preamble of claim 1, implementing a digital-to-analog conversion method according to the preamble of claim 6;

Fig. 2 shows a hardware structure for direct digital synthesis (DDS) based synthesizers as proposed in document US-A-5 563 535, to which, i.e. to the digital-to-analog conversion means DAC used therein, the present invention is applicable;

Fig. 3 shows a digital-to-analog converter device according to the present invention and implementing a corresponding method according to the present invention; and

Fig. 4 shows the present invention when implemented in the arrangement shown in Fig. 2.

DETAILED DESCRIPTION OF THE EMBODIMENTS Fig. 3 shows a digital-to-analog converter device implementing a corresponding method, according to the present invention.

As shown in Fig. 3, the digital-to-analog converter device receives via an input means (not shown) an input digital signal of n-bit width. Before said input signal is supplied to a digital-to-analog converter means 1 adapted to output an analog signal based on an input digital signal, the input signal is supplied to a signal processing means 4, 6. To this end, the n-bit digital signal is split in two branches: one branch of m-bit width contains the m most significant bits (MSBs) of the n-bit signal, and the other branch contains the n-m least significant bits (LSBs) .

Generally spoken, the signal processing means 4, 6 used in the digital-to-analog converter device according the present invention is supplied with said n-bit digital signal and adapted to output an (m+1) -bit digital signal to said digital-to-analog converter means 1, with n > m+1. Said digital-to-analog converter means 1 is designed for an (m+1) -bit digital-to-analog conversion. With reference to the detailed hardware structure of said signal processing means, the signal processing means comprises an adder means 4 and a noise shaping means 6. The m most significant. bits of said n-bit digital input signal are supplied to a first input of said adder means 4, while the n-m least significant bits (representing an amplitude error / quantization error) of said n-bit digital input signal are supplied to an input of said noise shaping means 6. The noise shaping means 6 outputs a p-bit output signal (with p < n-m) , which output signal is supplied to a second input of said adder means 4. The adder means 4 adds said m-bit and said p-bit signal and obtains an (m+1) -bit output signal. This (m+1) -bit output signal is supplied to said digital-to-analog converter means 1. The output signal of the digital-to-analog converter means 1 represents again an intermediate analog output signal which is subsequently subjected to bandpass filtering using a bandpass filter BPF 2, which bandpass filter outputs the final analog output signal .

In the example shown in Fig. 3, the noise shaping means 6 is realized by a ΣΔ-modulation means. Note that the noise shaper or ΣΔ-modulation means 6 is clocked with a signal f_ci - The origin and way of generation of this clock signal is however not a main concern of the present invention. In general, there is a relation between the digital input signal's clock rate, the ΣΔ-clock, and the clock (not shown) of the digital-to-analog converter means 1 of f_cik ≥ fsam_Piing_rate • The sampling rate f_Sampiing_rate is typically greater than the Nyquist frequency (in order to preserve the signal's integrity) and likewise this will hold for the clock of the digital-to-analog converter means 1.

The above configuration as represented in Fig. 3 alleviates the quantization error, hence the effect of the noise due to quantization on the analog output signal.

The transfer function, i.e. the input-to-output characteristic of the ΣΔ-modulator 6 as a noise shaping means is to be adjusted along with the band of interest of the input signal. The knowledge of such an input signal's band and/or frequency range is for example obtained in case of an application of the present invention such as direct digital synthesizer DDS, since the frequency (to be) generated by the direct digital synthesizer is already known beforehand. The knowledge of the input signal's band of interest can for example be obtained by a frequency band detection means (not shown) . Thus, having detected and/or derived a knowledge of the input signal's band of interest, the ΣΔ-modulator can be tuned to this frequency and the bandpass noise shaping can be performed. This, however, will usually be valid only for relatively narrow band applications .

Thus, as set out herein above, according to the present invention, a device and method are presented which enhance the resolution of a digital-to-analog converter means through noise shaping via the adjunction of a ΣΔ-modulator . The present invention produces an improved signal-to-noise ratio SNR for a (m+1) -bit digital-to-analog converter means, where the digital input signal to the digital-to- analog converter device is coded on n-bits (n > m+1) , over a (m+1) -bit digital-to-analog converter means, where the digital input signal is constituted by the m+1 most significant bits (MSB) of the before mentioned n-bit input signal. With adequate filtering (bandpass filtering), this yields a similar SNR for the (m+1) -bit digital-to-analog converter means and the n-bit digital-to-analog converter means, thus virtually increasing the resolution of the digital-to-analog converter means 1.

Heretofore, a description has been given that the n-m least significant bits of an n-bit digital signal are branched off, ΣΔ-modulated and reduced to p-bits (p < n-m) . In a specific case, p may equal to p=l so that the n-m least significant bits of an n-bit digital signal branched off and ΣΔ-modulated are reduced to a single bit that is added to the branched signal (m-bit). The then resulting (m+1)- bits are feed into an (m+1) -bit digital-to-analog converter means. In this way, using an (m+1) -bit digital-to-analog converter means, a performance in terms of quantization noise as using an n-bit digital-to-analog converter means, at least within the bandwidth of the ΣΔ-modulation means is obtained. This effect is generally obtained for the arrangement, for p=l as well as for p > 1.

As mentioned earlier, the present invention is applicable in all areas in which a digital-to-analog converter device is required. For example, the present invention may be applied to direct digital synthesis synthesizers (DDS) . An example for a direct digital frequency synthesizer is known from US-A-5 563 535.

Fig. 2 of the present invention corresponds to Fig. 2 of this United States patent. For details of the functional behavior of the arrangement shown in Fig. 2 , the interested reader is invited to refer to the above mentioned United States patent. In brief, document US-A-5 563 535 employs a ΣΔ-modulation means for phase dithering due to a loss of bit resolution (truncation) from an output of an accumulator 3 (designed for m-bits) to the input of a lookup table LUT 5. The look-up table 5 is for example realized by a read-only memory ROM containing sign wave data. The size of the look-up table 5, i.e. its address space, is coded by m-bits, and the word size of the contents stored at an respective address is k-bits, (m « n) , to keep the size and/or storage capacity of the look-up table ROM reasonable. Similar methods have been employed in phase locked loop (PLL) based synthesizers.

Fig. 4 shows the arrangement shown in Fig. 2 now supplemented by the digital-to-analog converter device according to the present invention. Thus, adapting the quantization error correction method and device as described in connection with the present invention, the system shown in Fig. 2 can be improved by allowing the use of a smaller word size digital-to-analog converter means. More precisely, the output signal of k-bit width as the read-out contents of an address space of the look-up table 5 is branched in two branches: one branch of j most significant bits of the k-bits, and one branch of k-j least significant bits of the k-bits. The j-most significant bits are supplied to an input of an adder means 4a, while the k-j least significant bits are supplied to a noise shaping means, here represented as a ΣΔ-modulator 6a. The ΣΔ- modulator outputs a signal of q-bit width supplied to a second input of the adder means 4a. The addition of the j- bit signal and the q-bit signal yields a signal of (j+1)- bit width supplied to a digital-to-analog converter means 1. Thus, (j+l)-bits as opposed to k-bits, k > j+1 in Fig. 4 are required to be used for the design of the digital-to- analog converter means 1, while yielding a similar signal- to-noise ratio as it were the case with a digital-to-analog converter means of k-bit as shown in Fig. 2. The prior knowledge of the frequency being generated and its narrow band (even as narrow as a single frequency in some cases) make the application of the proposed method and device as introduced in connection with Fig. 3 of the drawings very suitable for application with frequency synthesizers as this .

Thus, the present invention reduces the quantization error introduced by the use of fewer bits to represent the signal, by means of a signal processing technique including a ΣΔ-modulation means as a noise shaping means. This in turn allows the use of a lower resolution digital-to-analog converter means than originally needed to keep the same signal-to-noise ratio (SNR) at the analog output of the digital-to-analog converter device.

Heretofore, reference has been made to a noise shaping means. An example for such a noise shaping means has been given as ∑Δ-modulator . More precisely, a noise shaper - In applicable to the present invention as proposed herein, may be derived from Fig. 4 on page 1048 of the publication "A Direct-Digital Synthesizer with Improved Spectral Performance" by Paul O'Leary and Franco Maloberti in IEEE Transactions on Communications, Vol. 39, No. 7, July 1991. The noise shaper as proposed in Fig. 4 of this document is a simple integrator which can be regarded in fact as an instantiation of a ΣΔ-architecture of first order. A ΣΔ- architecture inherently contains a feedback loop. However, it is to be noted that when discussing the present invention in terms of a feed forward system, this feed forward system refers to the main signal path, and not to an internal feedback within the ΣΔ-modulation means. Other ΣΔ-modulation means different from the first order can be used. That is, second order or higher order ΣΔ- architectures may be used in connection with the ΣΔ- modulation means as a noise shaping means in connection with the present invention.

In view of the fact that ΣΔ-modulation and noise shaping as such is a vast field, the present patent application cannot cover this field exhaustively. Those skilled in the art may safely understand how to implement a ΣΔ-modulation means, and only for the sake of completeness, the interested reader is invited to refer to the publication "Theory of Lowpass and Bandpass Sigma-Delta Modualtion" by Orla Feely, in IEE, 1995, page 7/1 to page 7/8.

Accordingly, as described above, the present invention proposes a digital-to-analog converter device, comprising an input means for inputting a digital signal of n-bit width to said device, a digital-to-analog converter means 1 adapted to output an analog signal corresponding to the input n-bit signal, and is characterized by a signal processing means 4, 6 supplied with said n-bit digital signal and adapted to output an (m+1) -bit digital signal to said digital-to-analog converter means 1, with n > m+1, said digital-to-analog converter means 1 being designed for an (m+1) -bit digital-to-analog conversion. The present invention also proposes a corresponding method. Thus, the present invention adopts a feed forward arrangement for signal processing. This virtually increases the resolution of the used digital-to-analog conversion means to n-bits, although only (m+1) -bits are used, with n > m+1. No increase in DAC clocking frequency is needed. The reduction in the word size of a digital-to-analog converter means results in silicon area savings for integrated circuit implementation, and power consumption decrease.

Although the present invention has been described herein above with reference to its preferred embodiments, it should be understood that numerous modifications may be made thereto without departing from the spirit and scope of the invention. It is intended that all such modifications fall within the scope of the appended claims.

Claims

1. A digital-to-analog converter device, comprising an input means for inputting a digital signal of n-bit width to said device, a digital-to-analog converter means (1) adapted to output an analog signal corresponding to the input n-bit signal, characterized by a signal processing means (4, 6) supplied with said n-bit digital signal and adapted to output an (m+1) -bit digital signal to said digital-to-analog converter means (1), with n > m+1, said digital-to-analog converter means (1) being designed for an (m+1) -bit digital-to-analog conversion.

2. A device according to claim 1, wherein said signal processing means comprises an adder means (4) and a noise shaping means (6) .

3. A device according to claim 2, wherein the most significant bits of said n-bit digital input signal are supplied to a first input of said adder means (4) , the (n-m) least significant bits of said n-bit digital input signal are supplied to an input of said noise shaping means (6) , and a p-bit output signal (p < (n-m) ) of said noise shaping means (6) is supplied to a second input of said adder means (4), wherein said adder means (4) adds said m-bit and said p-bit signal to obtain an (m+1) -bit output signal supplied to said digital-to-analog conversion means (1).

4. A device according to claim 2 or 3, wherein said noise shaping means (6) is a ΣΔ-modulation means.

5. A device according to claim 3, wherein said p-bit output signal has a width of p=l bit.

6. A method for digital-to-analog conversion, comprising the steps of inputting a digital signal of n-bit width, performing a digital-to-analog conversion for output an analog signal corresponding to the input n-bit signal, characterized by performing a signal processing consisting of supplying said n-bit digital signal and outputting an (m+1) -bit digital signal subjected to said digital-to-analog conversion, with n > m+1, said digital-to-analog conversion being designed for performing an (m+1) -bit digital-to-analog conversion.

7. A method according to claim 6, wherein said signal processing comprises an adding step and a noise shaping step.

8. A method according to claim 7, wherein the m most significant bits of said n-bit digital input signal are used as a first argument in said adding step, the (n-m) least significant bits of said n-bit digital input signal are subjected to said noise shaping step, and said noise shaping step yields a p-bit output signal (p < (n-m) ) used as a second argument in said adding step, wherein said adding step adding said m-bit and said p-bit signal yields an (m+1) -bit output signal subjected to said digital-to-analog conversion.

9. A method according to claim 7 or 8, wherein said noise shaping step performs a ΣΔ-modulation.

10. A method according to claim 8, wherein said p-bit output signal has a width of p=l bit.