JPH08167848A - Dc voltage compensating circuit for deltasigma conversion device - Google Patents

Abstract

PURPOSE: To sequentially compensate offset voltage due to the DC voltage components of A/D and D/A converters using ΔΣconverters, a temperature change or power supply voltage variation. CONSTITUTION: A ΔΣ conversion device 100 is constituted of adding a DC voltage compensating circuit 11 to a ΔΣconvertion part 10. The conversion part 10 is provided with an integrator 1, a comparator 3, a one-sample delay circuit 4, and adders 7, 8 as main elements and constituted so that an input signal is added to a signal converted before one sample by the adder 7, the added value is integrated by the integrator 1 and converted into a digital signal by the comparator 3. The circuit 11 is constituted of proportional circuits 5, 6 for proportionally converting an input signal and an output signal, an adder 9 for mutually adding the proportionally converted input and output signals and an integrator 2 for integrating the added signal as constitutional elements. An output from the integrator 2 is fed back to the conversion part 10 to compensate a DC voltage component and offset voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ΔΣ conversion type analog / digital converter and a digital / analog converter.
More specifically, the present invention relates to a ΔΣ converter having a circuit for automatically compensating a DC voltage by using an input signal and an output signal to the ΔΣ converter.

[0002]

2. Description of the Related Art Recently, in an electronic device having a digital circuit as a constituent element, an analog / digital converter (hereinafter, simply referred to as "ADC") has been used in order to reduce the number of circuit parts in combination with the improvement of the integration density of IC. Integration of a digital / analog converter (hereinafter, simply referred to as “DAC”) together with other digital circuits into one integrated circuit (hereinafter, simply referred to as “IC”) has been advanced.

The ADC which is generally used at present extracts an analog signal frequency band with a filter and samples it at a sampling rate which is more than twice the frequency band.
The analog value is converted into a corresponding digital value. As the conversion method, there are a successive comparison type and a batch conversion type. The successive comparison type has a small number of circuit elements and is inexpensive, but the conversion speed is slow and it is difficult to use it for an electronic device that requires high-speed operation. Further, the batch conversion type has a high conversion speed, but the number of elements exponentially increases with respect to the number of decomposed bits, and it is difficult to form an IC together with other digital circuits in a multi-bit circuit. .

Further, the DAC is mainly of a current addition type in which the amount of current flowing according to the corresponding bit is weighted and the currents of all bits are added, but this is also integrated in one IC due to the circuit configuration. Was difficult.

On the other hand, in recent ADCs, the IC driving clock has become faster due to improvements in IC manufacturing technology, and oversampling technology for sampling at a sampling rate four times or eight times the required analog signal frequency band. Can be used, and according to this method, A
A low-pass filter (hereinafter simply referred to as "L
PF ") can be constructed in a low order, and
Quantization noise can also be reduced.

The oversampling technique and Δ
Combining Σ modulation, a bit compression technology, ADCs and DACs with a ΔΣ conversion method that have a smaller number of bits are becoming more practical (Akira Yukawa, “Oversampling A / D / A Conversion Technology,” Nikkei Electronics 1
July 25, 988 issue). The ΔΣ conversion method does not increase the number of constituent elements even if the number of decomposition bits increases due to its configuration form, and is therefore advantageous in integrating it with other digital circuits into an IC. Recently, this conversion method is often used. It has become to.

However, in this converter of the ΔΣ conversion system, conversion noise is generated due to the presence of a DC component, so that the DC component contained in the input signal is removed, and the offset voltage and the offset voltage generated in the ΔΣ converter are removed. There was a problem that fluctuations had to be eliminated.

Next, regarding the conventional correction method of the offset voltage generated in the ΔΣ converter, which is also the subject of the present invention,
This will be described with reference to FIGS.

First, a method of adjusting the offset voltage of the ADC by the ΔΣ conversion method will be described with reference to FIG. The switch 20 is connected to the terminal 2 on the ground side, and a zero potential is input to the ΔΣ conversion module 21. The converted output corresponding to the zero potential is zero without generating an offset voltage if it is an ideal ΔΣ converter, but in general, there is an offset voltage,
Outputs a small value. Next, this output passes through the digital filter 22, and the offset voltage generated in the ΔΣ conversion module 21 is output. Therefore, the digital output corresponding to the zero potential input is stored in the correction value storage memory 2
3, the offset voltage generated in the ΔΣ conversion module 21 is corrected by subtracting the value stored in the memory 23 in the digital filter 22 in the previous period.

After this operation, by connecting the switch 20 to the terminal 1 on the signal side, it is possible to obtain a digital output from which the offset voltage is removed from the input signal. However, as described above, in the adjustment of the ADC offset of the ΔΣ conversion method, the conversion output for the zero potential input measured at a certain time is stored in the memory as a correction value,
Since the offset is corrected with reference to this, it is not possible to correct the fluctuation of the offset due to the temperature rise during the IC operation or the fluctuation of the power supply voltage.

Next, a method of adjusting the offset voltage of the DAC by the ΔΣ conversion method will be described with reference to FIG. 4 (b).
Since the DAC does not generate a DC offset voltage in the ΔΣ conversion module 21 due to its configuration, as shown in FIG. 4B, only the DC component of the digital input signal is removed by the digital filter 24. However, the digital filter 24 is required to have high precision and high speed computing ability.

[0012]

Problem to be Solved by the Invention
Adjusting the DC offset voltage raises the temperature during IC operation,
Or the effect of fluctuations in the power supply voltage, etc. is corrected as necessary to prevent offset voltage from always occurring in the output.
It is intended to relax the precision and the calculation capability required of the digital filter used in the DAC.

[0013]

The present invention has been devised to solve these problems, in which the result obtained by subtracting the input signal from the output signal of the ΔΣ converter is input to an integrator, After that, the above problem is solved by providing a configuration in which the output from the integrator is fed back to the ΔΣ converter. The signal formation to be fed back employs a method of adjusting the respective levels of the output signal and the input signal before the calculation, or a method of collectively adjusting the levels after the calculation.

[0014]

The offset voltage which fluctuates with time due to the temperature change of the ΔΣ converter or power supply fluctuation can be compensated sequentially by the feedback method, and the noise peculiar to the converter generated in the ΔΣ converter is fed back and canceled. Therefore, the generation of noise is reduced.

Since the DC voltage component can be corrected, ΔΣ
The conversion section prevents the generation of the modulation frequency component, and therefore S /
N can be improved, and the output of the compensating circuit includes a component having a dithering effect to the ΔΣ converter due to the feedback DC voltage component, so that the resolution of the converter is improved.

Further, since the output signal is noise-shaped in the ΔΣ conversion method, the output signal minus the low frequency component of the input signal is used for feedback.
The attenuation characteristic of the integrator of the compensation circuit can be designed gently.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is intended to remove the DC component of an input signal in the ΔΣ conversion system and the DC offset voltage generated in the ΔΣ conversion unit as described above.
The circuit configuration and operation will be described with reference to FIGS.

As shown in FIG. 1, a ΔΣ converter 100 according to the present invention is constructed by adding a DC voltage compensating circuit 11 to a ΔΣ converter 10 having a conventional structure. The delta-sigma converter 10 includes an integrator 1, a comparator 3 and a 1-sample delay circuit 4 as main elements.
The digital value converted from is output, and after this output is delayed by 1 sample time by the 1 sample delay circuit 4,
It is added to the input signal in the adder 7 and is input to the integrator 1 as a digital conversion signal in the next sample.

Next, the structure of the DC voltage compensating circuit 11 which forms the feature of the present invention is composed of proportional circuits 5 and 6 for proportionally converting the input signal X1 and the output signal Y1, and the proportionally converted signal X.
Main components are an adder 9 for synthesizing 2 and Y2, and an integrator 2 to which the synthesized signal is input. The output of the integrator 2 is combined with the output of the integrator 1 in the adder 8 of the ΔΣ converter 10.

Next, the DC voltage correction operation will be described. The output spectrum of the ΔΣ converter 10 is formed of the spectrum of the input signal, the spectrum of the noise, and the spectrum of the DC component, as shown in FIG. In the figure (a), the noise spectrum has more energy distributed to higher frequencies due to the characteristic of ΔΣ conversion.
A so-called noise shaping effect is shown in which the spectrum level is increased. Further, if the input signal has a direct current component, when this is modulated, a spectrum is generated in the higher frequency side.

When the DC offset voltage is removed by feedback, if the input signal component is included in the signal to be fed back, the input signal component is also removed from the output signal. Therefore, this input signal spectrum must be attenuated sufficiently before being fed back, and when using a normal filter, it is necessary to make it an extremely steep filter. In this case, the constants of the circuit elements must be selected strictly, and a high-order filter structure must be used.

Therefore, in the present invention, the ΔΣ converter 10
Output Y1 and input X1 are proportional to Y2 and X2 respectively
Converted to and through proportional circuits 5 and 6, and Y2 to X2
The input signal spectrum is removed from the feedback signal by subtracting.

Further, as shown in FIG. 2, Y1 of the output and X1 of the input are added by an adder 9 to remove the input signal spectrum from the feedback signal, and then input to the proportional circuit 15 so that the addition result has an optimum level. May be converted to

The feedback signal produced in this way contains unnecessary DC voltage components in the input signal and offset voltage components generated in the ΔΣ converter 10. Therefore, this signal is converted to ΔΣ. By feeding back to the converter 10, the DC voltage component and the offset voltage component can be removed from the output of the ΔΣ converter 10. That is, since the sequential correction operation is performed by the feedback, the fluctuation of the power supply voltage or the fluctuation of the DC offset voltage value due to the temperature change of the device is corrected at any time.

[0025]

The offset voltage which fluctuates with time due to the temperature change of the ΔΣ converter or the fluctuation of the power supply can be compensated sequentially by the feedback method.

When a DC offset voltage or a DC voltage component is present in the input signal in the ΔΣ converter, a modulation frequency component having a high level is generated in the band used (for example, 20 Hz to 20 KHz in voice), but the DC voltage component is corrected. Since it can be made zero, the generation of the modulation frequency component is prevented, and therefore S
/ N can be improved.

Further, since the output signal is noise-shaped in the ΔΣ conversion method, the attenuation characteristic of the integrator of the compensation circuit can be relaxed by using the output signal minus the low frequency component of the input signal. Yes, that is, an inexpensive low-order filter can be used in the compensation circuit.

Further, since the output of the compensation circuit includes a component having a dithering effect to the ΔΣ converter, it contributes to the improvement of the resolution of the converter.

Furthermore, by the feedback method, ΔΣ
Since the noise component generated in the conversion unit can be fed back and canceled, the generation of noise can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a Δ to which a DC voltage compensation circuit according to the present invention is added.
It is a circuit block diagram which shows the 1st Example of a (sigma) converter.

FIG. 2 is a diagram showing a Δ to which a DC voltage compensation circuit according to the present invention is added.
It is a circuit block diagram which shows the 2nd Example of a (sigma) converter.

FIG. 3 shows an output spectrum by a ΔΣ converter only, FIG. 3A shows an output spectrum when a single frequency is input, and FIG. 3B shows an output spectrum when an input signal is reduced by a compensation circuit. It is a spectrum.

FIG. 4 is a diagram for explaining a conventional offset voltage correction method for a ΔΣ converter, in which (a) shows an ADC and (b) shows a DAC.

[Explanation of symbols]

 1, 2 integrator 3 comparator 4 1 sample delay circuit 5, 6, 15 proportional circuit 7, 8, 9 adder device 10 ΔΣ conversion unit 11 DC voltage compensation circuit 20 switch 21 ΔΣ conversion module 22, 24 digital filter 23 correction value Storage memory 25 D / A converter

Claims (3)

[Claims] 1. A ΔΣ conversion device which constitutes a converter from an analog signal to a digital signal by a ΔΣ conversion system and a converter from a digital signal to an analog signal, wherein an input signal and an output signal to the ΔΣ conversion device are A direct current voltage compensating circuit for a ΔΣ converter, characterized in that after being synthesized, it is input to an integrator and the output of the integrator is fed back to the ΔΣ converter. 2. A circuit for converting an input signal and an output signal to the ΔΣ converter at the same ratio is provided for each signal, and the integrated signal is combined with the input signal and the output signal converted by the circuit, and then the integrator is integrated. The DC voltage compensating circuit for the ΔΣ converter according to claim 1, wherein the DC voltage compensating circuit is configured such that the output of the integrator is fed back to the ΔΣ converter. 3. A circuit for synthesizing an input signal and an output signal to a ΔΣ converter and converting the combined signal at a constant ratio is provided, and an addition signal of the input signal and the output signal converted by the circuit is input to an integrator. The DC voltage compensating circuit for the ΔΣ converter according to claim 1, wherein the output of the integrator is fed back to the ΔΣ converter.