WO2002103893A1 - A method of operating a current-controlled solid state power amplifying device - Google Patents

A method of operating a current-controlled solid state power amplifying device Download PDF

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Publication number
WO2002103893A1
WO2002103893A1 PCT/US2001/019598 US0119598W WO02103893A1 WO 2002103893 A1 WO2002103893 A1 WO 2002103893A1 US 0119598 W US0119598 W US 0119598W WO 02103893 A1 WO02103893 A1 WO 02103893A1
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WO
WIPO (PCT)
Prior art keywords
solid state
circuit
output
impedance matching
state device
Prior art date
Application number
PCT/US2001/019598
Other languages
French (fr)
Inventor
Douglas M. Macheel
Peter B. Jones
Lee B. Max
Original Assignee
Zeta, A Division Of Sierratech, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zeta, A Division Of Sierratech, Inc. filed Critical Zeta, A Division Of Sierratech, Inc.
Priority to PCT/US2001/019598 priority Critical patent/WO2002103893A1/en
Publication of WO2002103893A1 publication Critical patent/WO2002103893A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
    • H01P5/022—Transitions between lines of the same kind and shape, but with different dimensions
    • H01P5/028—Transitions between lines of the same kind and shape, but with different dimensions between strip lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for

Definitions

  • This invention relates generally to the field of current-controlled solid-state power amplifying devices including, but not limited to, bipolar junction transistors (BJTs) and heterojunction bipolar transistors (HBTs).
  • BJTs bipolar junction transistors
  • HBTs heterojunction bipolar transistors
  • a method of operating a solid state current- controlled power-amplifying device includes applying one or more circuit techniques in order to balance the output current of the solid state device.
  • Figure 1 is a block diagram of one embodiment of a radio frequency amplification circuit
  • Figure 2A is a diagram of one embodiment of a radio frequency power BJT coupled to an input impedance matching circuit
  • Figure 2B is a diagram of one embodiment of a radio frequency power BJT coupled to an output impedance matching circuit
  • Figure 3A is a diagram of one embodiment of a base bias circuit coupled to a radio frequency power BJT.
  • Figure 3B is a diagram of one embodiment of a collector bias circuit coupled to a radio frequency power BJT.
  • FIG. 1 is a block diagram of one embodiment of a radio frequency amplification circuit 100.
  • Circuit 100 includes an input impedance matching circuit 110, an output impedance matching circuit 120, a radio frequency (RF) power bipolar junction transistor (BJT) 140, a base bias circuit 170 and a collector bias circuit 180.
  • RF radio frequency
  • BJT radio frequency bipolar junction transistor
  • circuit 100 receives input RF signals at input impedance matching circuit 110, amplifies the signal and transmits the amplified signal from output impedance matching circuit 120 to a load (not shown).
  • BJT 140 may comprise other solid state amplifying devices (e.g., HBT).
  • input impedance matching circuit 110 is designed to receive RF signals.
  • the impedance at the interface between the RF input and input impedance matching circuit 110 is 50 ⁇ .
  • Input impedance matching circuit 110 transforms the impedance from the level of the RF input to the impedance of BJT 140.
  • Figure 2A is a diagram of BJT 140 coupled to input impedance matching circuit 110.
  • input impedance matching circuit 110 includes a multi-section "pitchfork feed" 220.
  • pitchfork feed 220 is a printed trace that is configured to provide a balanced current feed into BJT 140.
  • Typical printed traces are relatively wide single lines that feed BJT 140.
  • pitchfork feed 220 provides for balanced current flow into BJT 140 by evenly dividing the current across multiple connected traces resulting in a more uniform current distribution at the input of BJT 140.
  • Input impedance matching circuit 110 also includes series resistors 230 within branches of the pitchfork feed 220 traces. Resistors 230 further equalize the current paths into BJT 140 so that the current will not prefer one side of the pitchfork feed 220 to the others. In addition, resistors 230 reduce the likelihood of low frequency oscillation of the high frequency BJT 140. According to one embodiment, each resistor 230 has a 4.7 ⁇ resistance. Nevertheless, one of ordinary skill in the art will appreciate that other values for resistors 230 may be used.
  • Input impedance matching circuit 110 further includes resistors 235.
  • Resistors 235 are placed pairs of branches of pitchfork feed 220 to further equalize the current between any two branches of pitchfork feed 220. For example, imbalances between the top two branches of pitchfork feed 220 are reduced by the resistor 235 between the two.
  • each resistor 230 has a 10 ⁇ resistance. Nevertheless, one of ordinary skill in the art will appreciate that other values for resistors 230 may be used.
  • Output impedance matching circuit 120 is coupled to BJT 140.
  • Output impedance matching circuit 120 transforms the impedance from the level of BJT 140 to the impedance level of load coupled to circuit 100.
  • the impedance at the interface between output impedance matching circuit 120 and the load is 50 ⁇ .
  • Figure 2B is a diagram of BJT 140 coupled to output impedance matching circuit 120.
  • output impedance matching circuit 120 includes a multi-section pitchfork feed 260 similar to pitchfork feed 220 in input impedance matching circuit 110.
  • the pitchfork feed 260 configuration in output impedance matching circuit 120 also presents a low impedance at the second and third harmonic frequencies to the output of BJT 140. The low impedance at the harmonic frequencies minimizes the RF voltage peaks at the output of BJT 140.
  • Base bias circuit 170 connects a power supply voltage to BJT 140 without having an affect on the RF signal amplified by BJT 140.
  • base bias circuit 170 presents a low impedance, resistive load to the bases of BJT 140 at frequencies from 1 MHz to one-third of the operating RF frequency of BJT 140.
  • base bias circuit 170 delivers the appropriate amount of DC current to the base of BJT 140 to optimize RF performance.
  • Figure 3A is a diagram of one embodiment of base bias circuit 170 coupled to BJT 140.
  • bias circuit 170 includes a set of resistors. The resistors are coupled between a supply voltage (VBB) and the base of BJT 140.
  • VBB supply voltage
  • Collector bias circuit 180 connects a DC power supply voltage to BJT 140 without affecting the RF signal amplified by BJT 140. According to one embodiment, bias circuit 180 results in uniform voltage across the entire lead 270 of BJT 140 coupled to the collectors of transistor 240.
  • Figure 3B is a diagram of one embodiment of collector bias circuit 180 coupled to BJT 140.
  • Bias circuit 180 includes a transient voltage suppressor 310, a capacitor (C) and an inductor (L). Transient voltage suppressor 310 is connected between a supply voltage (Vcc) and ground.
  • Vcc supplies 45-50 volts DC at 10A to the collector of BJT 140.
  • Transient voltage suppressor 110 suppresses voltage spikes within circuit 100 caused during the switching between high and low current levels.
  • transient voltage suppressor 110 is implemented using a diode.
  • fast voltage clipping devices may be used to implement transient voltage suppressor 110.
  • Inductor L is coupled between the supply voltage and BJT 140. Inductor L provides a predetermined impedance value that prevents RF current flow from BJT 140 through bias circuit 180. However, according to one embodiment, inductor L is designed to be sufficiently small so as to minimize voltage spikes caused by transient currents that occur due to changing current through the circuit. For example, whenever the output power of circuit 100 is quickly switched from low to high (e.g., 50 ns rise/ fall time), or vice versa, the current flow through inductor L changes, resulting in a transient voltage spike. The larger the inductance of inductor L, the higher the magnitude of the voltage spike. In cases where the voltage spike is sufficiently large, severe damage to BJT 140 may occur. Therefore, the small size of inductor L and the presence of transient voltage suppressor 110 permits BJT 140 to operate at higher voltages (e.g., 50 volts).

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

According to one embodiment, a circuit is disclosed. The circuit comprises a solid state power amplifying device (140), an input impedance matching circuit (110) and an output impedance matching circuit (120) coupled to the solid state amplifying device (140). The input impedance matching circuit (110) includes an input pitchfork trace pattern. The output impedance matching circuit (120) includes an output pitchfork trace pattern. The circuit further discloses an input bias circuit (170) and an output bias circuit (180).

Description

A METHOD OF OPERATING A CURRENT-CONTROLLED SOLID STATE POWER
AMPLIFYING DEVICE
FIELD OF THE INVENTION
This invention relates generally to the field of current-controlled solid-state power amplifying devices including, but not limited to, bipolar junction transistors (BJTs) and heterojunction bipolar transistors (HBTs).
BACKGROUND
It is widely known that improving output current balance of the die within solid-state, power amplifying devices results in performance improvement of gain, efficiency, peak output power and linearity. An area of amplifier performance enhancement that has heretofore been overlooked is the utilization and optimization of the amplifier circuit components to assist in balancing the output current distribution of the die of the amplifying device. Therefore, a method of balancing a solid state, power amplifying device is desired.
SUMMARY
According to one embodiment, a method of operating a solid state current- controlled power-amplifying device is disclosed. The method includes applying one or more circuit techniques in order to balance the output current of the solid state device. BRIEF DESCRIPTION OF THE DRAWINGS
A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:
Figure 1 is a block diagram of one embodiment of a radio frequency amplification circuit;
Figure 2A is a diagram of one embodiment of a radio frequency power BJT coupled to an input impedance matching circuit;
Figure 2B is a diagram of one embodiment of a radio frequency power BJT coupled to an output impedance matching circuit;
Figure 3A is a diagram of one embodiment of a base bias circuit coupled to a radio frequency power BJT; and
Figure 3B is a diagram of one embodiment of a collector bias circuit coupled to a radio frequency power BJT.
DETAILED DESCRIPTION
In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known structures and, devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. Figure 1 is a block diagram of one embodiment of a radio frequency amplification circuit 100. Circuit 100 includes an input impedance matching circuit 110, an output impedance matching circuit 120, a radio frequency (RF) power bipolar junction transistor (BJT) 140, a base bias circuit 170 and a collector bias circuit 180. According to one embodiment, circuit 100 receives input RF signals at input impedance matching circuit 110, amplifies the signal and transmits the amplified signal from output impedance matching circuit 120 to a load (not shown). In other embodiments, BJT 140 may comprise other solid state amplifying devices (e.g., HBT).
INPUT IMPEDANCE MATCHING CIRCUIT
As described above, input impedance matching circuit 110 is designed to receive RF signals. According to one embodiment, the impedance at the interface between the RF input and input impedance matching circuit 110 is 50Ω. Input impedance matching circuit 110 transforms the impedance from the level of the RF input to the impedance of BJT 140. Figure 2A is a diagram of BJT 140 coupled to input impedance matching circuit 110.
Referring to Figure 2A, input impedance matching circuit 110 includes a multi-section "pitchfork feed" 220. According to one embodiment, pitchfork feed 220 is a printed trace that is configured to provide a balanced current feed into BJT 140. Typical printed traces are relatively wide single lines that feed BJT 140. However, whenever circuit 100 is operating at high frequency there is typically a higher current density towards the outside edges of the wide single trace. Such an occurrence results in an unbalanced current feed into BJT 140. Therefore, pitchfork feed 220 provides for balanced current flow into BJT 140 by evenly dividing the current across multiple connected traces resulting in a more uniform current distribution at the input of BJT 140. Input impedance matching circuit 110 also includes series resistors 230 within branches of the pitchfork feed 220 traces. Resistors 230 further equalize the current paths into BJT 140 so that the current will not prefer one side of the pitchfork feed 220 to the others. In addition, resistors 230 reduce the likelihood of low frequency oscillation of the high frequency BJT 140. According to one embodiment, each resistor 230 has a 4.7Ω resistance. Nevertheless, one of ordinary skill in the art will appreciate that other values for resistors 230 may be used.
Input impedance matching circuit 110 further includes resistors 235. Resistors 235 are placed pairs of branches of pitchfork feed 220 to further equalize the current between any two branches of pitchfork feed 220. For example, imbalances between the top two branches of pitchfork feed 220 are reduced by the resistor 235 between the two. According to one embodiment, each resistor 230 has a 10Ω resistance. Nevertheless, one of ordinary skill in the art will appreciate that other values for resistors 230 may be used.
OUTPUT IMPEDANCE MATCHING CIRCUIT
Output impedance matching circuit 120 is coupled to BJT 140. Output impedance matching circuit 120 transforms the impedance from the level of BJT 140 to the impedance level of load coupled to circuit 100. According to one embodiment, the impedance at the interface between output impedance matching circuit 120 and the load is 50Ω. Figure 2B is a diagram of BJT 140 coupled to output impedance matching circuit 120.
Referring to Figure 2B, output impedance matching circuit 120 includes a multi-section pitchfork feed 260 similar to pitchfork feed 220 in input impedance matching circuit 110. In addition to the advantages described above, the pitchfork feed 260 configuration in output impedance matching circuit 120 also presents a low impedance at the second and third harmonic frequencies to the output of BJT 140. The low impedance at the harmonic frequencies minimizes the RF voltage peaks at the output of BJT 140.
BASE BIAS CIRCUIT
Base bias circuit 170 connects a power supply voltage to BJT 140 without having an affect on the RF signal amplified by BJT 140. According to one embodiment, base bias circuit 170 presents a low impedance, resistive load to the bases of BJT 140 at frequencies from 1 MHz to one-third of the operating RF frequency of BJT 140. In addition, base bias circuit 170 delivers the appropriate amount of DC current to the base of BJT 140 to optimize RF performance. Figure 3A is a diagram of one embodiment of base bias circuit 170 coupled to BJT 140. According to one embodiment, bias circuit 170 includes a set of resistors. The resistors are coupled between a supply voltage (VBB) and the base of BJT 140.
COLLECTOR BIAS CIRCUIT
Collector bias circuit 180 connects a DC power supply voltage to BJT 140 without affecting the RF signal amplified by BJT 140. According to one embodiment, bias circuit 180 results in uniform voltage across the entire lead 270 of BJT 140 coupled to the collectors of transistor 240. Figure 3B is a diagram of one embodiment of collector bias circuit 180 coupled to BJT 140. Bias circuit 180 includes a transient voltage suppressor 310, a capacitor (C) and an inductor (L). Transient voltage suppressor 310 is connected between a supply voltage (Vcc) and ground.
According to one embodiment, Vcc supplies 45-50 volts DC at 10A to the collector of BJT 140. Transient voltage suppressor 110 suppresses voltage spikes within circuit 100 caused during the switching between high and low current levels. In one embodiment, transient voltage suppressor 110 is implemented using a diode. However, one of ordinary skill in the art will appreciate that other fast voltage clipping devices may be used to implement transient voltage suppressor 110.
Inductor L is coupled between the supply voltage and BJT 140. Inductor L provides a predetermined impedance value that prevents RF current flow from BJT 140 through bias circuit 180. However, according to one embodiment, inductor L is designed to be sufficiently small so as to minimize voltage spikes caused by transient currents that occur due to changing current through the circuit. For example, whenever the output power of circuit 100 is quickly switched from low to high (e.g., 50 ns rise/ fall time), or vice versa, the current flow through inductor L changes, resulting in a transient voltage spike. The larger the inductance of inductor L, the higher the magnitude of the voltage spike. In cases where the voltage spike is sufficiently large, severe damage to BJT 140 may occur. Therefore, the small size of inductor L and the presence of transient voltage suppressor 110 permits BJT 140 to operate at higher voltages (e.g., 50 volts).
Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as the invention.

Claims

CLAIMSWhat is claimed is:
1. A method of operating a solid state current-controlled power amplifying device comprising applying one or more circuit techniques in order to balance the output current of the solid state device.
2. The method of claim 1 wherein the process of applying one or more circuit techniques in order to balance the output current of the solid state device comprises coupling an input pitchfork trace pattern to the input of the solid state device.
3. The method of claim 2 wherein the process of applying one or more circuit techniques in order to balance the output current of the solid state device comprises coupling an output pitchf ork trace pattern to the output of the solid state device.
4. The method of claim 2 wherein the process of applying one or more circuit techniques in order to balance the output current of the solid state device further comprises inserting a resistor within one or more branches of the input pitchfork trace pattern.
5. The method of claim 2 wherein the process of applying one or more circuit techniques in order to balance the output current of the solid state device further comprises inserting a resistor between one or more pairs of branches of the input pitchfork trace pattern.
6. The method of claim 1 further comprising applying one or more circuit techniques in order to reduce voltage spikes at the solid state device.
7. The method of claim 6 wherein the process of applying one or more circuit techniques in order to reduce voltage spikes at the solid state device comprises minimizing radio frequency (RF) voltage peaks at the solid state device.
8. The method of claim 6 wherein the process of applying one or more circuit techniques in order to reduce voltage spikes at the solid state device comprises coupling a transient voltage suppressor to the solid state device.
9. The method of claim 7 wherein the process of minimizing RF voltage peaks at the solid state device comprises presenting a matching impedance at a fundamental frequency of the solid state device.
10. The method of claim 7 wherein the process of minimizing RF voltage peaks at the solid state device further comprises presenting a matching impedance appearing at the odd harmonic frequencies of the solid state device.
11. The method of claim 7 wherein the process of minimizing RF voltage peaks at the solid state device further comprises presenting a matching impedance appearing at the even harmonic frequencies of the solid state device.
12. The method of claim 1 wherein the solid state device is a bipolar junction transistor (BJT).
13. The method of claim 1 wherein the solid state device is a heterojunction bipolar transistor (HBT).
14. An amplification circuit comprising: a current controlled solid state amplifying device; and an output impedance matching circuit coupled to the solid state amplifying device, wherein the output impedance matching circuit includes an output pitchfork trace pattern.
15. An amplification circuit comprising: a current controlled solid state amplifying device; and an input impedance matching circuit coupled to the solid state amplifying device, wherein the input impedance matching circuit includes an input pitchfork trace pattern.
16. The circuit of claim 15 wherein the input impedance matching circuit further comprises a resistor inserted within one or more branches of the pitchfork trace pattern.
17. The circuit of claim 15 wherein the input impedance matching circuit further comprises a resistor connected across one or more pairs of branches of the pitchfork trace pattern.
18. The circuit of claim 15 further comprising: a radio frequency source coupled to the input impedance matching circuit; an output impedance matching circuit coupled to the amplifying device; and a load coupled to the output impedance matching circuit.
19. The circuit of claim 15 further comprising a first bias circuit coupled to the solid state amplifying device and the output impedance matching circuit.
20. The circuit of claim 19 wherein the output bias circuit comprises a transient voltage suppressor.
21. The circuit of claim 16 further comprising an input bias circuit coupled to the amplifying device and the input impedance matching circuit.
22. The circuit of claim 15 wherein the solid state device is a bipolar junction transistor (BJT).
23. The circuit of claim 15 wherein the solid state device is a heterojunction bipolar transistor (HBT).
24. An amplification circuit comprising: a current controlled solid state amplifying device; and an output bias circuit coupled to the solid state amplifying device, wherein the output bias circuit comprises a transient voltage suppressor.
PCT/US2001/019598 2001-06-19 2001-06-19 A method of operating a current-controlled solid state power amplifying device WO2002103893A1 (en)

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Application Number Priority Date Filing Date Title
PCT/US2001/019598 WO2002103893A1 (en) 2001-06-19 2001-06-19 A method of operating a current-controlled solid state power amplifying device

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Application Number Priority Date Filing Date Title
PCT/US2001/019598 WO2002103893A1 (en) 2001-06-19 2001-06-19 A method of operating a current-controlled solid state power amplifying device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017005501A (en) * 2015-06-10 2017-01-05 住友電気工業株式会社 Electronic circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117203A (en) * 1990-12-13 1992-05-26 General Electric Company Phase stable limiting power amplifier
US5357213A (en) * 1992-10-09 1994-10-18 Thomson-Lgt Laboratoire General Des Telecommunications High-frequency wide band amplifier having reduced impedance
US6054902A (en) * 1996-08-09 2000-04-25 Murata Maufacturing Co., Ltd. High-frequency amplifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117203A (en) * 1990-12-13 1992-05-26 General Electric Company Phase stable limiting power amplifier
US5357213A (en) * 1992-10-09 1994-10-18 Thomson-Lgt Laboratoire General Des Telecommunications High-frequency wide band amplifier having reduced impedance
US6054902A (en) * 1996-08-09 2000-04-25 Murata Maufacturing Co., Ltd. High-frequency amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017005501A (en) * 2015-06-10 2017-01-05 住友電気工業株式会社 Electronic circuit

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