WO2002103494A3 - Multifunktionaler rechner - Google Patents

Multifunktionaler rechner Download PDF

Info

Publication number
WO2002103494A3
WO2002103494A3 PCT/EP2002/005429 EP0205429W WO02103494A3 WO 2002103494 A3 WO2002103494 A3 WO 2002103494A3 EP 0205429 W EP0205429 W EP 0205429W WO 02103494 A3 WO02103494 A3 WO 02103494A3
Authority
WO
WIPO (PCT)
Prior art keywords
information
command
data
computational unit
amount
Prior art date
Application number
PCT/EP2002/005429
Other languages
English (en)
French (fr)
Other versions
WO2002103494A2 (de
Inventor
Stefan Rueping
Original Assignee
Infineon Technologies Ag
Stefan Rueping
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Stefan Rueping filed Critical Infineon Technologies Ag
Priority to AU2002314075A priority Critical patent/AU2002314075A1/en
Publication of WO2002103494A2 publication Critical patent/WO2002103494A2/de
Publication of WO2002103494A3 publication Critical patent/WO2002103494A3/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
    • G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2123—Dummy operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)
  • Detection And Correction Of Errors (AREA)
  • Storage Device Security (AREA)

Abstract

Die vorliegende Erfindung schafft einen Rechner, der ein erstes Rechenwerk (1) und ein zweites Rechenwerk (2) aufweist. In dem ersten Rechenwerk (1) werden erste Informationen, die einen ersten Befehl und/oder eine erste Datenmenge umfassen, verarbeitet, während in dem zweiten Rechenwerk (2) zweite Informationen, die einen zweiten Befehl und/oder eine zweite Datenmenge umfassen, verarbeitet, wobei der erste Befehl gleich dem zweiten Befehl ist und die zweite Datenmenge Kompensationsdaten aufweist. Der Rechner weist ferner eine Verkopplungseinrichtung (5) zum Empfangen der ersten Informationen und zum Liefern der zweiten Informationen zu dem zweiten Rechenwerk (2) auf. Die Verkopplungseinrichtung (5) ist ausgebildet, um die zweiten Informationen abhängig von den ersten Informationen so zu erzeugen, daß die zweiten Informationen von den ersten Informationen unterschiedlich sind. Die Verkopplungseinrichtung ist ferner ausgebildet, um die Kompensationsdaten aus den ersten Informationen und dem zweiten Befehl derart zu erzeugen, daß eine Quersumme von logisch hohen Zuständen der ersten und zweiten Datenmenge einen konstanten vorbestimmten Wert aufweist.
PCT/EP2002/005429 2001-06-18 2002-05-16 Multifunktionaler rechner WO2002103494A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002314075A AU2002314075A1 (en) 2001-06-18 2002-05-16 Multifunctional computer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10129241.4 2001-06-18
DE10129241A DE10129241B4 (de) 2001-06-18 2001-06-18 Multifunktionaler Rechner

Publications (2)

Publication Number Publication Date
WO2002103494A2 WO2002103494A2 (de) 2002-12-27
WO2002103494A3 true WO2002103494A3 (de) 2003-09-25

Family

ID=7688521

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/005429 WO2002103494A2 (de) 2001-06-18 2002-05-16 Multifunktionaler rechner

Country Status (3)

Country Link
AU (1) AU2002314075A1 (de)
DE (1) DE10129241B4 (de)
WO (1) WO2002103494A2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BR122014004140B8 (pt) 2011-08-22 2023-03-28 Bayer Cropscience Ag Vetor recombinante ou construção recombinante, bem como métodos para obter e produzir uma planta de algodão ou célula vegetal tolerante a um inibidor de hppd, e para cultivar um campo de plantas de algodão

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1006492A1 (de) * 1998-11-30 2000-06-07 Hitachi, Ltd. Datenverarbeitungsanlage und -chipkarte
US6219789B1 (en) * 1995-07-20 2001-04-17 Dallas Semiconductor Corporation Microprocessor with coprocessing capabilities for secure transactions and quick clearing capabilities
EP1115094A2 (de) * 2000-01-08 2001-07-11 Philips Corporate Intellectual Property GmbH Datenverarbeitungseinrichtung und Verfahren zu dessen Betrieb
WO2001061916A2 (en) * 2000-02-18 2001-08-23 Cloakware Corporation Encoding method and system resistant to power analysis
US20010016910A1 (en) * 2000-01-12 2001-08-23 Chiaki Tanimoto IC card and microprocessor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574348A (en) * 1983-06-01 1986-03-04 The Boeing Company High speed digital signal processor architecture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6219789B1 (en) * 1995-07-20 2001-04-17 Dallas Semiconductor Corporation Microprocessor with coprocessing capabilities for secure transactions and quick clearing capabilities
EP1006492A1 (de) * 1998-11-30 2000-06-07 Hitachi, Ltd. Datenverarbeitungsanlage und -chipkarte
EP1115094A2 (de) * 2000-01-08 2001-07-11 Philips Corporate Intellectual Property GmbH Datenverarbeitungseinrichtung und Verfahren zu dessen Betrieb
US20010016910A1 (en) * 2000-01-12 2001-08-23 Chiaki Tanimoto IC card and microprocessor
WO2001061916A2 (en) * 2000-02-18 2001-08-23 Cloakware Corporation Encoding method and system resistant to power analysis

Also Published As

Publication number Publication date
AU2002314075A1 (en) 2003-01-02
DE10129241B4 (de) 2008-04-30
WO2002103494A2 (de) 2002-12-27
DE10129241A1 (de) 2003-01-02

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