WO2002091472A3 - Transistor und integrierter schaltkreis - Google Patents

Transistor und integrierter schaltkreis Download PDF

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Publication number
WO2002091472A3
WO2002091472A3 PCT/DE2002/001561 DE0201561W WO02091472A3 WO 2002091472 A3 WO2002091472 A3 WO 2002091472A3 DE 0201561 W DE0201561 W DE 0201561W WO 02091472 A3 WO02091472 A3 WO 02091472A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
capacity
transistor
owing
fact
Prior art date
Application number
PCT/DE2002/001561
Other languages
English (en)
French (fr)
Other versions
WO2002091472A2 (de
Inventor
Franz Hofmann
Wolfgang Roesner
Original Assignee
Infineon Technologies Ag
Franz Hofmann
Wolfgang Roesner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Franz Hofmann, Wolfgang Roesner filed Critical Infineon Technologies Ag
Publication of WO2002091472A2 publication Critical patent/WO2002091472A2/de
Publication of WO2002091472A3 publication Critical patent/WO2002091472A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Die Erfindung schafft einen MOS-Transistor, bei dem die Source- und die Drain-Kapazität bezüglich des Substrats dadurch reduziert ist, dass unter der Source- und Drain-Zuführung je ein Isolatorelement (507) aus einem Material mit niedriger Dielektrizitätskonstante angeordnet ist. Die Erfindung schafft weiter einen integrierten Schaltkreis, bei dem die Bitleitungs-Zuleitungs-Kapazität bezüglich des Substrats dadurch reduziert ist, dass unter der Bitleitungs-Zuleitung ein Isolatorelement (307) aus einem Material mit niedriger Dielektrizitätskonstante angeordnet ist.
PCT/DE2002/001561 2001-05-03 2002-04-29 Transistor und integrierter schaltkreis WO2002091472A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10121494.4 2001-05-03
DE10121494A DE10121494A1 (de) 2001-05-03 2001-05-03 Transistor und integrierter Schaltkreis

Publications (2)

Publication Number Publication Date
WO2002091472A2 WO2002091472A2 (de) 2002-11-14
WO2002091472A3 true WO2002091472A3 (de) 2003-02-20

Family

ID=7683479

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/001561 WO2002091472A2 (de) 2001-05-03 2002-04-29 Transistor und integrierter schaltkreis

Country Status (3)

Country Link
DE (1) DE10121494A1 (de)
TW (1) TW541700B (de)
WO (1) WO2002091472A2 (de)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS636868A (ja) * 1986-06-26 1988-01-12 Sony Corp メモリ装置
JPS63307775A (ja) * 1987-06-09 1988-12-15 Nec Corp キャパシタおよびその製造方法
US5620912A (en) * 1994-07-21 1997-04-15 Lg Semicon Co., Ltd. Method of manufacturing a semiconductor device using a spacer
EP0814507A1 (de) * 1996-06-21 1997-12-29 Siemens Aktiengesellschaft Grabenkondensator-Speicherzelle und Verfahren zur Herstellung derselben
US5953604A (en) * 1995-10-05 1999-09-14 Integrated Device Technology, Inc. Methods for making compact P-channel/N-channel transistor structure
US6198142B1 (en) * 1998-07-31 2001-03-06 Intel Corporation Transistor with minimal junction capacitance and method of fabrication

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS636868A (ja) * 1986-06-26 1988-01-12 Sony Corp メモリ装置
JPS63307775A (ja) * 1987-06-09 1988-12-15 Nec Corp キャパシタおよびその製造方法
US5620912A (en) * 1994-07-21 1997-04-15 Lg Semicon Co., Ltd. Method of manufacturing a semiconductor device using a spacer
US5953604A (en) * 1995-10-05 1999-09-14 Integrated Device Technology, Inc. Methods for making compact P-channel/N-channel transistor structure
EP0814507A1 (de) * 1996-06-21 1997-12-29 Siemens Aktiengesellschaft Grabenkondensator-Speicherzelle und Verfahren zur Herstellung derselben
US6198142B1 (en) * 1998-07-31 2001-03-06 Intel Corporation Transistor with minimal junction capacitance and method of fabrication

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 012, no. 207 (E - 621) 14 June 1988 (1988-06-14) *
PATENT ABSTRACTS OF JAPAN vol. 013, no. 147 (E - 741) 11 April 1989 (1989-04-11) *

Also Published As

Publication number Publication date
TW541700B (en) 2003-07-11
DE10121494A1 (de) 2002-11-14
WO2002091472A2 (de) 2002-11-14

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