Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T1/00—General purpose image data processing
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H17/00—Networks using digital techniques
  • H03H17/02—Frequency selective networks
  • H03H17/0202—Two or more dimensional filters; Filters for complex signals

Definitions

• This disclosure is related to pyramid filters.
• an image such as a scanned color image
• a color or gray-scale document image can be decomposed into background and foreground images for efficient image processing operations, such as enhancement, compression, etc., as are at times applied in a typical photocopying machine or scanner device.
• this operation is often referred to as a descreening operation.
• This descreening is also sometimes applied to remove halftone patterns that may exist in an original scanned image. For example, these halftone patterns may cause objectionable artifacts for human eyes if not properly removed.
• the traditional approach for this decomposition or descreening is to filter the color image in order to blur it.
• symmetric pyramid filtering architectures to generate different blurred images in parallel from a single source image may be desirable.
• the numbers provided in parenthesis for each FIR block in FIG. 1 represents the pyramid filter of corresponding length.
• (1 , 2, 1) are the filter coefficients for a symmetric pyramid finite impulse response (FIR) filter of order or length 3.
• (1 , 2, 3, 2, 1) are the coefficients for an FIR pyramid filter of order 5
• (1 , 2, 3, 4, 3, 2, 1) are the coefficients for an FIR pyramid filter of order 7
• (1 , 2, 3, 4, 5, 4, 3, 2, 1 ) are the coefficients for an FIR pyramid filter of order 9
• (1 , 2, 3, 4, 5, 6, 5, 4, 3, 2, 1) are the coefficients for an FIR pyramid filter of order 1 1 , and so forth.
• FIG. 1 has disadvantages. For example, inefficiency may result from redundant computations. Likewise, FIR implementations frequently employ multiplier circuits. While implementations exist to reduce or avoid the use of multipliers, such as with shifting and summing circuitry, that may then result in increased clocking and, hence, may reduce circuit throughput. A need, therefore, exists for improving pyramid filtering implementations or architectures.
• FIG. 1 is a block diagram illustrating a brute force approach to implementing a finite impulse response (FIR) multiple pyramid filtering architecture
• FIG. 2 is one embodiment of a one-dimensional multiplierless pyramid filter
• FIG. 3 is one embodiment of a two-dimensional pyramid filter architecture
• FIG. 4 is a table/matrix showing an example of a matrix that may result from implementing a two-dimensional pyramid filter architecture, such as one that may be implemented by the embodiment of FIG. 3;
• FIG. 5 is a table/matrix showing an example of a two-dimensional signal that may be operated upon by a two-dimensional pyramid filter architecture
• FIG. 6 is a table/matrix showing an example of applying a one-dimensional pyramid filter kernel both row-wise and column-wise;
• FIG. 8 is a table/matrix showing the result of applying a one-dimensional pyramid filter to the rows of a two-dimensional input signal sample matrix
• FIG. 9 is a table/matrix showing the result of applying a one-dimensional pyramid filter to the columns of a two-dimensional input signal sample matrix.
• pyramid filtering in particular, symmetric pyramid filtering, may be employed in connection with color images or color image processing in order to decompose or descreen the image, such as into a background and foreground image, for example.
• pyramid filtering architectures that reduce computational complexity or processing and/or hardware cost are particularly desirable.
• implementations that are multiplerless, that is, do not specifically employ multiplication in the implementation are also desirable usually because such implementations or embodiments are cheaper to implement than those that employ or include multiplier circuits.
• FIG. 2 illustrates an embodiment 200 of a one-dimensional pyramid filter, such as described in more detail in aforementioned U.S. Patent Application Serial No. 09/754,684, titled “Multiplierless Pyramid Filter,” by T. Acharya (attorney docket no. 042390. P10722), filed on January 3, 2001.
• Embodiment 200 comprises a unified multiplierless cascaded symmetric pyramid filtering architecture to generate a multiple number of filtered output signal streams for a series or sequence of pyramid filters having different orders, the generation of the output signal streams occurring in parallel.
• this particular embodiment although, again, the claimed subject matter is not limited in scope in this respect, a filtered output signal stream is produced on every clock cycle for each pyramid filter of a different order being implemented. Therefore, in addition to being computationally efficient, this particular embodiment produces good results in terms of throughput. However, as previously indicated, this particular embodiment implements a one-dimensional pyramid filter.
• FIG. 2 is understood in the context of specific notation.
• an input source signal, X may be designated as follows:
• FIG.2 employs pyramid filters. These filters are typically implemented using digital filters of lengths or orders that are odd, such as 3, 5, 7, 9, etc. Odd numbers or orders, in this context, may be expressed in the form 2N-1 , where N is a positive integer greater than two, for example. Some examples of such digital filters are as follows:
• the filtered output signals or output signal streams may be represented as follows:
• bj Xj. 3 + 2x
• bj 9 Xj. 4 + 2x*,- 3 + 3Xj- 2 + 4X1-! + 5Xi + 4x i+1 + 3x i+2 + 2x i+3 + x i+4
• bi 11 x*,- 5 + 2Xj. 4 + 3Xi -3 + 4x i-2 + 5xi_i + 6X
• bi 3 X
• + Sj 3 , where s 3 x M + x, + x i+1
• the desired pyramid filter may be expressed as follows:
• FIG. 2 A study of FIG. 2 illustrates that the computed output signal streams, B 3 , B 5 , B 7 , B 9 , Bn, etc. of the pyramid filters shown in FIG. 2 are produced by the embodiment illustrated.
• dimensional pyramid filter F hk may be derived as shown in FIG. 6.
• FIG. 7 we
• FIG. 4 is a table illustrating a matrix that may result, here a two-dimensional filtered signal sample output matrix, P kxk , in which the two dimensional input signal sample matrix is filtered using two-dimensional pyramid filter kernel E ⁇ .
• the matrix shown in FIG. 8 may result from applying a one-dimensional k- tap pyramid filter in every row of the two-dimensional input signal sample matrix and the matrix shown in FIG. 9 may result from applying a one-dimensional k-tap pyramid filter in every column of the two-dimensional input signal sample matrix.
• the matrix in FIG. 8 may result from applying a one-dimensional k- tap pyramid filter in every row of the two-dimensional input signal sample matrix
• the matrix shown in FIG. 9 may result from applying a one-dimensional k-tap pyramid filter in every column of the two-dimensional input signal sample matrix.
• +3j ._ +10s l+3J +8s ;+3j . +l +6s l 3J+2 + 4s, +3J+3 + 2s, +3j+4 ) + ( * ⁇
• p f X s , ;- 5 + 2S ⁇ , + 3*,*,y_ 3 + 4-s, j _ 2 + 5s u _, + 6s, >y + 5s . , +1 + 4s u+2 + 3s iJ+3 + 2s,. , +4 + s,. +5
• Pu U O s +2s,._ 5J _ 4 +3s,._ 5 _ 3 +4s,._ 5 _ 2 +5s,._ 5 ._ 1 +6s,._ 5> . + 5s,._ S +1 +4s,._ 5 . +2 +3s,._ 5 +3 +2s,._ 5> . +4 +s,._ 5 +5 )* (2 4, ,*- 5 +4* M ⁇ y_ 4 +6s MJ _ 3 + 8s,._ 4> ._ 2 + 10s,._ 4 _, +12s,._ 4 + 10s,._ 4 +1 + 8 J M J+2 + 6s,._ 4 ?
• Equation [1] above illustrates that a direct two-dimensional pyramid filter architecture of order 2N-1 , in this case where N is six, may potentially be implemented using either four two-dimensional pyramid filters of order [2(N-1)-1], that is nine, or one two-dimensional pyramid filter of order [2(N-1)-1] using four
• dimensional pyramid filters of order 2N-1 here eleven, the filters being row-wise and column-wise, in this example. It also employs one two-dimensional pyramid filter of order [2(N-2)-1], that is seven here, to produce P. 7 * 7 and two one-dimensional pyramid filter of order [2(N-2)-1], that is seven here, to produce P. 7 * 7 and two one-dimensional pyramid filter of order [2(N-2)-1], that is seven here, to produce P. 7 * 7 and two one-
• FIG. 3 is a schematic
• the output signal samples corresponding to those produced by four two-dimensional pyramid filters of order 2(N-1)-1 , here order nine where N is six, and also the output signal samples produced by two-dimensional pyramid filter of order 2(N-2)-1 , here order seven, may not necessarily be produced by two- dimensional pyramid filters.
• these output signals may be produced using one-dimensional pyramid filters.
• One such filter is shown in FIG. 2, although, again, additional approaches to producing the output signals for the architecture shown in FIG. 3 may also be employed.
• FIG. 3 illustrates an integrated circuit (IC), 300, although, of course, alternative embodiments may not necessarily be implemented on a single integrated circuit chip.
• IC 300 includes a two-dimensional pyramid filter architecture of an order 2N-1 , where N is a positive integer greater than five, here six, in operation, capable of producing, on respective clock cycles, at least the following.
• Pyramid filtered output signals are produced corresponding to output signals produced by fourteen one-dimensional pyramid filters of order 2N-1, again, eleven in this example where N is six, 330, 332, 334, 340, 342, 344, 350, 352, 354, 360, 362, 364, 366, and 368 in FIG. 3.
• Pyramid filtered output signals are also produced corresponding to output signals produced either by four two- dimensional pyramid filters or one two-dimensional pyramid of order [2(N-1) - 1] or nine here, where N is six, using signal sample
• Pyramid filtered output signals are also produced corresponding to output signals produced by one two-dimensional pyramid filter of order [2(N-2) - 1] or seven here, where N is six , using signal sample
• the output signals in this two dimensional pyramid filter architecture implementation in the implementation in FIG. 3, for example, the output signals of 330, 332, 334, 340, 342, 344, 350, 352, 354, 360, 362, 364, 366, and 368 are summed on respective clock cycles of the two dimensional pyramid filter architecture, by adders 370 and 375 in FIG. 3.
• Adder 380 sums the output signals of 310, 370, 375 and 390.
• FIG. 3 is just one possible example of an implementation and the claimed subject matter is not limited in scope to this or to another particular implementation.
• N is not limited to six.
• the pyramid filtered output signals that correspond to output signals produced by a two-dimensional pyramid filter are not limited to being implemented by one-dimensional pyramid filters or to two-dimensional pyramid filters.
• the filters are not limited to the implementation approach described in aforementioned U. S. Patent Application Serial No. 09/754,684, titled “Multiplierless Pyramid Filter,” filed January 3, 2001 , by Tinku Acharya, or in aforementioned U. S. Patent Application Serial No., titled “Pyramid Filter,” (attorney docket 042390.P11211), filed on March 28, 2001, by Tinku Acharya.
• one-dimensional pyramid filters other than multiplierless pyramid filters may be employed.
• different numbers of such pyramid filters and different orders of such pyramid filters may be employed.
• the output signals may be combined or processed in a way to produce pyramid filtered output signals corresponding to pyramid filters of a different number, dimension, or order.
• Such a storage medium such as, for example, a CD-ROM, or a disk, may have stored thereon instructions, which when executed by a system, such as a computer system or platform, or an imaging system, for example, may result in an embodiment of a method in accordance with the claimed subject matter being executed, such as an embodiment of a method of filtering or processing an image or video, for example, as previously described.
• a system such as a computer system or platform, or an imaging system
• an imaging system for example, may result in an embodiment of a method in accordance with the claimed subject matter being executed, such as an embodiment of a method of filtering or processing an image or video, for example, as previously described.
• an image processing platform or an imaging processing system may include an image processing unit, a video or image input/output device and/or memory.

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• Mathematical Physics (AREA)
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• Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
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• Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
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• 2001
  • 2001-04-30 US US09/846,609 patent/US6725247B2/en not_active Expired - Fee Related
• 2002
  • 2002-03-12 TW TW091104602A patent/TW556120B/zh not_active IP Right Cessation
  • 2002-04-12 KR KR1020037014161A patent/KR100550676B1/ko not_active Expired - Lifetime
  • 2002-04-12 CN CNA028091191A patent/CN1505866A/zh active Pending
  • 2002-04-12 EP EP02725662A patent/EP1396081B1/en not_active Expired - Lifetime
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  • 2002-04-12 AT AT02725662T patent/ATE298471T1/de not_active IP Right Cessation
  • 2002-04-12 WO PCT/US2002/011753 patent/WO2002089061A2/en not_active Ceased
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  • 2002-04-12 JP JP2002586286A patent/JP4102198B2/ja not_active Expired - Lifetime
• 2004
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