WO2002075808A2 - Contact de memoire mram auto-aligne et procede de fabrication - Google Patents

Contact de memoire mram auto-aligne et procede de fabrication Download PDF

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Publication number
WO2002075808A2
WO2002075808A2 PCT/US2002/007285 US0207285W WO02075808A2 WO 2002075808 A2 WO2002075808 A2 WO 2002075808A2 US 0207285 W US0207285 W US 0207285W WO 02075808 A2 WO02075808 A2 WO 02075808A2
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WO
WIPO (PCT)
Prior art keywords
layers
magnetic
layer
iron
conductive
Prior art date
Application number
PCT/US2002/007285
Other languages
English (en)
Other versions
WO2002075808A3 (fr
Inventor
Roger Lee
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to PCT/US2002/007285 priority Critical patent/WO2002075808A2/fr
Priority to AU2002306683A priority patent/AU2002306683A1/en
Publication of WO2002075808A2 publication Critical patent/WO2002075808A2/fr
Publication of WO2002075808A3 publication Critical patent/WO2002075808A3/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment

Definitions

  • the present invention relates MRAM semiconductor structures
  • Magnetic random access memories employ magnetic
  • an MRAM cell stores
  • the MRAM cell has two stable magnetic configurations, high resistance
  • a typical multilayer-film MRAM includes a number of bit or
  • magnetically coercive material is inte ⁇ osed between the corresponding bit line and
  • lines form a magnetic memory cell which stores a bit of information.
  • the basic memory element of an MRAM is a patterned structure
  • a multilayer material which is typically composed of a stack of different materials, such as copper (Cu), tantalum (Ta), permalloy (NiFe) or aluminum
  • the stack may contain as many as ten different oxides (Al 2 O 3 ), among others.
  • the stack may contain as many as ten different oxides (Al 2 O 3 ), among others.
  • the stack may contain as many as ten different
  • overlapping material layers and the layer sequence may repeat up to ten times.
  • Figure 1 shows an exemplary conventional MRAM structure
  • MRAM stacks 22 which have three respective associated bit or digit lines
  • the digit lines 18, typically formed of copper (Cu), are first formed in an
  • insulating layer 16 formed over underlayers 14 of an integrated circuit (IC)
  • Underlayers 14 may include, for example, portions of integrated
  • a pinned layer 20 typically formed of
  • a pinned layer is
  • CMOS circuits for example CMOS circuits and/or with circuitry that
  • word line conductors are typically formed by
  • the photolithography techniques employ a
  • the present invention provides a method for forming self- aligned
  • MRAM contacts for MRAM structures such as magnetic layers of an MRAM
  • MRAM stacks are formed to include a
  • top layer of a conductive material such as tungsten nitrogen.
  • CMP chemically mechanically polished
  • Figure 1 is a schematic three-dimensional view of a portion of a
  • Figure 2 illustrates a partial cross-sectional view of a
  • Figure 3 illustrates a partial cross-sectional view of the self-
  • Figure 4 illustrates a partial cross-sectional view of the self-
  • Figure 5 illustrates a partial cross-sectional view of the self-
  • Figure 6 illustrates a partial cross-sectional view of the self-
  • Figure 7 illustrates a partial cross-sectional view of the self-
  • Figure 8 illustrates a partial cross-sectional view of the self-
  • Figure 9 illustrates a partial cross-sectional view of the self-
  • Figure 10 illustrates a partial cross-sectional view of the self-
  • Figure 11 illustrates a partial cross-sectional view of the self-
  • Figure 12 illustrates a partial cross-sectional view of the self-
  • Figure 13 illustrates a partial cross-sectional view of the self-
  • Figure 14 illustrates a partial cross-sectional view of the self-
  • Figure 15 illustrates a partial cross-sectional view of the self-
  • Figure 16 is a partial three-dimensional view of the self- aligned
  • Figure 17 is a partial three-dimensional view of the self- aligned
  • Figure 18 is a partial three-dimensional view of the self- aligned
  • Figure 19 is a partial three-dimensional view of the self-aligned
  • Figure 20 is a schematic diagram of a processor system
  • substrate used in the following description may
  • Structure must be understood to include silicon, silicon-on insulator
  • SOI silicon-on sapphire
  • SOS silicon-on sapphire
  • doped and undoped semiconductors epitaxial layers of silicon supported by a base semiconductor foundation, and od er
  • the semiconductor need not be silicon-based.
  • semiconductor could be silicon-germanium, germanium, or gallium arsenide.
  • steps may have been utilized to form regions or junctions in or on the base
  • metal is intended to include not only elemental
  • metal is also known in the semiconductor art.
  • metal is also known in the semiconductor art.
  • metal is also known in the semiconductor art.
  • metal is also known in the semiconductor art.
  • Figures 2-19 illustrate an exemplary
  • Figure 2 depicts a portion of a semiconductor substrate 50
  • the underlying layer 52 could include, for example,
  • circuit layers forming CMOS devices and circuits.
  • an insulating layer 54 is formed over
  • the insulating layer 54 is blanket deposited by spin coating to a thickness of about 1,000 Angstroms to about 10,000 Angstroms.
  • CND plasma enhanced CND
  • PECND plasma enhanced CND
  • PND physical vapor deposition
  • the insulating layer 54 may be formed of a conventional insulator, for
  • a thermal oxide of silicon such as SiO or SiO 2
  • a nitride such as Si 3 ⁇ 4 .
  • a high temperature polymer such as a polyimide, or a low dielectric
  • constant inorganic material may also be employed.
  • the photoresist layer 55 is exposed d rough a mask
  • the mask 56 ( Figure 5) with high-intensity UN light.
  • the mask 56 may include any suitable
  • photoresist layer 55 are exposed through portions 56a of the mask 56 wherever
  • portions of the insulating layer 54 need to be removed.
  • Figure 5 schematically illustrates mask 56 positioned
  • openings 57 are left over the insulating layer 54, as shown in Figure 6. This way, openings 57
  • the grooves 58 are etched to a
  • thin barrier layer 59 is formed in the grooves 58 and over the insulating layer 54,
  • bonding materials such as tantalum (Ta), titanium (Ti), titanium-
  • TiW titanium nitride
  • Cr chromium
  • barrier layer 59 forms a strong mechanical and chemical bond between the
  • the barrier layer 59 is formed of sputtered
  • tantalum is deposited to a thickness of about 5nm
  • a conductive material layer 60 is
  • the conductive material comprises copper (Cu).
  • metal alloys may be employed also, depending on
  • the conductive material layer 60 is formed over the barrier layer
  • CMP polishing
  • RIE RIE dry etching
  • metal line 62 will form the bit or digit line of a conventional MRAM structure.
  • magnetic member 79 is formed of various material layers, described below in more
  • a first tantalum (Ta) layer 71 (of about 20-400 Angstroms
  • NiFe nickel-iron
  • (NiFe) layer 77 (of about 10-100 Angstroms thick, more preferably of about 60
  • Angstroms thick are successively blanket deposited over the insulating layer 54
  • layers 71, 73, 75 and 77 may be accomplished by magnetron sputtering, for
  • nonmagnetic, electrically nonconductive layer 80 formed of, for example,
  • Al 2 O 3 aluminum oxide (Al 2 O 3 ) (of about 5-25 Angstroms thick, more preferably of
  • Magnetic materials such as copper (Cu), titanium oxide (TiO 2 ), magnesium oxide
  • MgO silicon oxide
  • SiO 2 silicon oxide
  • A1N aluminum nitride
  • films forming a second magnetic member 89 are next formed over the nonmagnetic layer 80. Accordingly, in an exemplary embodiment of the present
  • a third nickel-iron (NiFe) layer 81 (of about 10-100 Angstroms thick,
  • tantalum (Ta) layer 83 (of
  • a conductive layer 85 (of about 100-400 Angstroms thick, more preferably of
  • magnetron sputtering for example, but other conventional deposition methods
  • conductive layer 85 may be formed of tungsten nitrogen (WN), which is deposited
  • tungsten (W) tungsten
  • copper tungsten (W)
  • MRAM structure 100 includes the pinned layer 91 (as part of the first magnetic
  • the multilayer stack For simplicity, the multilayer stack
  • forming the pinned layer 91 is illustrated in Figure 16 as a single layer. Similarly,
  • the multilayer stack forming the sense layer 92 is also illustrated in Figure 16 as a
  • the pinned layer 91 includes
  • layer 92 includes portions of the layers 81, 83 and 85.
  • 75, 77, 80, 81, 83 and 85 may be accomplished by ion milling which typically
  • Patterning involves physical sputtering of each layer by an argon ion beam. Patterning may be
  • ECR electron cyclotron resonance
  • a mixture of chlorine with other gases such as argon, neon or
  • helium may be used also.
  • the pinned and sense layers may be used also.
  • metal lines 62 that form the bottom electrodes of the pinned layers 91.
  • substrate 50 including the MRAM structures 100 to a thickness of about 90-
  • the insulating circuitry 10,000 Angstroms, more preferably of about 5,000 Angstroms.
  • the insulating layer 95 is formed of a nitride material such as silicon nitride (Si 3 N 4 ), which may be
  • CND plasma enhanced CND
  • PECND plasma enhanced CND
  • aluminum oxide a thermal oxide of silicon, such as SiO or SiO 2 , or a
  • high temperature polymer such as a polyimide, a low dielectric constant inorganic
  • amo ⁇ hous dielectric or bias sputtered quartz may also be employed.
  • MRAM structures 100 are removed by means of chemical mechanical polishing
  • CMP CMP or well-known RIE dry etching processes.
  • the insulating layer 95 is chemical mechanical polished so that an
  • abravise polish removes d e top surface of die insulating layer 95 above the MRAM
  • conductors to enable bidirectional current flow in die presence of a read and write signal, may be formed to complete the fabrication process of such MRAM
  • Figure 19 illustrates schematically three MRAM cell
  • the word line 93 may be formed of copper, for example, by patterning a
  • word line 93 is formed on a direction orthogonal to that of the sense layer 92.
  • Figure 19 illustrates self- aligned MRAM contacts 99 in
  • the word line 93 may be formed also, as desired.
  • a typical processor based system 400 which includes a memory
  • circuit 448 for example an MRAM with MRAM cell structures 100 having self-
  • a processor system such as a computer system, generally comprises a central processing unit (CPU) 444, such as a CPU
  • microprocessor a digital signal processor, or odier programmable digital logic
  • I/O input/output
  • the memory 448 communicates with the system over bus 452.
  • the processor system may
  • peripheral devices such as a floppy disk drive 454 and a compact disk (CD)
  • ROM drive 456 which also communicate with CPU 444 over die bus 452.
  • Memory 448 may be combined with the processor, i.e. CPU 444, in a single
  • invention contemplates the use of a plurality of self- aligned MRAM contacts 99 of
  • pinned layers and sense layers as part of a plurality of MRAM cells arranged, for
  • invention contemplates the use of other methods of patterning and etching.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

L'invention concerne un procédé de formation d'un contact de mémoire MRAM auto-aligné. Les paquets de mémoire MRAM munis d'une couche supérieure de matériau conducteur sont formés sur des portions de circuits intégrés. Un matériau isolant est formé sur le substrat, comportant les paquets de mémoire MRAM munis de la couche supérieure de matériau conducteur. Le matériau isolant est ensuite poli ou gravé de façon mécanico-chimique, jusqu'au niveau de la couche supérieure de matériau conducteur, afin d'exposer ce matériau utilisé en tant que contacts MRAM auto-alignés.
PCT/US2002/007285 2001-03-15 2002-03-12 Contact de memoire mram auto-aligne et procede de fabrication WO2002075808A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2002/007285 WO2002075808A2 (fr) 2001-03-15 2002-03-12 Contact de memoire mram auto-aligne et procede de fabrication
AU2002306683A AU2002306683A1 (en) 2001-03-15 2002-03-12 Self-aligned mram contact and method of fabrication

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US80591501 2001-03-15
US09/805,915 2001-03-15
PCT/US2002/007285 WO2002075808A2 (fr) 2001-03-15 2002-03-12 Contact de memoire mram auto-aligne et procede de fabrication

Publications (2)

Publication Number Publication Date
WO2002075808A2 true WO2002075808A2 (fr) 2002-09-26
WO2002075808A3 WO2002075808A3 (fr) 2004-02-12

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Country Status (2)

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AU (1) AU2002306683A1 (fr)
WO (1) WO2002075808A2 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841692A (en) * 1996-03-18 1998-11-24 International Business Machines Corporation Magnetic tunnel junction device with antiferromagnetically coupled pinned layer
EP1054449A2 (fr) * 1999-05-17 2000-11-22 Motorola, Inc. Mémoire à accès direct magnétique et sa méthode de fabrication
US6153443A (en) * 1998-12-21 2000-11-28 Motorola, Inc. Method of fabricating a magnetic random access memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841692A (en) * 1996-03-18 1998-11-24 International Business Machines Corporation Magnetic tunnel junction device with antiferromagnetically coupled pinned layer
US6153443A (en) * 1998-12-21 2000-11-28 Motorola, Inc. Method of fabricating a magnetic random access memory
EP1054449A2 (fr) * 1999-05-17 2000-11-22 Motorola, Inc. Mémoire à accès direct magnétique et sa méthode de fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HU Y Z ET AL: "Chemical-mechanical polishing as an enabling technology for giant magnetoresistance devices" THIN SOLID FILMS, ELSEVIER-SEQUOIA S.A. LAUSANNE, CH, vol. 308-309, no. 1-4, 31 October 1997 (1997-10-31), pages 555-561, XP004110335 ISSN: 0040-6090 *

Also Published As

Publication number Publication date
AU2002306683A1 (en) 2002-10-03
WO2002075808A3 (fr) 2004-02-12

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