WO2002069498A3 - Rapid single flux quantum programmable gate array - Google Patents

Rapid single flux quantum programmable gate array Download PDF

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Publication number
WO2002069498A3
WO2002069498A3 PCT/ZA2002/000023 ZA0200023W WO02069498A3 WO 2002069498 A3 WO2002069498 A3 WO 2002069498A3 ZA 0200023 W ZA0200023 W ZA 0200023W WO 02069498 A3 WO02069498 A3 WO 02069498A3
Authority
WO
WIPO (PCT)
Prior art keywords
flux quantum
single flux
programmable gate
gate array
rapid single
Prior art date
Application number
PCT/ZA2002/000023
Other languages
French (fr)
Other versions
WO2002069498A2 (en
Inventor
Peter Gross
Willem Jacobus Perold
Original Assignee
Univ Stellenbosh
Peter Gross
Willem Jacobus Perold
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Stellenbosh, Peter Gross, Willem Jacobus Perold filed Critical Univ Stellenbosh
Publication of WO2002069498A2 publication Critical patent/WO2002069498A2/en
Publication of WO2002069498A3 publication Critical patent/WO2002069498A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

A configurable logic block (10) comprising rapid single flux quantum (RSFQ) superconducting circuitry comprises first and second input arrangements (12,14) connected to an imput selector (16). The input selector is connected to an address decoder (18) for a look-up table (LUT) (20). An output of the LUT is connected via an output selector (22) to output arrangements (24,26). An interconnect resource enables uni-directional propagation of RSFQ pulses between adjacent blocks in an array of blocks.
PCT/ZA2002/000023 2001-02-28 2002-02-28 Rapid single flux quantum programmable gate array WO2002069498A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ZA200101657 2001-02-28
ZA2001/1657 2001-02-28

Publications (2)

Publication Number Publication Date
WO2002069498A2 WO2002069498A2 (en) 2002-09-06
WO2002069498A3 true WO2002069498A3 (en) 2004-02-12

Family

ID=25589083

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/ZA2002/000023 WO2002069498A2 (en) 2001-02-28 2002-02-28 Rapid single flux quantum programmable gate array

Country Status (1)

Country Link
WO (1) WO2002069498A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7443719B2 (en) * 2006-02-23 2008-10-28 Hypres, Inc. Superconducting circuit for high-speed lookup table
US9520180B1 (en) 2014-03-11 2016-12-13 Hypres, Inc. System and method for cryogenic hybrid technology computing and memory
US9712172B2 (en) 2015-10-07 2017-07-18 Microsoft Technology Licensing, Llc Devices with an array of superconducting logic cells
US10411713B2 (en) * 2017-02-04 2019-09-10 Microsoft Technology Licensing, Llc Superconducting circuits based devices and methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233242A (en) * 1991-08-14 1993-08-03 Westinghouse Electric Corp. Superconducting push-pull flux quantum gate array cells
JPH08148989A (en) * 1994-11-18 1996-06-07 Hitachi Ltd Superconducting fpga device
US5629889A (en) * 1995-12-14 1997-05-13 Nec Research Institute, Inc. Superconducting fault-tolerant programmable memory cell incorporating Josephson junctions

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233242A (en) * 1991-08-14 1993-08-03 Westinghouse Electric Corp. Superconducting push-pull flux quantum gate array cells
JPH08148989A (en) * 1994-11-18 1996-06-07 Hitachi Ltd Superconducting fpga device
US5629889A (en) * 1995-12-14 1997-05-13 Nec Research Institute, Inc. Superconducting fault-tolerant programmable memory cell incorporating Josephson junctions

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
BEHA H,JÄCKEL H: "Programmable Josephson Current Injection Logic Device", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 26, no. 7A, 1 December 1983 (1983-12-01), New York, US, pages 3387 - 3388, XP002251462 *
BROWN S ET AL: "FPGA AND CPLD ARCHITECTURES: A TUTORIAL", IEEE DESIGN & TEST OF COMPUTERS, IEEE COMPUTERS SOCIETY. LOS ALAMITOS, US, vol. 13, no. 2, 1 June 1996 (1996-06-01), pages 42 - 57, XP000596695, ISSN: 0740-7475 *
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 10 31 October 1996 (1996-10-31) *
REDDY S ET AL: "A high density embedded array programmable logic architecture", CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1996., PROCEEDINGS OF THE IEEE 1996 SAN DIEGO, CA, USA 5-8 MAY 1996, NEW YORK, NY, USA,IEEE, US, 5 May 1996 (1996-05-05), pages 251 - 254, XP010167455, ISBN: 0-7803-3117-6 *

Also Published As

Publication number Publication date
WO2002069498A2 (en) 2002-09-06

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