WO2002069498A2 - Rapid single flux quantum programmable gate array - Google Patents
Rapid single flux quantum programmable gate array Download PDFInfo
- Publication number
- WO2002069498A2 WO2002069498A2 PCT/ZA2002/000023 ZA0200023W WO02069498A2 WO 2002069498 A2 WO2002069498 A2 WO 2002069498A2 ZA 0200023 W ZA0200023 W ZA 0200023W WO 02069498 A2 WO02069498 A2 WO 02069498A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- arrangement
- logic circuit
- circuits
- configurable logic
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
Definitions
- THIS invention relates to configurable logic blocks and more
- Programmable gate arrays are general-purpose devices that can be
- logic circuits operate at about 200MHz.
- the logic circuitry comprising configurable rapid single flux
- the rapid single flux quantum circuitry is preferably programmable.
- the logic circuitry may comprise a lookup table comprising
- the configurable logic circuit may comprise an input selector circuit for
- the configurable logic circuit may comprise an output selector circuit
- the address decoder circuit may be connected to a clock circuit.
- the configurable logic circuit may be arranged in a block and at least a
- output arrangement may be provided on a first side of the block.
- arrangement may be provided on a second side of the block.
- the block is preferably rectangular in configuration and the first side
- the second side may be opposed to one another.
- the invention also includes within its scope a programmable gate array
- programmable tile circuit comprising a configurable logic circuit as
- the interconnect resource circuit preferably causes pulses to
- the invention also includes within its scope an array of tile circuits
- the interconnect in an array of at least four tile circuits the interconnect
- resource circuits may collectively provide a first propagation path
- figure 1 is a basic block diagram of a configurable logic circuit
- figure 2 is a block diagram of a programmable gate array
- figure 3(a) is a basic Josephson junction circuit diagram of a rapid
- figure 3(b) is a schematic representation of the cell
- figure 3(c) is a timing diagram of the operation of the cell
- figure 4(a) is a more detailed diagram of an input selector for the
- figure 4(b) is a schematic representation of the input selector
- figure 5(a) is a more detailed diagram of an address decoder for a
- figure 5(b) is a schematic representation of the address decoder
- figure 6(a) is a more detailed diagram of the lookup table for the
- figure 6(b) is a schematic representation of the lookup table
- figure 7(a) is a more detailed diagram of an output selector for the
- figure 7(b) is a schematic representation of the output selector
- figure 8(a) is a more detailed diagram of a switch box for a tile in
- figure 8(b) is a schematic representation of the switch box
- figure 9(a) is a more detailed diagram of an interconnect resource
- figure 9(b) is a schematic representation of the interconnect
- figure 10 is a schematic representation of the upper right hand tile
- figure 1 1 is another representation of the tile in figures 2 and 9 in
- the invention is generally designated by the reference numeral 10 in
- figure 1 figure 1 .
- the circuit 10 comprises a first input arrangement 12, comprising
- a second input arrangement 14 comprising inputs
- a clock 28 is connected to the
- the clock 28 may also be connected to the address
- RSFQ flux quantum
- the circuit 10 may form part of each of tile circuits 30.1 to 30.4
- the circuit may be provided in
- output arrangement 24 are provided on one side 32 of rectangular
- the circuit 10 may form part of a programmable gate array (PGA) of
- circuits that can be interconnected in a selected manner.
- interconnect resource facilitates this selected connection.
- the RSFQ PGA array 40 in figure 2 comprises four tiles 30.1 to 30.4
- each comprising the basic circuit 10 but differing from one another in
- the interconnect resources collectively provide a
- Each tile further comprises a switch box 38.1 to 38.4
- Any plurality of such tiles may be used in an RSFQ PGA
- a basic element of the circuit 10 is a non-destructive read out (NDRO)
- the selectable pin X allows row selection of the cell 31 in an array.
- the set repeat pin S' and clear repeat pin C allow for vertical
- junctions J1 and J2 in figure 3(a) are responsible for the repeating of the set S and clear C signals.
- the X line 33 biases two resistors that
- the cell is as follows. When the cell is set and pin A is pulsed, then
- pin F pulses. Otherwise there will be no pulse at pin F.
- clock period would indicate a logic one while the absence of a pulse
- RSFQ input selector 16 A more detailed diagram of an RSFQ input selector 16 is shown in
- the input selector comprises eight (8) of the
- NDRO non-destructive read out
- outputs of the buffers are designated 46.0 to 46.3 respectively.
- FIG. 5(a) A schematic representation of the decoder 18 is
- outputs of the splitters are directed to AND gates 58.0 to 58.15, to
- the LUT 20 comprises an array of sixteen
- the output selector 22 is shown in more detail in figure 7(a) and a
- output selector comprises an eight-way splitter 64 connected to the
- the splitter is connected to eight memory
- a switch box 38.2 is shown in more detail in figure 8(a) and a
- 38.2 comprises sixteen memory cells 70.0 to 70.15 interconnected as
- FIG 2 A more detailed diagram of interconnect resource 36.2 is shown in
- the resource comprises confluence buffers 72.0 to 72.3,
- the interconnect resource allows for the
- the tile comprises a plurality of memory cells 31 as hereinbefore
- Input/outputs are provided on all four sides of the tile. The speed at
- RSFQPGA RSFQ Programmable Gate Array
- the first step for the designing a circuit for the RSFQPGA is to
- circuit conceptualise a functional circuit.
- the circuit is then captured as a
- circuit network that can be implemented by one of the available
- a placement stage determines where to place each mapped block
- This stage merely chooses physical CLBs to allocate
- a routing stage assigns the Interconnect Resources to set the required
- the RSFQPGA would be programmed using a serial communication
- serial data will be loaded by a RSFQ shift
- RSFQPGA would be the ability to arrange the devices in an in-line
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
A configurable logic block (10) comprising rapid single flux quantum (RSFQ) superconducting circuitry comprises first and second input arrangements (12,14) connected to an imput selector (16). The input selector is connected to an address decoder (18) for a look-up table (LUT) (20). An output of the LUT is connected via an output selector (22) to output arrangements (24,26). An interconnect resource enables uni-directional propagation of RSFQ pulses between adjacent blocks in an array of blocks.
Description
RAPID SINGLE FLUX QUANTUM PROGRAMMABLE GATE ARRAY
TECHNICAL FIELD
THIS invention relates to configurable logic blocks and more
particularly to programmable gate arrays comprising such blocks.
BACKGROUND ART
Programmable gate arrays are general-purpose devices that can be
configured or programmed for a wide variety of applications. The
fastest of these arrays which comprise semi-conductor voltage state
logic circuits operate at about 200MHz.
OBJECTIVE OF THE INVENTION
It is an object of this invention to provide a configurable logic circuit
and gate array with which the applicant believes substantially higher
speeds of operation may be achieved.
DISCLOSURE OF THE INVENTION
According to the invention there is provided a configurable logic circuit
comprising:
- an input arrangement comprising a plurality of inputs;
an output arrangement comprising a plurality of outputs;
configurable logic circuitry connected between the input
arrangement and the output arrangement;
the logic circuitry comprising configurable rapid single flux
quantum superconducting circuitry to perform logic operations
on signals at the input arrangement utilizing propagating pulses
of the rapid single flux quantum circuitry.
The rapid single flux quantum circuitry is preferably programmable.
The logic circuitry may comprise a lookup table comprising
configurable rapid single flux quantum superconducting circuitry.
The configurable logic circuit may comprise an input selector circuit for
cooperating with the input arrangement and an address decoder circuit
for the lookup table connected between the input arrangement and the
lookup table.
The configurable logic circuit may comprise an output selector circuit
for cooperating with the output arrangement connected between the
lookup table and the output arrangement.
The address decoder circuit may be connected to a clock circuit.
The configurable logic circuit may be arranged in a block and at least a
first part of the input arrangement and at least a first part of the
output arrangement may be provided on a first side of the block.
Another part of the input arrangement and another part of the output
arrangement may be provided on a second side of the block.
The block is preferably rectangular in configuration and the first side
and the second side may be opposed to one another.
The invention also includes within its scope a programmable gate array
comprising a configurable logic circuit as herein defined and/or
described.
Yet further included within the scope of the invention is a
programmable tile circuit comprising a configurable logic circuit as
herein defined and/or described and an interconnect resource circuit
for connecting the logic circuit to another logic circuit.
The interconnect resource circuit preferably causes pulses to
propagate in one direction only.
The invention also includes within its scope an array of tile circuits
wherein respective interconnect resource circuits collectively provide
propagation paths between logic circuits for the pulses propagating
between logic circuits.
For example, in an array of at least four tile circuits the interconnect
resource circuits may collectively provide a first propagation path
between adjacent logic circuits in the array for pulses to propagate in
a first direction only and a second transverse propagation path for
pulses to propagate in a second direction only.
BRIEF DESCRIPTION OF THE ACCOMPANYING DIAGRAMS
The invention will now further be described, by way of example only,
with reference to the accompanying diagrams wherein:
figure 1 is a basic block diagram of a configurable logic circuit
according to the invention;
figure 2 is a block diagram of a programmable gate array
comprising one each of four basic tiles, each comprising a
configurable logic circuit implemented by rapid single flux
quantum circuits;
figure 3(a) is a basic Josephson junction circuit diagram of a rapid
single flux quantum memory cell;
figure 3(b) is a schematic representation of the cell;
figure 3(c) is a timing diagram of the operation of the cell;
figure 4(a) is a more detailed diagram of an input selector for the
block in figure 1 ;
figure 4(b) is a schematic representation of the input selector;
figure 5(a) is a more detailed diagram of an address decoder for a
lookup table for the circuit in figure 1 ;
figure 5(b) is a schematic representation of the address decoder;
figure 6(a) is a more detailed diagram of the lookup table for the
circuit in figure 1 ;
figure 6(b) is a schematic representation of the lookup table;
figure 7(a) is a more detailed diagram of an output selector for the
circuit in figure 1 ;
figure 7(b) is a schematic representation of the output selector;
figure 8(a) is a more detailed diagram of a switch box for a tile in
figure 2;
figure 8(b) is a schematic representation of the switch box;
figure 9(a) is a more detailed diagram of an interconnect resource
circuit for the tile in figure 2;
figure 9(b) is a schematic representation of the interconnect
resource;
figure 10 is a schematic representation of the upper right hand tile
in figure 2; and
figure 1 1 is another representation of the tile in figures 2 and 9 in
the form of a basic arrangement of rapid single flux
quantum memory cells.
DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
A block diagram of a configurable logic block (CLB) circuit according to
the invention is generally designated by the reference numeral 10 in
figure 1 .
The circuit 10 comprises a first input arrangement 12, comprising
inputs INOO to IN03, a second input arrangement 14 comprising inputs
IN 10 to IN 13, an input selector 16, an address decoder 18, a lookup
table (LUT) 20, an output selector 22, a first output arrangement 24
and a second output arrangement 26. A clock 28 is connected to the
address decoder 18. In embodiments wherein a plurality of similar
circuits are used, the clock 28 may also be connected to the address
decoders of those circuits, so that it constitutes a common or global
clock.
When the circuit 10 is implemented with superconducting rapid single
flux quantum (RSFQ) circuits which is a pulse based logic technology,
the circuit 10 may form part of each of tile circuits 30.1 to 30.4
shown in figure 2. As shown in figure 1 , the circuit may be provided in
the form of a block wherein the first input arrangement 12 and first
output arrangement 24 are provided on one side 32 of rectangular
block 10 and the second input arrangement 14 and second output
arrangement 26 are provided on a second, but opposite side of the
block. This is to facilitate routing of RSFQ pulses between tiles 30.1
to 30.4 in figure 2, due to the fact that RSFQ pulses propagate in one
direction only, namely that indicated by the arrows in figures 1 and 2.
The circuit 10 may form part of a programmable gate array (PGA) of
the kind which comprises an array of uncommitted configurable logic
circuits that can be interconnected in a selected manner. An
interconnect resource facilitates this selected connection.
The RSFQ PGA array 40 in figure 2 comprises four tiles 30.1 to 30.4
each comprising the basic circuit 10 but differing from one another in
the configuration of interconnect resources 36.1 to 36.4 respectively,
adjacent the blocks. The interconnect resources collectively provide a
first propagation path P1 between adjacent blocks for pulses to
propagate in a first direction y only and a second transverse
propagation path P2 for pulses to propagate in a second direction z
only. Each tile further comprises a switch box 38.1 to 38.4
respectively. Any plurality of such tiles may be used in an RSFQ PGA
array.
A basic element of the circuit 10 is a non-destructive read out (NDRO)
memory cell 31 shown in figure 3(a). A schematic diagram of the
cell which is also used in other circuits described in this specification
is shown in figure 3(b). The pin description for the cell is as follows:-
Pin Description
S Set pin
C Clear pin
A Read Pin
S' Set repeat
C Clear repeat
F Output
X Programme select*
X' Programme repeat* * Voltage state logic
The selectable pin X allows row selection of the cell 31 in an array.
The set repeat pin S' and clear repeat pin C allow for vertical
alignment by repeating programming instructions. The Josephson
junctions J1 and J2 in figure 3(a) are responsible for the repeating of
the set S and clear C signals. The X line 33 biases two resistors that
allow for the setting and clearing of the cell 31 . The logic operation of
the cell is as follows. When the cell is set and pin A is pulsed, then
pin F pulses. Otherwise there will be no pulse at pin F. Referring to
the timing diagram in figure 3(c), the X line is made high at 35 which
enables the cell to be set by S pulse 37. At 39, pin A is pulsed and
the state of the cell is reflected at output F as shown at 41 in figure
3(c). Pulse 43 on line C clears the cell, so that when pin A is pulsed
again at 45, output F remains clear. A pulse at output F during a
clock period would indicate a logic one while the absence of a pulse
during the clock period would indicate a logic zero.
A more detailed diagram of an RSFQ input selector 16 is shown in
figure 4(a). The input selector comprises eight (8) of the
aforementioned non-destructive read out (NDRO) memory cells
designated 42.0 to 42.7. The eight inputs INOO to IN03 and IN10 to
IN 13 are each connected to a respective pin designated A in figure
4(a) of memory cells 42.0 to 42.7. The outputs of adjacent pairs of
cells are connected to known confluence buffers 44.0 to 44.3. The
outputs of the buffers are designated 46.0 to 46.3 respectively.
Depending on a programmed state of the cells, input pulses will
propagate to the confluence buffers to be combined thereby. As seen
from figure 4(a), corresponding inputs of input arrangements 12 and
14 are discriminated between. A schematic diagram of the input
selector is shown in figure 4(b).
A more detailed diagram of the address decoder 18 for the LUT 20 is
shown in figure 5(a). A schematic representation of the decoder 18 is
shown in figure 5(b). As shown in figure 5(a), the decoder decodes
four inputs 48.0 to 48.3 connected to the aforementioned outputs
46.0 to 46.3, to select one of sixteen (16) address decoder outputs
50.0 to 50.15.
Signals on the inputs 48.0 to 48.3 are split by respective splitters
52.0 to 52.3 and fed into buffers 55.0 to 55.3 and inverters 54.0 to
54.3 also connected to clock 28 to synchronize the circuit. The
outputs of the buffers and inverters are connected to eight splitters
56.0 to 56.7. Hence, for each signal on the inputs 48.0 to 48.3, a
buffering and an inversion of its value is made. For each clock pulse an
output of each buffer and each inverter is splitted eight ways. The
outputs of the splitters are directed to AND gates 58.0 to 58.15, to
provide the aforementioned outputs 50.0 to 50.15 of decoder 18.
As shown in figure 6(a) the LUT 20 comprises an array of sixteen
memory cells 60.0 to 60.1 5 in two rows of eight each. A value
stored in the LUT is read by pulsing respective A pins of the cells with
signals on outputs 50.1 to 50.15 of the address decoder 18. The
delay between the read pulse and the value at output 62 is in the
order of 30ps. A schematic diagram of the LUT 20 is shown in figure
6(b).
The output selector 22 is shown in more detail in figure 7(a) and a
schematic diagram of the output selector is shown in figure 7(b). The
output selector comprises an eight-way splitter 64 connected to the
output 62 of the LUT 20. The splitter is connected to eight memory
cells 66.0 to 66.7 which determine the way in which they connect to
the interconnect resource 36.2. The outputs of the output selector are
shown at 68 in figure 7(b).
A switch box 38.2 is shown in more detail in figure 8(a) and a
schematic diagram thereof is shown in figure 8(b). The switch box
38.2 comprises sixteen memory cells 70.0 to 70.15 interconnected as
shown in figure 8(a). Dictated by the uni-directionality of the
propagation of RSFQ pulses, switch boxes 38.1 to 38.4 (shown in
figure 2) have different configurations.
A more detailed diagram of interconnect resource 36.2 is shown in
figure 9(a). The resource comprises confluence buffers 72.0 to 72.3,
buffered Josephson transmission lines (JTL) 74.0 to 74.3, splitters
76.0 to 76.3, confluence buffers 78.0 to 78.3, JTL's 80.0 to 80.3
and splitters 82.0 to 82.3. The interconnect resource allows for the
uni-directional propagation of pulses between the blocks in figure 2 in
the direction indicated by the arrows.
A schematic diagram of the tile 30.2 in figure 2 is shown in figure 10
together with the required interconnections between constituent parts
thereof. The difference between this tile and the other tiles 30.1 , 30.3
and 30.4 is the orientation of the switch boxes and interconnect
resources.
A more detailed RSFQ implementation of tile 30.2 is shown in figure
1 1 . The tile comprises a plurality of memory cells 31 as hereinbefore
described. Programming lines 92 into the tile are repeated at 94.
Input/outputs are provided on all four sides of the tile. The speed at
which an RSFQ array works, is determined by the time delay involved
to perform one logic operation. For this circuit, operation speed is
determined by the time for a pulse of this pulse based technology to
propagate from the input selector 16 to the output selector 22.
Simulation results indicate a time of in the order of 135ps and less. It
is anticipated that the block and array according to the invention may
operate at speeds of an order faster than arrays constituted by the
aforementioned semiconductor voltage state logic circuits.
Programming of the RSFQ Programmable Gate Array (RSFQPGA) is as
follows.
The first step for the designing a circuit for the RSFQPGA is to
conceptualise a functional circuit. The circuit is then captured as a
schematic entry; by entering a VHDL description; or specifying
Boolean expressions. This is achieved using proprietary computer
aided design (CAD) tools. With these tools, the circuit descriptions are
then translated into standard Boolean expressions and optimised to
minimize circuit area and maximize the logic circuit speed.
The optimised Boolean expressions are technology mapped to fit into
the logic blocks of the RSFQPGA. This is done by selecting pieces of a
circuit network that can be implemented by one of the available
physical CLBs. This implies the memory of the Input Selector, LUT,
Output Selector and any other additional circuitry to be added to the
RSFQPGA to increase its functionality.
A placement stage determines where to place each mapped block
within the physical RSFQPGA to minimize interconnecting path
lengths. This stage merely chooses physical CLBs to allocate
previously defined CLBs from the mapping stage.
A routing stage assigns the Interconnect Resources to set the required
connections among the logic blocks. Due to the complexity of this
routing problem a three step "divide and conquer" strategy is used,
namely: Partitioning, Global Routing and Detailed Routing.
The RSFQPGA would be programmed using a serial communication
interface from the design platform computer operating the CAD tools.
Internal to the RSFQPGA, serial data will be loaded by a RSFQ shift
register circuit arrangement not detailed here, and decoded further to
set and clear the memory of the CLBs in the array. Included to the
RSFQPGA would be the ability to arrange the devices in an in-line
manner allowing for multiple units to be programmed simultaneously.
Finally, the complete RSFQPGA would have a programming and
running state. Switching between these states would start and stop
the global clock within the RSFQPGA that is used to synchronize the
CLBs.
Claims
1. A configurable logic circuit comprising:
an input arrangement comprising a plurality of inputs;
an output arrangement comprising a plurality of outputs;
- configurable logic circuitry connected between the input
arrangement and the output arrangement;
the logic circuitry comprising configurable rapid single flux
quantum superconducting circuitry to perform logic
operations on signals at the input arrangement utilizing
propagating pulses of the rapid single flux quantum
circuitry.
2. A configurable logic circuit as claimed in claim 1 wherein the
rapid single flux quantum circuitry is programmable.
3. A configurable logic circuit as claimed in claim 1 or claim 2
wherein the logic circuitry comprises a lookup table comprising
configurable rapid single flux quantum superconducting
circuitry.
4. A configurable logic circuit as claimed in claim 3 wherein an
input selector circuit for cooperating with the input arrangement and an address decoder circuit for the lookup table are
connected between the input arrangement and the lookup table.
5. A configurable logic circuit as claimed in claim 3 or claim 4
wherein an output selector circuit for cooperating with the
output arrangement is connected between the lookup table and
the output arrangement.
6. A configurable logic circuit as claimed in claim 4 or claim 5
wherein the address decoder circuit is connected to a clock
circuit.
7. A configurable logic circuit as claimed in any one of the
preceding claims wherein the circuit is arranged in a block,
wherein at least a first part of the input arrangement and at
least a first part of the output arrangement are provided on a
first side of the block.
8. A configurable logic circuit as claimed in claim 7 wherein
another part of the input arrangement and another part of the
output arrangement are provided on a second side of the block.
9. A configurable logic circuit as claimed in claim 8 wherein the
block is rectangular in configuration and wherein the first side
and the second side are opposed to one another.
10. A programmable gate array comprising a configurable logic
circuit as claimed in any one of claims 1 to 9.
1 1 . A programmable tile circuit comprising a configurable logic
circuit as claimed in any one of claims 1 to 9 and an
interconnect resource circuit for connecting the logic circuit to
another logic circuit.
12. A programmable tile circuit as claimed in claim 1 1 wherein the
interconnect resource circuit causes pulses to propagate in one
direction only.
13. An array of tile circuits comprising a plurality of tile circuits as
claimed in claim 1 1 wherein respective interconnect circuits
collectively provide propagation paths between logic circuits for
the pulses propagating between logic circuits.
4. An array of at least four tile circuits as claimed in claim 1 1
wherein the interconnect resource circuits collectively provide a
first propagation path between adjacent logic circuits in the
array for pulses to propagate in a first direction only and a
second transverse propagation path for pulses to propagate in a
second direction only.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ZA200101657 | 2001-02-28 | ||
ZA2001/1657 | 2001-02-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002069498A2 true WO2002069498A2 (en) | 2002-09-06 |
WO2002069498A3 WO2002069498A3 (en) | 2004-02-12 |
Family
ID=25589083
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/ZA2002/000023 WO2002069498A2 (en) | 2001-02-28 | 2002-02-28 | Rapid single flux quantum programmable gate array |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2002069498A2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110167241A1 (en) * | 2006-02-23 | 2011-07-07 | Hypres, Inc. | Superconducting circuit for high-speed lookup table |
US9520180B1 (en) | 2014-03-11 | 2016-12-13 | Hypres, Inc. | System and method for cryogenic hybrid technology computing and memory |
US9712172B2 (en) | 2015-10-07 | 2017-07-18 | Microsoft Technology Licensing, Llc | Devices with an array of superconducting logic cells |
WO2018203942A3 (en) * | 2017-02-04 | 2019-03-21 | Microsoft Technology Licensing, Llc | Superconducting circuits based devices and methods |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5233242A (en) * | 1991-08-14 | 1993-08-03 | Westinghouse Electric Corp. | Superconducting push-pull flux quantum gate array cells |
JPH08148989A (en) * | 1994-11-18 | 1996-06-07 | Hitachi Ltd | Superconducting FPGA device |
US5629889A (en) * | 1995-12-14 | 1997-05-13 | Nec Research Institute, Inc. | Superconducting fault-tolerant programmable memory cell incorporating Josephson junctions |
-
2002
- 2002-02-28 WO PCT/ZA2002/000023 patent/WO2002069498A2/en not_active Application Discontinuation
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110167241A1 (en) * | 2006-02-23 | 2011-07-07 | Hypres, Inc. | Superconducting circuit for high-speed lookup table |
US9520180B1 (en) | 2014-03-11 | 2016-12-13 | Hypres, Inc. | System and method for cryogenic hybrid technology computing and memory |
US9887000B1 (en) | 2014-03-11 | 2018-02-06 | Hypres, Inc. | System and method for cryogenic hybrid technology computing and memory |
US10460796B1 (en) | 2014-03-11 | 2019-10-29 | SeeQC, Inc. | System and method for cryogenic hybrid technology computing and memory |
US10950299B1 (en) | 2014-03-11 | 2021-03-16 | SeeQC, Inc. | System and method for cryogenic hybrid technology computing and memory |
US11406583B1 (en) | 2014-03-11 | 2022-08-09 | SeeQC, Inc. | System and method for cryogenic hybrid technology computing and memory |
US11717475B1 (en) | 2014-03-11 | 2023-08-08 | SeeQC, Inc. | System and method for cryogenic hybrid technology computing and memory |
US9712172B2 (en) | 2015-10-07 | 2017-07-18 | Microsoft Technology Licensing, Llc | Devices with an array of superconducting logic cells |
WO2018203942A3 (en) * | 2017-02-04 | 2019-03-21 | Microsoft Technology Licensing, Llc | Superconducting circuits based devices and methods |
US10411713B2 (en) | 2017-02-04 | 2019-09-10 | Microsoft Technology Licensing, Llc | Superconducting circuits based devices and methods |
CN110235368A (en) * | 2017-02-04 | 2019-09-13 | 微软技术许可有限责任公司 | Devices and methods based on superconducting circuits |
Also Published As
Publication number | Publication date |
---|---|
WO2002069498A3 (en) | 2004-02-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0746103B1 (en) | Programmable logic array integrated circuits | |
US5436575A (en) | Programmable logic array integrated circuits | |
US6069490A (en) | Routing architecture using a direct connect routing mesh | |
US6359469B1 (en) | Logic element for a programmable logic integrated circuit | |
US7839167B2 (en) | Interconnection and input/output resources for programmable logic integrated circuit devices | |
US6392438B1 (en) | Programmable logic array integrated circuit devices | |
US6636070B1 (en) | Driver circuitry for programmable logic devices with hierarchical interconnection resources | |
US5537057A (en) | Programmable logic array device with grouped logic regions and three types of conductors | |
EP0340890A2 (en) | Programmable logic device with array blocks connected via a programmable interconnect array | |
US6882176B1 (en) | High-performance programmable logic architecture | |
US6255847B1 (en) | Programmable logic device | |
US8390321B2 (en) | Reconfigurable logical circuit | |
US7634753B2 (en) | System for signal routing line aggregation in a field-programmable gate array | |
Chow et al. | A 1.2 m CMOS FPGA using cascaded logic blocks and segmented routing | |
WO2002069498A2 (en) | Rapid single flux quantum programmable gate array | |
US8120382B2 (en) | Programmable integrated circuit with mirrored interconnect structure | |
ZA200207825B (en) | Rapid single flux quantum programmable gate array. | |
US6759870B2 (en) | Programmable logic array integrated circuits | |
US6429681B1 (en) | Programmable logic device routing architecture to facilitate register re-timing | |
US6262595B1 (en) | High-speed programmable interconnect | |
US6980029B1 (en) | Programmable integrated circuit architecture | |
JPH02122544A (en) | Standard cell output driver connection system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 2002/07825 Country of ref document: ZA Ref document number: 200207825 Country of ref document: ZA |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
122 | Ep: pct application non-entry in european phase | ||
NENP | Non-entry into the national phase |
Ref country code: JP |
|
WWW | Wipo information: withdrawn in national office |
Country of ref document: JP |